Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1 | /* |
| 2 | * sata_mv.c - Marvell SATA support |
| 3 | * |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 4 | * Copyright 2008: Marvell Corporation, all rights reserved. |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 5 | * Copyright 2005: EMC Corporation, all rights reserved. |
Jeff Garzik | e2b1be5 | 2005-11-18 14:04:23 -0500 | [diff] [blame] | 6 | * Copyright 2005 Red Hat, Inc. All rights reserved. |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 7 | * |
| 8 | * Please ALWAYS copy linux-ide@vger.kernel.org on emails. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | */ |
| 24 | |
Jeff Garzik | 4a05e20 | 2007-05-24 23:40:15 -0400 | [diff] [blame] | 25 | /* |
| 26 | sata_mv TODO list: |
| 27 | |
| 28 | 1) Needs a full errata audit for all chipsets. I implemented most |
| 29 | of the errata workarounds found in the Marvell vendor driver, but |
| 30 | I distinctly remember a couple workarounds (one related to PCI-X) |
| 31 | are still needed. |
| 32 | |
Mark Lord | 1fd2e1c | 2008-01-26 18:33:59 -0500 | [diff] [blame] | 33 | 2) Improve/fix IRQ and error handling sequences. |
| 34 | |
| 35 | 3) ATAPI support (Marvell claims the 60xx/70xx chips can do it). |
| 36 | |
| 37 | 4) Think about TCQ support here, and for libata in general |
| 38 | with controllers that suppport it via host-queuing hardware |
| 39 | (a software-only implementation could be a nightmare). |
Jeff Garzik | 4a05e20 | 2007-05-24 23:40:15 -0400 | [diff] [blame] | 40 | |
| 41 | 5) Investigate problems with PCI Message Signalled Interrupts (MSI). |
| 42 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 43 | 6) Cache frequently-accessed registers in mv_port_priv to reduce overhead. |
Jeff Garzik | 4a05e20 | 2007-05-24 23:40:15 -0400 | [diff] [blame] | 44 | |
Mark Lord | 40f0bc2 | 2008-04-16 14:57:25 -0400 | [diff] [blame] | 45 | 7) Fix/reenable hot plug/unplug (should happen as a side-effect of (2) above). |
Jeff Garzik | 4a05e20 | 2007-05-24 23:40:15 -0400 | [diff] [blame] | 46 | |
Jeff Garzik | 4a05e20 | 2007-05-24 23:40:15 -0400 | [diff] [blame] | 47 | 8) Develop a low-power-consumption strategy, and implement it. |
| 48 | |
| 49 | 9) [Experiment, low priority] See if ATAPI can be supported using |
| 50 | "unknown FIS" or "vendor-specific FIS" support, or something creative |
| 51 | like that. |
| 52 | |
| 53 | 10) [Experiment, low priority] Investigate interrupt coalescing. |
| 54 | Quite often, especially with PCI Message Signalled Interrupts (MSI), |
| 55 | the overhead reduced by interrupt mitigation is quite often not |
| 56 | worth the latency cost. |
| 57 | |
| 58 | 11) [Experiment, Marvell value added] Is it possible to use target |
| 59 | mode to cross-connect two Linux boxes with Marvell cards? If so, |
| 60 | creating LibATA target mode support would be very interesting. |
| 61 | |
| 62 | Target mode, for those without docs, is the ability to directly |
| 63 | connect two SATA controllers. |
| 64 | |
Jeff Garzik | 4a05e20 | 2007-05-24 23:40:15 -0400 | [diff] [blame] | 65 | */ |
| 66 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 67 | #include <linux/kernel.h> |
| 68 | #include <linux/module.h> |
| 69 | #include <linux/pci.h> |
| 70 | #include <linux/init.h> |
| 71 | #include <linux/blkdev.h> |
| 72 | #include <linux/delay.h> |
| 73 | #include <linux/interrupt.h> |
Andrew Morton | 8d8b600 | 2008-02-04 23:43:44 -0800 | [diff] [blame] | 74 | #include <linux/dmapool.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 75 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 76 | #include <linux/device.h> |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 77 | #include <linux/platform_device.h> |
| 78 | #include <linux/ata_platform.h> |
Lennert Buytenhek | 15a3263 | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 79 | #include <linux/mbus.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 80 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 81 | #include <scsi/scsi_cmnd.h> |
Jeff Garzik | 6c08772 | 2007-10-12 00:16:23 -0400 | [diff] [blame] | 82 | #include <scsi/scsi_device.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 83 | #include <linux/libata.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 84 | |
| 85 | #define DRV_NAME "sata_mv" |
Mark Lord | 1fd2e1c | 2008-01-26 18:33:59 -0500 | [diff] [blame] | 86 | #define DRV_VERSION "1.20" |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 87 | |
| 88 | enum { |
| 89 | /* BAR's are enumerated in terms of pci_resource_start() terms */ |
| 90 | MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ |
| 91 | MV_IO_BAR = 2, /* offset 0x18: IO space */ |
| 92 | MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ |
| 93 | |
| 94 | MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ |
| 95 | MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ |
| 96 | |
| 97 | MV_PCI_REG_BASE = 0, |
| 98 | MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ |
Mark Lord | 615ab95 | 2006-05-19 16:24:56 -0400 | [diff] [blame] | 99 | MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), |
| 100 | MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), |
| 101 | MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), |
| 102 | MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), |
| 103 | MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), |
| 104 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 105 | MV_SATAHC0_REG_BASE = 0x20000, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 106 | MV_FLASH_CTL = 0x1046c, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 107 | MV_GPIO_PORT_CTL = 0x104f0, |
| 108 | MV_RESET_CFG = 0x180d8, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 109 | |
| 110 | MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, |
| 111 | MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, |
| 112 | MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ |
| 113 | MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, |
| 114 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 115 | MV_MAX_Q_DEPTH = 32, |
| 116 | MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, |
| 117 | |
| 118 | /* CRQB needs alignment on a 1KB boundary. Size == 1KB |
| 119 | * CRPB needs alignment on a 256B boundary. Size == 256B |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 120 | * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B |
| 121 | */ |
| 122 | MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), |
| 123 | MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 124 | MV_MAX_SG_CT = 256, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 125 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 126 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 127 | /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 128 | MV_PORT_HC_SHIFT = 2, |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 129 | MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ |
| 130 | /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ |
| 131 | MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 132 | |
| 133 | /* Host Flags */ |
| 134 | MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ |
| 135 | MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 136 | /* SoC integrated controllers, no PCI interface */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 137 | MV_FLAG_SOC = (1 << 28), |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 138 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 139 | MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 140 | ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | |
| 141 | ATA_FLAG_PIO_POLLING, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 142 | MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 143 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 144 | CRQB_FLAG_READ = (1 << 0), |
| 145 | CRQB_TAG_SHIFT = 1, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 146 | CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 147 | CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 148 | CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 149 | CRQB_CMD_ADDR_SHIFT = 8, |
| 150 | CRQB_CMD_CS = (0x2 << 11), |
| 151 | CRQB_CMD_LAST = (1 << 15), |
| 152 | |
| 153 | CRPB_FLAG_STATUS_SHIFT = 8, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 154 | CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ |
| 155 | CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 156 | |
| 157 | EPRD_FLAG_END_OF_TBL = (1 << 31), |
| 158 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 159 | /* PCI interface registers */ |
| 160 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 161 | PCI_COMMAND_OFS = 0xc00, |
| 162 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 163 | PCI_MAIN_CMD_STS_OFS = 0xd30, |
| 164 | STOP_PCI_MASTER = (1 << 2), |
| 165 | PCI_MASTER_EMPTY = (1 << 3), |
| 166 | GLOB_SFT_RST = (1 << 4), |
| 167 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 168 | MV_PCI_MODE = 0xd00, |
| 169 | MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, |
| 170 | MV_PCI_DISC_TIMER = 0xd04, |
| 171 | MV_PCI_MSI_TRIGGER = 0xc38, |
| 172 | MV_PCI_SERR_MASK = 0xc28, |
| 173 | MV_PCI_XBAR_TMOUT = 0x1d04, |
| 174 | MV_PCI_ERR_LOW_ADDRESS = 0x1d40, |
| 175 | MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, |
| 176 | MV_PCI_ERR_ATTRIBUTE = 0x1d48, |
| 177 | MV_PCI_ERR_COMMAND = 0x1d50, |
| 178 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 179 | PCI_IRQ_CAUSE_OFS = 0x1d58, |
| 180 | PCI_IRQ_MASK_OFS = 0x1d5c, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 181 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ |
| 182 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 183 | PCIE_IRQ_CAUSE_OFS = 0x1900, |
| 184 | PCIE_IRQ_MASK_OFS = 0x1910, |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 185 | PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 186 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 187 | HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, |
| 188 | HC_MAIN_IRQ_MASK_OFS = 0x1d64, |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 189 | HC_SOC_MAIN_IRQ_CAUSE_OFS = 0x20020, |
| 190 | HC_SOC_MAIN_IRQ_MASK_OFS = 0x20024, |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 191 | ERR_IRQ = (1 << 0), /* shift by port # */ |
| 192 | DONE_IRQ = (1 << 1), /* shift by port # */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 193 | HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ |
| 194 | HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ |
| 195 | PCI_ERR = (1 << 18), |
| 196 | TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ |
| 197 | TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 198 | PORTS_0_3_COAL_DONE = (1 << 8), |
| 199 | PORTS_4_7_COAL_DONE = (1 << 17), |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 200 | PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ |
| 201 | GPIO_INT = (1 << 22), |
| 202 | SELF_INT = (1 << 23), |
| 203 | TWSI_INT = (1 << 24), |
| 204 | HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 205 | HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 206 | HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 207 | HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 208 | PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | |
| 209 | HC_MAIN_RSVD), |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 210 | HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | |
| 211 | HC_MAIN_RSVD_5), |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 212 | HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC), |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 213 | |
| 214 | /* SATAHC registers */ |
| 215 | HC_CFG_OFS = 0, |
| 216 | |
| 217 | HC_IRQ_CAUSE_OFS = 0x14, |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 218 | DMA_IRQ = (1 << 0), /* shift by port # */ |
| 219 | HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 220 | DEV_IRQ = (1 << 8), /* shift by port # */ |
| 221 | |
| 222 | /* Shadow block registers */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 223 | SHD_BLK_OFS = 0x100, |
| 224 | SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 225 | |
| 226 | /* SATA registers */ |
| 227 | SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ |
| 228 | SATA_ACTIVE_OFS = 0x350, |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 229 | SATA_FIS_IRQ_CAUSE_OFS = 0x364, |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 230 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 231 | LTMODE_OFS = 0x30c, |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 232 | LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ |
| 233 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 234 | PHY_MODE3 = 0x310, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 235 | PHY_MODE4 = 0x314, |
| 236 | PHY_MODE2 = 0x330, |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 237 | SATA_IFCTL_OFS = 0x344, |
| 238 | SATA_IFSTAT_OFS = 0x34c, |
| 239 | VENDOR_UNIQUE_FIS_OFS = 0x35c, |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 240 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 241 | FIS_CFG_OFS = 0x360, |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 242 | FIS_CFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ |
| 243 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 244 | MV5_PHY_MODE = 0x74, |
| 245 | MV5_LT_MODE = 0x30, |
| 246 | MV5_PHY_CTL = 0x0C, |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 247 | SATA_INTERFACE_CFG = 0x050, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 248 | |
| 249 | MV_M2_PREAMP_MASK = 0x7e0, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 250 | |
| 251 | /* Port registers */ |
| 252 | EDMA_CFG_OFS = 0, |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 253 | EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ |
| 254 | EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ |
| 255 | EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ |
| 256 | EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ |
| 257 | EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 258 | EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ |
| 259 | EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 260 | |
| 261 | EDMA_ERR_IRQ_CAUSE_OFS = 0x8, |
| 262 | EDMA_ERR_IRQ_MASK_OFS = 0xc, |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 263 | EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ |
| 264 | EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ |
| 265 | EDMA_ERR_DEV = (1 << 2), /* device error */ |
| 266 | EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ |
| 267 | EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ |
| 268 | EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 269 | EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ |
| 270 | EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 271 | EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 272 | EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 273 | EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ |
| 274 | EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ |
| 275 | EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ |
| 276 | EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 277 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 278 | EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 279 | EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ |
| 280 | EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ |
| 281 | EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ |
| 282 | EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ |
| 283 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 284 | EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 285 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 286 | EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 287 | EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ |
| 288 | EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ |
| 289 | EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ |
| 290 | EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ |
| 291 | EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ |
| 292 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 293 | EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 294 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 295 | EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 296 | EDMA_ERR_OVERRUN_5 = (1 << 5), |
| 297 | EDMA_ERR_UNDERRUN_5 = (1 << 6), |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 298 | |
| 299 | EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | |
| 300 | EDMA_ERR_LNK_CTRL_RX_1 | |
| 301 | EDMA_ERR_LNK_CTRL_RX_3 | |
Mark Lord | 40f0bc2 | 2008-04-16 14:57:25 -0400 | [diff] [blame] | 302 | EDMA_ERR_LNK_CTRL_TX | |
| 303 | /* temporary, until we fix hotplug: */ |
| 304 | (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON), |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 305 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 306 | EDMA_EH_FREEZE = EDMA_ERR_D_PAR | |
| 307 | EDMA_ERR_PRD_PAR | |
| 308 | EDMA_ERR_DEV_DCON | |
| 309 | EDMA_ERR_DEV_CON | |
| 310 | EDMA_ERR_SERR | |
| 311 | EDMA_ERR_SELF_DIS | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 312 | EDMA_ERR_CRQB_PAR | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 313 | EDMA_ERR_CRPB_PAR | |
| 314 | EDMA_ERR_INTRL_PAR | |
| 315 | EDMA_ERR_IORDY | |
| 316 | EDMA_ERR_LNK_CTRL_RX_2 | |
| 317 | EDMA_ERR_LNK_DATA_RX | |
| 318 | EDMA_ERR_LNK_DATA_TX | |
| 319 | EDMA_ERR_TRANS_PROTO, |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 320 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 321 | EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | |
| 322 | EDMA_ERR_PRD_PAR | |
| 323 | EDMA_ERR_DEV_DCON | |
| 324 | EDMA_ERR_DEV_CON | |
| 325 | EDMA_ERR_OVERRUN_5 | |
| 326 | EDMA_ERR_UNDERRUN_5 | |
| 327 | EDMA_ERR_SELF_DIS_5 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 328 | EDMA_ERR_CRQB_PAR | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 329 | EDMA_ERR_CRPB_PAR | |
| 330 | EDMA_ERR_INTRL_PAR | |
| 331 | EDMA_ERR_IORDY, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 332 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 333 | EDMA_REQ_Q_BASE_HI_OFS = 0x10, |
| 334 | EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 335 | |
| 336 | EDMA_REQ_Q_OUT_PTR_OFS = 0x18, |
| 337 | EDMA_REQ_Q_PTR_SHIFT = 5, |
| 338 | |
| 339 | EDMA_RSP_Q_BASE_HI_OFS = 0x1c, |
| 340 | EDMA_RSP_Q_IN_PTR_OFS = 0x20, |
| 341 | EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 342 | EDMA_RSP_Q_PTR_SHIFT = 3, |
| 343 | |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 344 | EDMA_CMD_OFS = 0x28, /* EDMA command register */ |
| 345 | EDMA_EN = (1 << 0), /* enable EDMA */ |
| 346 | EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ |
| 347 | ATA_RST = (1 << 2), /* reset trans/link/phy */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 348 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 349 | EDMA_IORDY_TMOUT = 0x34, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 350 | EDMA_ARB_CFG = 0x38, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 351 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 352 | GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */ |
| 353 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 354 | /* Host private flags (hp_flags) */ |
| 355 | MV_HP_FLAG_MSI = (1 << 0), |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 356 | MV_HP_ERRATA_50XXB0 = (1 << 1), |
| 357 | MV_HP_ERRATA_50XXB2 = (1 << 2), |
| 358 | MV_HP_ERRATA_60X1B2 = (1 << 3), |
| 359 | MV_HP_ERRATA_60X1C0 = (1 << 4), |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 360 | MV_HP_ERRATA_XX42A0 = (1 << 5), |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 361 | MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ |
| 362 | MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ |
| 363 | MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 364 | MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 365 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 366 | /* Port private flags (pp_flags) */ |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 367 | MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ |
Mark Lord | 7210916 | 2008-01-26 18:31:33 -0500 | [diff] [blame] | 368 | MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 369 | }; |
| 370 | |
Jeff Garzik | ee9ccdf | 2007-07-12 15:51:22 -0400 | [diff] [blame] | 371 | #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) |
| 372 | #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 373 | #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 374 | #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 375 | |
Lennert Buytenhek | 15a3263 | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 376 | #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) |
| 377 | #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) |
| 378 | |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 379 | enum { |
Jeff Garzik | baf14aa | 2007-10-09 13:51:57 -0400 | [diff] [blame] | 380 | /* DMA boundary 0xffff is required by the s/g splitting |
| 381 | * we need on /length/ in mv_fill-sg(). |
| 382 | */ |
| 383 | MV_DMA_BOUNDARY = 0xffffU, |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 384 | |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 385 | /* mask of register bits containing lower 32 bits |
| 386 | * of EDMA request queue DMA address |
| 387 | */ |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 388 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, |
| 389 | |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 390 | /* ditto, for response queue */ |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 391 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, |
| 392 | }; |
| 393 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 394 | enum chip_type { |
| 395 | chip_504x, |
| 396 | chip_508x, |
| 397 | chip_5080, |
| 398 | chip_604x, |
| 399 | chip_608x, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 400 | chip_6042, |
| 401 | chip_7042, |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 402 | chip_soc, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 403 | }; |
| 404 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 405 | /* Command ReQuest Block: 32B */ |
| 406 | struct mv_crqb { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 407 | __le32 sg_addr; |
| 408 | __le32 sg_addr_hi; |
| 409 | __le16 ctrl_flags; |
| 410 | __le16 ata_cmd[11]; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 411 | }; |
| 412 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 413 | struct mv_crqb_iie { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 414 | __le32 addr; |
| 415 | __le32 addr_hi; |
| 416 | __le32 flags; |
| 417 | __le32 len; |
| 418 | __le32 ata_cmd[4]; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 419 | }; |
| 420 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 421 | /* Command ResPonse Block: 8B */ |
| 422 | struct mv_crpb { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 423 | __le16 id; |
| 424 | __le16 flags; |
| 425 | __le32 tmstmp; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 426 | }; |
| 427 | |
| 428 | /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ |
| 429 | struct mv_sg { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 430 | __le32 addr; |
| 431 | __le32 flags_size; |
| 432 | __le32 addr_hi; |
| 433 | __le32 reserved; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 434 | }; |
| 435 | |
| 436 | struct mv_port_priv { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 437 | struct mv_crqb *crqb; |
| 438 | dma_addr_t crqb_dma; |
| 439 | struct mv_crpb *crpb; |
| 440 | dma_addr_t crpb_dma; |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 441 | struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; |
| 442 | dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 443 | |
| 444 | unsigned int req_idx; |
| 445 | unsigned int resp_idx; |
| 446 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 447 | u32 pp_flags; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 448 | }; |
| 449 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 450 | struct mv_port_signal { |
| 451 | u32 amps; |
| 452 | u32 pre; |
| 453 | }; |
| 454 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 455 | struct mv_host_priv { |
| 456 | u32 hp_flags; |
| 457 | struct mv_port_signal signal[8]; |
| 458 | const struct mv_hw_ops *ops; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 459 | int n_ports; |
| 460 | void __iomem *base; |
| 461 | void __iomem *main_cause_reg_addr; |
| 462 | void __iomem *main_mask_reg_addr; |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 463 | u32 irq_cause_ofs; |
| 464 | u32 irq_mask_ofs; |
| 465 | u32 unmask_all_irqs; |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 466 | /* |
| 467 | * These consistent DMA memory pools give us guaranteed |
| 468 | * alignment for hardware-accessed data structures, |
| 469 | * and less memory waste in accomplishing the alignment. |
| 470 | */ |
| 471 | struct dma_pool *crqb_pool; |
| 472 | struct dma_pool *crpb_pool; |
| 473 | struct dma_pool *sg_tbl_pool; |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 474 | }; |
| 475 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 476 | struct mv_hw_ops { |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 477 | void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 478 | unsigned int port); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 479 | void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 480 | void (*read_preamp)(struct mv_host_priv *hpriv, int idx, |
| 481 | void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 482 | int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 483 | unsigned int n_hc); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 484 | void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 485 | void (*reset_bus)(struct ata_host *host, void __iomem *mmio); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 486 | }; |
| 487 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 488 | static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); |
| 489 | static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); |
| 490 | static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); |
| 491 | static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 492 | static int mv_port_start(struct ata_port *ap); |
| 493 | static void mv_port_stop(struct ata_port *ap); |
| 494 | static void mv_qc_prep(struct ata_queued_cmd *qc); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 495 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 496 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 497 | static int mv_hardreset(struct ata_link *link, unsigned int *class, |
| 498 | unsigned long deadline); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 499 | static void mv_eh_freeze(struct ata_port *ap); |
| 500 | static void mv_eh_thaw(struct ata_port *ap); |
Mark Lord | f273827 | 2008-01-26 18:32:29 -0500 | [diff] [blame] | 501 | static void mv6_dev_config(struct ata_device *dev); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 502 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 503 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 504 | unsigned int port); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 505 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 506 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
| 507 | void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 508 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 509 | unsigned int n_hc); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 510 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 511 | static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 512 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 513 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 514 | unsigned int port); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 515 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 516 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
| 517 | void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 518 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 519 | unsigned int n_hc); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 520 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 521 | static void mv_soc_enable_leds(struct mv_host_priv *hpriv, |
| 522 | void __iomem *mmio); |
| 523 | static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, |
| 524 | void __iomem *mmio); |
| 525 | static int mv_soc_reset_hc(struct mv_host_priv *hpriv, |
| 526 | void __iomem *mmio, unsigned int n_hc); |
| 527 | static void mv_soc_reset_flash(struct mv_host_priv *hpriv, |
| 528 | void __iomem *mmio); |
| 529 | static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 530 | static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 531 | static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 532 | unsigned int port_no); |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 533 | static int mv_stop_edma(struct ata_port *ap); |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 534 | static int mv_stop_edma_engine(void __iomem *port_mmio); |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 535 | static void mv_edma_cfg(struct ata_port *ap, int want_ncq); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 536 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 537 | static void mv_pmp_select(struct ata_port *ap, int pmp); |
| 538 | static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, |
| 539 | unsigned long deadline); |
| 540 | static int mv_softreset(struct ata_link *link, unsigned int *class, |
| 541 | unsigned long deadline); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 542 | |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 543 | /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below |
| 544 | * because we have to allow room for worst case splitting of |
| 545 | * PRDs for 64K boundaries in mv_fill_sg(). |
| 546 | */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 547 | static struct scsi_host_template mv5_sht = { |
Tejun Heo | 68d1d07 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 548 | ATA_BASE_SHT(DRV_NAME), |
Jeff Garzik | baf14aa | 2007-10-09 13:51:57 -0400 | [diff] [blame] | 549 | .sg_tablesize = MV_MAX_SG_CT / 2, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 550 | .dma_boundary = MV_DMA_BOUNDARY, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 551 | }; |
| 552 | |
| 553 | static struct scsi_host_template mv6_sht = { |
Tejun Heo | 68d1d07 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 554 | ATA_NCQ_SHT(DRV_NAME), |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 555 | .can_queue = MV_MAX_Q_DEPTH - 1, |
Jeff Garzik | baf14aa | 2007-10-09 13:51:57 -0400 | [diff] [blame] | 556 | .sg_tablesize = MV_MAX_SG_CT / 2, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 557 | .dma_boundary = MV_DMA_BOUNDARY, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 558 | }; |
| 559 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 560 | static struct ata_port_operations mv5_ops = { |
| 561 | .inherits = &ata_sff_port_ops, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 562 | |
| 563 | .qc_prep = mv_qc_prep, |
| 564 | .qc_issue = mv_qc_issue, |
| 565 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 566 | .freeze = mv_eh_freeze, |
| 567 | .thaw = mv_eh_thaw, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 568 | .hardreset = mv_hardreset, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 569 | .error_handler = ata_std_error_handler, /* avoid SFF EH */ |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 570 | .post_internal_cmd = ATA_OP_NULL, |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 571 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 572 | .scr_read = mv5_scr_read, |
| 573 | .scr_write = mv5_scr_write, |
| 574 | |
| 575 | .port_start = mv_port_start, |
| 576 | .port_stop = mv_port_stop, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 577 | }; |
| 578 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 579 | static struct ata_port_operations mv6_ops = { |
| 580 | .inherits = &mv5_ops, |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 581 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
Mark Lord | f273827 | 2008-01-26 18:32:29 -0500 | [diff] [blame] | 582 | .dev_config = mv6_dev_config, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 583 | .scr_read = mv_scr_read, |
| 584 | .scr_write = mv_scr_write, |
| 585 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 586 | .pmp_hardreset = mv_pmp_hardreset, |
| 587 | .pmp_softreset = mv_softreset, |
| 588 | .softreset = mv_softreset, |
| 589 | .error_handler = sata_pmp_error_handler, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 590 | }; |
| 591 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 592 | static struct ata_port_operations mv_iie_ops = { |
| 593 | .inherits = &mv6_ops, |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 594 | .qc_defer = ata_std_qc_defer, /* FIS-based switching */ |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 595 | .dev_config = ATA_OP_NULL, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 596 | .qc_prep = mv_qc_prep_iie, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 597 | }; |
| 598 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 599 | static const struct ata_port_info mv_port_info[] = { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 600 | { /* chip_504x */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 601 | .flags = MV_COMMON_FLAGS, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 602 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 603 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 604 | .port_ops = &mv5_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 605 | }, |
| 606 | { /* chip_508x */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 607 | .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 608 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 609 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 610 | .port_ops = &mv5_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 611 | }, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 612 | { /* chip_5080 */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 613 | .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 614 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 615 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 616 | .port_ops = &mv5_ops, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 617 | }, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 618 | { /* chip_604x */ |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 619 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 620 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 621 | ATA_FLAG_NCQ, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 622 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 623 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 624 | .port_ops = &mv6_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 625 | }, |
| 626 | { /* chip_608x */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 627 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 628 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 629 | ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 630 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 631 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 632 | .port_ops = &mv6_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 633 | }, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 634 | { /* chip_6042 */ |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 635 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 636 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 637 | ATA_FLAG_NCQ, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 638 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 639 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 640 | .port_ops = &mv_iie_ops, |
| 641 | }, |
| 642 | { /* chip_7042 */ |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 643 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 644 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 645 | ATA_FLAG_NCQ, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 646 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 647 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 648 | .port_ops = &mv_iie_ops, |
| 649 | }, |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 650 | { /* chip_soc */ |
Mark Lord | 02c1f32 | 2008-04-16 14:58:13 -0400 | [diff] [blame] | 651 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 652 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | |
Mark Lord | 02c1f32 | 2008-04-16 14:58:13 -0400 | [diff] [blame] | 653 | ATA_FLAG_NCQ | MV_FLAG_SOC, |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 654 | .pio_mask = 0x1f, /* pio0-4 */ |
| 655 | .udma_mask = ATA_UDMA6, |
| 656 | .port_ops = &mv_iie_ops, |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 657 | }, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 658 | }; |
| 659 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 660 | static const struct pci_device_id mv_pci_tbl[] = { |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 661 | { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, |
| 662 | { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, |
| 663 | { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, |
| 664 | { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, |
Alan Cox | cfbf723 | 2007-07-09 14:38:41 +0100 | [diff] [blame] | 665 | /* RocketRAID 1740/174x have different identifiers */ |
| 666 | { PCI_VDEVICE(TTI, 0x1740), chip_508x }, |
| 667 | { PCI_VDEVICE(TTI, 0x1742), chip_508x }, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 668 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 669 | { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, |
| 670 | { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, |
| 671 | { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, |
| 672 | { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, |
| 673 | { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, |
Jeff Garzik | 2917953 | 2005-11-11 08:08:03 -0500 | [diff] [blame] | 674 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 675 | { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, |
| 676 | |
Florian Attenberger | d9f9c6b | 2007-07-02 17:09:29 +0200 | [diff] [blame] | 677 | /* Adaptec 1430SA */ |
| 678 | { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, |
| 679 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 680 | /* Marvell 7042 support */ |
Morrison, Tom | 6a3d586 | 2007-03-06 02:38:10 -0800 | [diff] [blame] | 681 | { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, |
| 682 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 683 | /* Highpoint RocketRAID PCIe series */ |
| 684 | { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, |
| 685 | { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, |
| 686 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 687 | { } /* terminate list */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 688 | }; |
| 689 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 690 | static const struct mv_hw_ops mv5xxx_ops = { |
| 691 | .phy_errata = mv5_phy_errata, |
| 692 | .enable_leds = mv5_enable_leds, |
| 693 | .read_preamp = mv5_read_preamp, |
| 694 | .reset_hc = mv5_reset_hc, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 695 | .reset_flash = mv5_reset_flash, |
| 696 | .reset_bus = mv5_reset_bus, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 697 | }; |
| 698 | |
| 699 | static const struct mv_hw_ops mv6xxx_ops = { |
| 700 | .phy_errata = mv6_phy_errata, |
| 701 | .enable_leds = mv6_enable_leds, |
| 702 | .read_preamp = mv6_read_preamp, |
| 703 | .reset_hc = mv6_reset_hc, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 704 | .reset_flash = mv6_reset_flash, |
| 705 | .reset_bus = mv_reset_pci_bus, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 706 | }; |
| 707 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 708 | static const struct mv_hw_ops mv_soc_ops = { |
| 709 | .phy_errata = mv6_phy_errata, |
| 710 | .enable_leds = mv_soc_enable_leds, |
| 711 | .read_preamp = mv_soc_read_preamp, |
| 712 | .reset_hc = mv_soc_reset_hc, |
| 713 | .reset_flash = mv_soc_reset_flash, |
| 714 | .reset_bus = mv_soc_reset_bus, |
| 715 | }; |
| 716 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 717 | /* |
| 718 | * Functions |
| 719 | */ |
| 720 | |
| 721 | static inline void writelfl(unsigned long data, void __iomem *addr) |
| 722 | { |
| 723 | writel(data, addr); |
| 724 | (void) readl(addr); /* flush to avoid PCI posted write */ |
| 725 | } |
| 726 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 727 | static inline unsigned int mv_hc_from_port(unsigned int port) |
| 728 | { |
| 729 | return port >> MV_PORT_HC_SHIFT; |
| 730 | } |
| 731 | |
| 732 | static inline unsigned int mv_hardport_from_port(unsigned int port) |
| 733 | { |
| 734 | return port & MV_PORT_MASK; |
| 735 | } |
| 736 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 737 | static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) |
| 738 | { |
| 739 | return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); |
| 740 | } |
| 741 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 742 | static inline void __iomem *mv_hc_base_from_port(void __iomem *base, |
| 743 | unsigned int port) |
| 744 | { |
| 745 | return mv_hc_base(base, mv_hc_from_port(port)); |
| 746 | } |
| 747 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 748 | static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) |
| 749 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 750 | return mv_hc_base_from_port(base, port) + |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 751 | MV_SATAHC_ARBTR_REG_SZ + |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 752 | (mv_hardport_from_port(port) * MV_PORT_REG_SZ); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 753 | } |
| 754 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 755 | static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) |
| 756 | { |
| 757 | void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); |
| 758 | unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; |
| 759 | |
| 760 | return hc_mmio + ofs; |
| 761 | } |
| 762 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 763 | static inline void __iomem *mv_host_base(struct ata_host *host) |
| 764 | { |
| 765 | struct mv_host_priv *hpriv = host->private_data; |
| 766 | return hpriv->base; |
| 767 | } |
| 768 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 769 | static inline void __iomem *mv_ap_base(struct ata_port *ap) |
| 770 | { |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 771 | return mv_port_base(mv_host_base(ap->host), ap->port_no); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 772 | } |
| 773 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 774 | static inline int mv_get_hc_count(unsigned long port_flags) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 775 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 776 | return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 777 | } |
| 778 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 779 | static void mv_set_edma_ptrs(void __iomem *port_mmio, |
| 780 | struct mv_host_priv *hpriv, |
| 781 | struct mv_port_priv *pp) |
| 782 | { |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 783 | u32 index; |
| 784 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 785 | /* |
| 786 | * initialize request queue |
| 787 | */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 788 | index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT; |
| 789 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 790 | WARN_ON(pp->crqb_dma & 0x3ff); |
| 791 | writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 792 | writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 793 | port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
| 794 | |
| 795 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 796 | writelfl((pp->crqb_dma & 0xffffffff) | index, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 797 | port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); |
| 798 | else |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 799 | writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 800 | |
| 801 | /* |
| 802 | * initialize response queue |
| 803 | */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 804 | index = (pp->resp_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_RSP_Q_PTR_SHIFT; |
| 805 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 806 | WARN_ON(pp->crpb_dma & 0xff); |
| 807 | writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); |
| 808 | |
| 809 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 810 | writelfl((pp->crpb_dma & 0xffffffff) | index, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 811 | port_mmio + EDMA_RSP_Q_IN_PTR_OFS); |
| 812 | else |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 813 | writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 814 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 815 | writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 816 | port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 817 | } |
| 818 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 819 | /** |
| 820 | * mv_start_dma - Enable eDMA engine |
| 821 | * @base: port base address |
| 822 | * @pp: port private data |
| 823 | * |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 824 | * Verify the local cache of the eDMA state is accurate with a |
| 825 | * WARN_ON. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 826 | * |
| 827 | * LOCKING: |
| 828 | * Inherited from caller. |
| 829 | */ |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 830 | static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, |
Mark Lord | 7210916 | 2008-01-26 18:31:33 -0500 | [diff] [blame] | 831 | struct mv_port_priv *pp, u8 protocol) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 832 | { |
Mark Lord | 7210916 | 2008-01-26 18:31:33 -0500 | [diff] [blame] | 833 | int want_ncq = (protocol == ATA_PROT_NCQ); |
| 834 | |
| 835 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { |
| 836 | int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); |
| 837 | if (want_ncq != using_ncq) |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 838 | mv_stop_edma(ap); |
Mark Lord | 7210916 | 2008-01-26 18:31:33 -0500 | [diff] [blame] | 839 | } |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 840 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 841 | struct mv_host_priv *hpriv = ap->host->private_data; |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 842 | int hardport = mv_hardport_from_port(ap->port_no); |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 843 | void __iomem *hc_mmio = mv_hc_base_from_port( |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 844 | mv_host_base(ap->host), hardport); |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 845 | u32 hc_irq_cause, ipending; |
| 846 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 847 | /* clear EDMA event indicators, if any */ |
Mark Lord | f630d56 | 2008-01-26 18:31:00 -0500 | [diff] [blame] | 848 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 849 | |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 850 | /* clear EDMA interrupt indicator, if any */ |
| 851 | hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 852 | ipending = (DEV_IRQ | DMA_IRQ) << hardport; |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 853 | if (hc_irq_cause & ipending) { |
| 854 | writelfl(hc_irq_cause & ~ipending, |
| 855 | hc_mmio + HC_IRQ_CAUSE_OFS); |
| 856 | } |
| 857 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 858 | mv_edma_cfg(ap, want_ncq); |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 859 | |
| 860 | /* clear FIS IRQ Cause */ |
| 861 | writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); |
| 862 | |
Mark Lord | f630d56 | 2008-01-26 18:31:00 -0500 | [diff] [blame] | 863 | mv_set_edma_ptrs(port_mmio, hpriv, pp); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 864 | |
Mark Lord | f630d56 | 2008-01-26 18:31:00 -0500 | [diff] [blame] | 865 | writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 866 | pp->pp_flags |= MV_PP_FLAG_EDMA_EN; |
| 867 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 868 | } |
| 869 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 870 | /** |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 871 | * mv_stop_edma_engine - Disable eDMA engine |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 872 | * @port_mmio: io base address |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 873 | * |
| 874 | * LOCKING: |
| 875 | * Inherited from caller. |
| 876 | */ |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 877 | static int mv_stop_edma_engine(void __iomem *port_mmio) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 878 | { |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 879 | int i; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 880 | |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 881 | /* Disable eDMA. The disable bit auto clears. */ |
| 882 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 883 | |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 884 | /* Wait for the chip to confirm eDMA is off. */ |
| 885 | for (i = 10000; i > 0; i--) { |
| 886 | u32 reg = readl(port_mmio + EDMA_CMD_OFS); |
Jeff Garzik | 4537deb | 2007-07-12 14:30:19 -0400 | [diff] [blame] | 887 | if (!(reg & EDMA_EN)) |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 888 | return 0; |
| 889 | udelay(10); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 890 | } |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 891 | return -EIO; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 892 | } |
| 893 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 894 | static int mv_stop_edma(struct ata_port *ap) |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 895 | { |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 896 | void __iomem *port_mmio = mv_ap_base(ap); |
| 897 | struct mv_port_priv *pp = ap->private_data; |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 898 | |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 899 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) |
| 900 | return 0; |
| 901 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
| 902 | if (mv_stop_edma_engine(port_mmio)) { |
| 903 | ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); |
| 904 | return -EIO; |
| 905 | } |
| 906 | return 0; |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 907 | } |
| 908 | |
Jeff Garzik | 8a70f8d | 2005-10-05 17:19:47 -0400 | [diff] [blame] | 909 | #ifdef ATA_DEBUG |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 910 | static void mv_dump_mem(void __iomem *start, unsigned bytes) |
| 911 | { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 912 | int b, w; |
| 913 | for (b = 0; b < bytes; ) { |
| 914 | DPRINTK("%p: ", start + b); |
| 915 | for (w = 0; b < bytes && w < 4; w++) { |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 916 | printk("%08x ", readl(start + b)); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 917 | b += sizeof(u32); |
| 918 | } |
| 919 | printk("\n"); |
| 920 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 921 | } |
Jeff Garzik | 8a70f8d | 2005-10-05 17:19:47 -0400 | [diff] [blame] | 922 | #endif |
| 923 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 924 | static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) |
| 925 | { |
| 926 | #ifdef ATA_DEBUG |
| 927 | int b, w; |
| 928 | u32 dw; |
| 929 | for (b = 0; b < bytes; ) { |
| 930 | DPRINTK("%02x: ", b); |
| 931 | for (w = 0; b < bytes && w < 4; w++) { |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 932 | (void) pci_read_config_dword(pdev, b, &dw); |
| 933 | printk("%08x ", dw); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 934 | b += sizeof(u32); |
| 935 | } |
| 936 | printk("\n"); |
| 937 | } |
| 938 | #endif |
| 939 | } |
| 940 | static void mv_dump_all_regs(void __iomem *mmio_base, int port, |
| 941 | struct pci_dev *pdev) |
| 942 | { |
| 943 | #ifdef ATA_DEBUG |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 944 | void __iomem *hc_base = mv_hc_base(mmio_base, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 945 | port >> MV_PORT_HC_SHIFT); |
| 946 | void __iomem *port_base; |
| 947 | int start_port, num_ports, p, start_hc, num_hcs, hc; |
| 948 | |
| 949 | if (0 > port) { |
| 950 | start_hc = start_port = 0; |
| 951 | num_ports = 8; /* shld be benign for 4 port devs */ |
| 952 | num_hcs = 2; |
| 953 | } else { |
| 954 | start_hc = port >> MV_PORT_HC_SHIFT; |
| 955 | start_port = port; |
| 956 | num_ports = num_hcs = 1; |
| 957 | } |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 958 | DPRINTK("All registers for port(s) %u-%u:\n", start_port, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 959 | num_ports > 1 ? num_ports - 1 : start_port); |
| 960 | |
| 961 | if (NULL != pdev) { |
| 962 | DPRINTK("PCI config space regs:\n"); |
| 963 | mv_dump_pci_cfg(pdev, 0x68); |
| 964 | } |
| 965 | DPRINTK("PCI regs:\n"); |
| 966 | mv_dump_mem(mmio_base+0xc00, 0x3c); |
| 967 | mv_dump_mem(mmio_base+0xd00, 0x34); |
| 968 | mv_dump_mem(mmio_base+0xf00, 0x4); |
| 969 | mv_dump_mem(mmio_base+0x1d00, 0x6c); |
| 970 | for (hc = start_hc; hc < start_hc + num_hcs; hc++) { |
Dan Aloni | d220c37 | 2006-04-10 23:20:22 -0700 | [diff] [blame] | 971 | hc_base = mv_hc_base(mmio_base, hc); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 972 | DPRINTK("HC regs (HC %i):\n", hc); |
| 973 | mv_dump_mem(hc_base, 0x1c); |
| 974 | } |
| 975 | for (p = start_port; p < start_port + num_ports; p++) { |
| 976 | port_base = mv_port_base(mmio_base, p); |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 977 | DPRINTK("EDMA regs (port %i):\n", p); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 978 | mv_dump_mem(port_base, 0x54); |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 979 | DPRINTK("SATA regs (port %i):\n", p); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 980 | mv_dump_mem(port_base+0x300, 0x60); |
| 981 | } |
| 982 | #endif |
| 983 | } |
| 984 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 985 | static unsigned int mv_scr_offset(unsigned int sc_reg_in) |
| 986 | { |
| 987 | unsigned int ofs; |
| 988 | |
| 989 | switch (sc_reg_in) { |
| 990 | case SCR_STATUS: |
| 991 | case SCR_CONTROL: |
| 992 | case SCR_ERROR: |
| 993 | ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); |
| 994 | break; |
| 995 | case SCR_ACTIVE: |
| 996 | ofs = SATA_ACTIVE_OFS; /* active is not with the others */ |
| 997 | break; |
| 998 | default: |
| 999 | ofs = 0xffffffffU; |
| 1000 | break; |
| 1001 | } |
| 1002 | return ofs; |
| 1003 | } |
| 1004 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1005 | static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1006 | { |
| 1007 | unsigned int ofs = mv_scr_offset(sc_reg_in); |
| 1008 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1009 | if (ofs != 0xffffffffU) { |
| 1010 | *val = readl(mv_ap_base(ap) + ofs); |
| 1011 | return 0; |
| 1012 | } else |
| 1013 | return -EINVAL; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1014 | } |
| 1015 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1016 | static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1017 | { |
| 1018 | unsigned int ofs = mv_scr_offset(sc_reg_in); |
| 1019 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1020 | if (ofs != 0xffffffffU) { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1021 | writelfl(val, mv_ap_base(ap) + ofs); |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1022 | return 0; |
| 1023 | } else |
| 1024 | return -EINVAL; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1025 | } |
| 1026 | |
Mark Lord | f273827 | 2008-01-26 18:32:29 -0500 | [diff] [blame] | 1027 | static void mv6_dev_config(struct ata_device *adev) |
| 1028 | { |
| 1029 | /* |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1030 | * Deal with Gen-II ("mv6") hardware quirks/restrictions: |
| 1031 | * |
| 1032 | * Gen-II does not support NCQ over a port multiplier |
| 1033 | * (no FIS-based switching). |
| 1034 | * |
Mark Lord | f273827 | 2008-01-26 18:32:29 -0500 | [diff] [blame] | 1035 | * We don't have hob_nsect when doing NCQ commands on Gen-II. |
| 1036 | * See mv_qc_prep() for more info. |
| 1037 | */ |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1038 | if (adev->flags & ATA_DFLAG_NCQ) { |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1039 | if (sata_pmp_attached(adev->link->ap)) { |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1040 | adev->flags &= ~ATA_DFLAG_NCQ; |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1041 | ata_dev_printk(adev, KERN_INFO, |
| 1042 | "NCQ disabled for command-based switching\n"); |
| 1043 | } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) { |
| 1044 | adev->max_sectors = GEN_II_NCQ_MAX_SECTORS; |
| 1045 | ata_dev_printk(adev, KERN_INFO, |
| 1046 | "max_sectors limited to %u for NCQ\n", |
| 1047 | adev->max_sectors); |
| 1048 | } |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1049 | } |
Mark Lord | f273827 | 2008-01-26 18:32:29 -0500 | [diff] [blame] | 1050 | } |
| 1051 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1052 | static void mv_config_fbs(void __iomem *port_mmio, int enable_fbs) |
| 1053 | { |
| 1054 | u32 old_fcfg, new_fcfg, old_ltmode, new_ltmode; |
| 1055 | /* |
| 1056 | * Various bit settings required for operation |
| 1057 | * in FIS-based switching (fbs) mode on GenIIe: |
| 1058 | */ |
| 1059 | old_fcfg = readl(port_mmio + FIS_CFG_OFS); |
| 1060 | old_ltmode = readl(port_mmio + LTMODE_OFS); |
| 1061 | if (enable_fbs) { |
| 1062 | new_fcfg = old_fcfg | FIS_CFG_SINGLE_SYNC; |
| 1063 | new_ltmode = old_ltmode | LTMODE_BIT8; |
| 1064 | } else { /* disable fbs */ |
| 1065 | new_fcfg = old_fcfg & ~FIS_CFG_SINGLE_SYNC; |
| 1066 | new_ltmode = old_ltmode & ~LTMODE_BIT8; |
| 1067 | } |
| 1068 | if (new_fcfg != old_fcfg) |
| 1069 | writelfl(new_fcfg, port_mmio + FIS_CFG_OFS); |
| 1070 | if (new_ltmode != old_ltmode) |
| 1071 | writelfl(new_ltmode, port_mmio + LTMODE_OFS); |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 1072 | } |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1073 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1074 | static void mv_edma_cfg(struct ata_port *ap, int want_ncq) |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1075 | { |
| 1076 | u32 cfg; |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1077 | struct mv_port_priv *pp = ap->private_data; |
| 1078 | struct mv_host_priv *hpriv = ap->host->private_data; |
| 1079 | void __iomem *port_mmio = mv_ap_base(ap); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1080 | |
| 1081 | /* set up non-NCQ EDMA configuration */ |
| 1082 | cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ |
| 1083 | |
| 1084 | if (IS_GEN_I(hpriv)) |
| 1085 | cfg |= (1 << 8); /* enab config burst size mask */ |
| 1086 | |
| 1087 | else if (IS_GEN_II(hpriv)) |
| 1088 | cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; |
| 1089 | |
| 1090 | else if (IS_GEN_IIE(hpriv)) { |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 1091 | cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ |
| 1092 | cfg |= (1 << 22); /* enab 4-entry host queue cache */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1093 | cfg |= (1 << 18); /* enab early completion */ |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 1094 | cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */ |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1095 | |
| 1096 | if (want_ncq && sata_pmp_attached(ap)) { |
| 1097 | cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ |
| 1098 | mv_config_fbs(port_mmio, 1); |
| 1099 | } else { |
| 1100 | mv_config_fbs(port_mmio, 0); |
| 1101 | } |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1102 | } |
| 1103 | |
Mark Lord | 7210916 | 2008-01-26 18:31:33 -0500 | [diff] [blame] | 1104 | if (want_ncq) { |
| 1105 | cfg |= EDMA_CFG_NCQ; |
| 1106 | pp->pp_flags |= MV_PP_FLAG_NCQ_EN; |
| 1107 | } else |
| 1108 | pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; |
| 1109 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1110 | writelfl(cfg, port_mmio + EDMA_CFG_OFS); |
| 1111 | } |
| 1112 | |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1113 | static void mv_port_free_dma_mem(struct ata_port *ap) |
| 1114 | { |
| 1115 | struct mv_host_priv *hpriv = ap->host->private_data; |
| 1116 | struct mv_port_priv *pp = ap->private_data; |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1117 | int tag; |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1118 | |
| 1119 | if (pp->crqb) { |
| 1120 | dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); |
| 1121 | pp->crqb = NULL; |
| 1122 | } |
| 1123 | if (pp->crpb) { |
| 1124 | dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); |
| 1125 | pp->crpb = NULL; |
| 1126 | } |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1127 | /* |
| 1128 | * For GEN_I, there's no NCQ, so we have only a single sg_tbl. |
| 1129 | * For later hardware, we have one unique sg_tbl per NCQ tag. |
| 1130 | */ |
| 1131 | for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { |
| 1132 | if (pp->sg_tbl[tag]) { |
| 1133 | if (tag == 0 || !IS_GEN_I(hpriv)) |
| 1134 | dma_pool_free(hpriv->sg_tbl_pool, |
| 1135 | pp->sg_tbl[tag], |
| 1136 | pp->sg_tbl_dma[tag]); |
| 1137 | pp->sg_tbl[tag] = NULL; |
| 1138 | } |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1139 | } |
| 1140 | } |
| 1141 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1142 | /** |
| 1143 | * mv_port_start - Port specific init/start routine. |
| 1144 | * @ap: ATA channel to manipulate |
| 1145 | * |
| 1146 | * Allocate and point to DMA memory, init port private memory, |
| 1147 | * zero indices. |
| 1148 | * |
| 1149 | * LOCKING: |
| 1150 | * Inherited from caller. |
| 1151 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1152 | static int mv_port_start(struct ata_port *ap) |
| 1153 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1154 | struct device *dev = ap->host->dev; |
| 1155 | struct mv_host_priv *hpriv = ap->host->private_data; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1156 | struct mv_port_priv *pp; |
James Bottomley | dde2020 | 2008-02-19 11:36:56 +0100 | [diff] [blame] | 1157 | int tag; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1158 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1159 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 1160 | if (!pp) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1161 | return -ENOMEM; |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1162 | ap->private_data = pp; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1163 | |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1164 | pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); |
| 1165 | if (!pp->crqb) |
| 1166 | return -ENOMEM; |
| 1167 | memset(pp->crqb, 0, MV_CRQB_Q_SZ); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1168 | |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1169 | pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); |
| 1170 | if (!pp->crpb) |
| 1171 | goto out_port_free_dma_mem; |
| 1172 | memset(pp->crpb, 0, MV_CRPB_Q_SZ); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1173 | |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1174 | /* |
| 1175 | * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. |
| 1176 | * For later hardware, we need one unique sg_tbl per NCQ tag. |
| 1177 | */ |
| 1178 | for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { |
| 1179 | if (tag == 0 || !IS_GEN_I(hpriv)) { |
| 1180 | pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, |
| 1181 | GFP_KERNEL, &pp->sg_tbl_dma[tag]); |
| 1182 | if (!pp->sg_tbl[tag]) |
| 1183 | goto out_port_free_dma_mem; |
| 1184 | } else { |
| 1185 | pp->sg_tbl[tag] = pp->sg_tbl[0]; |
| 1186 | pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; |
| 1187 | } |
| 1188 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1189 | return 0; |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1190 | |
| 1191 | out_port_free_dma_mem: |
| 1192 | mv_port_free_dma_mem(ap); |
| 1193 | return -ENOMEM; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1194 | } |
| 1195 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1196 | /** |
| 1197 | * mv_port_stop - Port specific cleanup/stop routine. |
| 1198 | * @ap: ATA channel to manipulate |
| 1199 | * |
| 1200 | * Stop DMA, cleanup port memory. |
| 1201 | * |
| 1202 | * LOCKING: |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1203 | * This routine uses the host lock to protect the DMA stop. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1204 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1205 | static void mv_port_stop(struct ata_port *ap) |
| 1206 | { |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1207 | mv_stop_edma(ap); |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1208 | mv_port_free_dma_mem(ap); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1209 | } |
| 1210 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1211 | /** |
| 1212 | * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries |
| 1213 | * @qc: queued command whose SG list to source from |
| 1214 | * |
| 1215 | * Populate the SG list and mark the last entry. |
| 1216 | * |
| 1217 | * LOCKING: |
| 1218 | * Inherited from caller. |
| 1219 | */ |
Jeff Garzik | 6c08772 | 2007-10-12 00:16:23 -0400 | [diff] [blame] | 1220 | static void mv_fill_sg(struct ata_queued_cmd *qc) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1221 | { |
| 1222 | struct mv_port_priv *pp = qc->ap->private_data; |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 1223 | struct scatterlist *sg; |
Jeff Garzik | 3be6cbd | 2007-10-18 16:21:18 -0400 | [diff] [blame] | 1224 | struct mv_sg *mv_sg, *last_sg = NULL; |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 1225 | unsigned int si; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1226 | |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1227 | mv_sg = pp->sg_tbl[qc->tag]; |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 1228 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1229 | dma_addr_t addr = sg_dma_address(sg); |
| 1230 | u32 sg_len = sg_dma_len(sg); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1231 | |
Olof Johansson | 4007b49 | 2007-10-02 20:45:27 -0500 | [diff] [blame] | 1232 | while (sg_len) { |
| 1233 | u32 offset = addr & 0xffff; |
| 1234 | u32 len = sg_len; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1235 | |
Olof Johansson | 4007b49 | 2007-10-02 20:45:27 -0500 | [diff] [blame] | 1236 | if ((offset + sg_len > 0x10000)) |
| 1237 | len = 0x10000 - offset; |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 1238 | |
Olof Johansson | 4007b49 | 2007-10-02 20:45:27 -0500 | [diff] [blame] | 1239 | mv_sg->addr = cpu_to_le32(addr & 0xffffffff); |
| 1240 | mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); |
Jeff Garzik | 6c08772 | 2007-10-12 00:16:23 -0400 | [diff] [blame] | 1241 | mv_sg->flags_size = cpu_to_le32(len & 0xffff); |
Olof Johansson | 4007b49 | 2007-10-02 20:45:27 -0500 | [diff] [blame] | 1242 | |
| 1243 | sg_len -= len; |
| 1244 | addr += len; |
| 1245 | |
Jeff Garzik | 3be6cbd | 2007-10-18 16:21:18 -0400 | [diff] [blame] | 1246 | last_sg = mv_sg; |
Olof Johansson | 4007b49 | 2007-10-02 20:45:27 -0500 | [diff] [blame] | 1247 | mv_sg++; |
Olof Johansson | 4007b49 | 2007-10-02 20:45:27 -0500 | [diff] [blame] | 1248 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1249 | } |
Jeff Garzik | 3be6cbd | 2007-10-18 16:21:18 -0400 | [diff] [blame] | 1250 | |
| 1251 | if (likely(last_sg)) |
| 1252 | last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1253 | } |
| 1254 | |
Jeff Garzik | 5796d1c | 2007-10-26 00:03:37 -0400 | [diff] [blame] | 1255 | static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1256 | { |
Mark Lord | 559eeda | 2006-05-19 16:40:15 -0400 | [diff] [blame] | 1257 | u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1258 | (last ? CRQB_CMD_LAST : 0); |
Mark Lord | 559eeda | 2006-05-19 16:40:15 -0400 | [diff] [blame] | 1259 | *cmdw = cpu_to_le16(tmp); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1260 | } |
| 1261 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1262 | /** |
| 1263 | * mv_qc_prep - Host specific command preparation. |
| 1264 | * @qc: queued command to prepare |
| 1265 | * |
| 1266 | * This routine simply redirects to the general purpose routine |
| 1267 | * if command is not DMA. Else, it handles prep of the CRQB |
| 1268 | * (command request block), does some sanity checking, and calls |
| 1269 | * the SG load routine. |
| 1270 | * |
| 1271 | * LOCKING: |
| 1272 | * Inherited from caller. |
| 1273 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1274 | static void mv_qc_prep(struct ata_queued_cmd *qc) |
| 1275 | { |
| 1276 | struct ata_port *ap = qc->ap; |
| 1277 | struct mv_port_priv *pp = ap->private_data; |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 1278 | __le16 *cw; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1279 | struct ata_taskfile *tf; |
| 1280 | u16 flags = 0; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1281 | unsigned in_index; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1282 | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 1283 | if ((qc->tf.protocol != ATA_PROT_DMA) && |
| 1284 | (qc->tf.protocol != ATA_PROT_NCQ)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1285 | return; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1286 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1287 | /* Fill in command request block |
| 1288 | */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1289 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1290 | flags |= CRQB_FLAG_READ; |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 1291 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1292 | flags |= qc->tag << CRQB_TAG_SHIFT; |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1293 | flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1294 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1295 | /* get current queue index from software */ |
| 1296 | in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1297 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1298 | pp->crqb[in_index].sg_addr = |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1299 | cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1300 | pp->crqb[in_index].sg_addr_hi = |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1301 | cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1302 | pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); |
| 1303 | |
| 1304 | cw = &pp->crqb[in_index].ata_cmd[0]; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1305 | tf = &qc->tf; |
| 1306 | |
| 1307 | /* Sadly, the CRQB cannot accomodate all registers--there are |
| 1308 | * only 11 bytes...so we must pick and choose required |
| 1309 | * registers based on the command. So, we drop feature and |
| 1310 | * hob_feature for [RW] DMA commands, but they are needed for |
| 1311 | * NCQ. NCQ will drop hob_nsect. |
| 1312 | */ |
| 1313 | switch (tf->command) { |
| 1314 | case ATA_CMD_READ: |
| 1315 | case ATA_CMD_READ_EXT: |
| 1316 | case ATA_CMD_WRITE: |
| 1317 | case ATA_CMD_WRITE_EXT: |
Jens Axboe | c15d85c | 2006-02-15 15:59:25 +0100 | [diff] [blame] | 1318 | case ATA_CMD_WRITE_FUA_EXT: |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1319 | mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); |
| 1320 | break; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1321 | case ATA_CMD_FPDMA_READ: |
| 1322 | case ATA_CMD_FPDMA_WRITE: |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1323 | mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1324 | mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); |
| 1325 | break; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1326 | default: |
| 1327 | /* The only other commands EDMA supports in non-queued and |
| 1328 | * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none |
| 1329 | * of which are defined/used by Linux. If we get here, this |
| 1330 | * driver needs work. |
| 1331 | * |
| 1332 | * FIXME: modify libata to give qc_prep a return value and |
| 1333 | * return error here. |
| 1334 | */ |
| 1335 | BUG_ON(tf->command); |
| 1336 | break; |
| 1337 | } |
| 1338 | mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); |
| 1339 | mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); |
| 1340 | mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); |
| 1341 | mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); |
| 1342 | mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); |
| 1343 | mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); |
| 1344 | mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); |
| 1345 | mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); |
| 1346 | mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ |
| 1347 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1348 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1349 | return; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1350 | mv_fill_sg(qc); |
| 1351 | } |
| 1352 | |
| 1353 | /** |
| 1354 | * mv_qc_prep_iie - Host specific command preparation. |
| 1355 | * @qc: queued command to prepare |
| 1356 | * |
| 1357 | * This routine simply redirects to the general purpose routine |
| 1358 | * if command is not DMA. Else, it handles prep of the CRQB |
| 1359 | * (command request block), does some sanity checking, and calls |
| 1360 | * the SG load routine. |
| 1361 | * |
| 1362 | * LOCKING: |
| 1363 | * Inherited from caller. |
| 1364 | */ |
| 1365 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc) |
| 1366 | { |
| 1367 | struct ata_port *ap = qc->ap; |
| 1368 | struct mv_port_priv *pp = ap->private_data; |
| 1369 | struct mv_crqb_iie *crqb; |
| 1370 | struct ata_taskfile *tf; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1371 | unsigned in_index; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1372 | u32 flags = 0; |
| 1373 | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 1374 | if ((qc->tf.protocol != ATA_PROT_DMA) && |
| 1375 | (qc->tf.protocol != ATA_PROT_NCQ)) |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1376 | return; |
| 1377 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1378 | /* Fill in Gen IIE command request block */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1379 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
| 1380 | flags |= CRQB_FLAG_READ; |
| 1381 | |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 1382 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1383 | flags |= qc->tag << CRQB_TAG_SHIFT; |
Mark Lord | 8c0aeb4 | 2008-01-26 18:31:48 -0500 | [diff] [blame] | 1384 | flags |= qc->tag << CRQB_HOSTQ_SHIFT; |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1385 | flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1386 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1387 | /* get current queue index from software */ |
| 1388 | in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1389 | |
| 1390 | crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1391 | crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); |
| 1392 | crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1393 | crqb->flags = cpu_to_le32(flags); |
| 1394 | |
| 1395 | tf = &qc->tf; |
| 1396 | crqb->ata_cmd[0] = cpu_to_le32( |
| 1397 | (tf->command << 16) | |
| 1398 | (tf->feature << 24) |
| 1399 | ); |
| 1400 | crqb->ata_cmd[1] = cpu_to_le32( |
| 1401 | (tf->lbal << 0) | |
| 1402 | (tf->lbam << 8) | |
| 1403 | (tf->lbah << 16) | |
| 1404 | (tf->device << 24) |
| 1405 | ); |
| 1406 | crqb->ata_cmd[2] = cpu_to_le32( |
| 1407 | (tf->hob_lbal << 0) | |
| 1408 | (tf->hob_lbam << 8) | |
| 1409 | (tf->hob_lbah << 16) | |
| 1410 | (tf->hob_feature << 24) |
| 1411 | ); |
| 1412 | crqb->ata_cmd[3] = cpu_to_le32( |
| 1413 | (tf->nsect << 0) | |
| 1414 | (tf->hob_nsect << 8) |
| 1415 | ); |
| 1416 | |
| 1417 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
| 1418 | return; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1419 | mv_fill_sg(qc); |
| 1420 | } |
| 1421 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1422 | /** |
| 1423 | * mv_qc_issue - Initiate a command to the host |
| 1424 | * @qc: queued command to start |
| 1425 | * |
| 1426 | * This routine simply redirects to the general purpose routine |
| 1427 | * if command is not DMA. Else, it sanity checks our local |
| 1428 | * caches of the request producer/consumer indices then enables |
| 1429 | * DMA and bumps the request producer index. |
| 1430 | * |
| 1431 | * LOCKING: |
| 1432 | * Inherited from caller. |
| 1433 | */ |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 1434 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1435 | { |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1436 | struct ata_port *ap = qc->ap; |
| 1437 | void __iomem *port_mmio = mv_ap_base(ap); |
| 1438 | struct mv_port_priv *pp = ap->private_data; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1439 | u32 in_index; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1440 | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 1441 | if ((qc->tf.protocol != ATA_PROT_DMA) && |
| 1442 | (qc->tf.protocol != ATA_PROT_NCQ)) { |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 1443 | /* |
| 1444 | * We're about to send a non-EDMA capable command to the |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1445 | * port. Turn off EDMA so there won't be problems accessing |
| 1446 | * shadow block, etc registers. |
| 1447 | */ |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 1448 | mv_stop_edma(ap); |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1449 | mv_pmp_select(ap, qc->dev->link->pmp); |
Tejun Heo | 9363c38 | 2008-04-07 22:47:16 +0900 | [diff] [blame] | 1450 | return ata_sff_qc_issue(qc); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1451 | } |
| 1452 | |
Mark Lord | 7210916 | 2008-01-26 18:31:33 -0500 | [diff] [blame] | 1453 | mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1454 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1455 | pp->req_idx++; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1456 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1457 | in_index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1458 | |
| 1459 | /* and write the request in pointer to kick the EDMA to life */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1460 | writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, |
| 1461 | port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1462 | |
| 1463 | return 0; |
| 1464 | } |
| 1465 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1466 | /** |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1467 | * mv_err_intr - Handle error interrupts on the port |
| 1468 | * @ap: ATA channel to manipulate |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 1469 | * @reset_allowed: bool: 0 == don't trigger from reset here |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1470 | * |
| 1471 | * In most cases, just clear the interrupt and move on. However, |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1472 | * some cases require an eDMA reset, which also performs a COMRESET. |
| 1473 | * The SERR case requires a clear of pending errors in the SATA |
| 1474 | * SERROR register. Finally, if the port disabled DMA, |
| 1475 | * update our cached copy to match. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1476 | * |
| 1477 | * LOCKING: |
| 1478 | * Inherited from caller. |
| 1479 | */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1480 | static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1481 | { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1482 | void __iomem *port_mmio = mv_ap_base(ap); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1483 | u32 edma_err_cause, eh_freeze_mask, serr = 0; |
| 1484 | struct mv_port_priv *pp = ap->private_data; |
| 1485 | struct mv_host_priv *hpriv = ap->host->private_data; |
| 1486 | unsigned int edma_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); |
| 1487 | unsigned int action = 0, err_mask = 0; |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1488 | struct ata_eh_info *ehi = &ap->link.eh_info; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1489 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1490 | ata_ehi_clear_desc(ehi); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1491 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1492 | if (!edma_enabled) { |
| 1493 | /* just a guess: do we need to do this? should we |
| 1494 | * expand this, and do it in all cases? |
| 1495 | */ |
Tejun Heo | 936fd73 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1496 | sata_scr_read(&ap->link, SCR_ERROR, &serr); |
| 1497 | sata_scr_write_flush(&ap->link, SCR_ERROR, serr); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1498 | } |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1499 | |
| 1500 | edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 1501 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1502 | ata_ehi_push_desc(ehi, "edma_err_cause=%08x", edma_err_cause); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1503 | |
| 1504 | /* |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1505 | * All generations share these EDMA error cause bits: |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1506 | */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1507 | if (edma_err_cause & EDMA_ERR_DEV) |
| 1508 | err_mask |= AC_ERR_DEV; |
| 1509 | if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 1510 | EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1511 | EDMA_ERR_INTRL_PAR)) { |
| 1512 | err_mask |= AC_ERR_ATA_BUS; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1513 | action |= ATA_EH_RESET; |
Tejun Heo | b64bbc3 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1514 | ata_ehi_push_desc(ehi, "parity error"); |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 1515 | } |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1516 | if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { |
| 1517 | ata_ehi_hotplugged(ehi); |
| 1518 | ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? |
Tejun Heo | b64bbc3 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1519 | "dev disconnect" : "dev connect"); |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1520 | action |= ATA_EH_RESET; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1521 | } |
| 1522 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1523 | /* |
| 1524 | * Gen-I has a different SELF_DIS bit, |
| 1525 | * different FREEZE bits, and no SERR bit: |
| 1526 | */ |
Jeff Garzik | ee9ccdf | 2007-07-12 15:51:22 -0400 | [diff] [blame] | 1527 | if (IS_GEN_I(hpriv)) { |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1528 | eh_freeze_mask = EDMA_EH_FREEZE_5; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1529 | if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1530 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
Tejun Heo | b64bbc3 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1531 | ata_ehi_push_desc(ehi, "EDMA self-disable"); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1532 | } |
| 1533 | } else { |
| 1534 | eh_freeze_mask = EDMA_EH_FREEZE; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1535 | if (edma_err_cause & EDMA_ERR_SELF_DIS) { |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1536 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
Tejun Heo | b64bbc3 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1537 | ata_ehi_push_desc(ehi, "EDMA self-disable"); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1538 | } |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1539 | if (edma_err_cause & EDMA_ERR_SERR) { |
Tejun Heo | 936fd73 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1540 | sata_scr_read(&ap->link, SCR_ERROR, &serr); |
| 1541 | sata_scr_write_flush(&ap->link, SCR_ERROR, serr); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1542 | err_mask = AC_ERR_ATA_BUS; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1543 | action |= ATA_EH_RESET; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1544 | } |
| 1545 | } |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1546 | |
| 1547 | /* Clear EDMA now that SERR cleanup done */ |
Mark Lord | 3606a38 | 2008-01-26 18:28:23 -0500 | [diff] [blame] | 1548 | writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1549 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1550 | if (!err_mask) { |
| 1551 | err_mask = AC_ERR_OTHER; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1552 | action |= ATA_EH_RESET; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1553 | } |
| 1554 | |
| 1555 | ehi->serror |= serr; |
| 1556 | ehi->action |= action; |
| 1557 | |
| 1558 | if (qc) |
| 1559 | qc->err_mask |= err_mask; |
| 1560 | else |
| 1561 | ehi->err_mask |= err_mask; |
| 1562 | |
| 1563 | if (edma_err_cause & eh_freeze_mask) |
| 1564 | ata_port_freeze(ap); |
| 1565 | else |
| 1566 | ata_port_abort(ap); |
| 1567 | } |
| 1568 | |
| 1569 | static void mv_intr_pio(struct ata_port *ap) |
| 1570 | { |
| 1571 | struct ata_queued_cmd *qc; |
| 1572 | u8 ata_status; |
| 1573 | |
| 1574 | /* ignore spurious intr if drive still BUSY */ |
| 1575 | ata_status = readb(ap->ioaddr.status_addr); |
| 1576 | if (unlikely(ata_status & ATA_BUSY)) |
| 1577 | return; |
| 1578 | |
| 1579 | /* get active ATA command */ |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1580 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1581 | if (unlikely(!qc)) /* no active tag */ |
| 1582 | return; |
| 1583 | if (qc->tf.flags & ATA_TFLAG_POLLING) /* polling; we don't own qc */ |
| 1584 | return; |
| 1585 | |
| 1586 | /* and finally, complete the ATA command */ |
| 1587 | qc->err_mask |= ac_err_mask(ata_status); |
| 1588 | ata_qc_complete(qc); |
| 1589 | } |
| 1590 | |
| 1591 | static void mv_intr_edma(struct ata_port *ap) |
| 1592 | { |
| 1593 | void __iomem *port_mmio = mv_ap_base(ap); |
| 1594 | struct mv_host_priv *hpriv = ap->host->private_data; |
| 1595 | struct mv_port_priv *pp = ap->private_data; |
| 1596 | struct ata_queued_cmd *qc; |
| 1597 | u32 out_index, in_index; |
| 1598 | bool work_done = false; |
| 1599 | |
| 1600 | /* get h/w response queue pointer */ |
| 1601 | in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) |
| 1602 | >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
| 1603 | |
| 1604 | while (1) { |
| 1605 | u16 status; |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 1606 | unsigned int tag; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1607 | |
| 1608 | /* get s/w response queue last-read pointer, and compare */ |
| 1609 | out_index = pp->resp_idx & MV_MAX_Q_DEPTH_MASK; |
| 1610 | if (in_index == out_index) |
| 1611 | break; |
| 1612 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1613 | /* 50xx: get active ATA command */ |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 1614 | if (IS_GEN_I(hpriv)) |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1615 | tag = ap->link.active_tag; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1616 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 1617 | /* Gen II/IIE: get active ATA command via tag, to enable |
| 1618 | * support for queueing. this works transparently for |
| 1619 | * queued and non-queued modes. |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1620 | */ |
Mark Lord | 8c0aeb4 | 2008-01-26 18:31:48 -0500 | [diff] [blame] | 1621 | else |
| 1622 | tag = le16_to_cpu(pp->crpb[out_index].id) & 0x1f; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1623 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 1624 | qc = ata_qc_from_tag(ap, tag); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1625 | |
Mark Lord | cb92441 | 2008-01-26 18:32:09 -0500 | [diff] [blame] | 1626 | /* For non-NCQ mode, the lower 8 bits of status |
| 1627 | * are from EDMA_ERR_IRQ_CAUSE_OFS, |
| 1628 | * which should be zero if all went well. |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1629 | */ |
| 1630 | status = le16_to_cpu(pp->crpb[out_index].flags); |
Mark Lord | cb92441 | 2008-01-26 18:32:09 -0500 | [diff] [blame] | 1631 | if ((status & 0xff) && !(pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1632 | mv_err_intr(ap, qc); |
| 1633 | return; |
| 1634 | } |
| 1635 | |
| 1636 | /* and finally, complete the ATA command */ |
| 1637 | if (qc) { |
| 1638 | qc->err_mask |= |
| 1639 | ac_err_mask(status >> CRPB_FLAG_STATUS_SHIFT); |
| 1640 | ata_qc_complete(qc); |
| 1641 | } |
| 1642 | |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 1643 | /* advance software response queue pointer, to |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1644 | * indicate (after the loop completes) to hardware |
| 1645 | * that we have consumed a response queue entry. |
| 1646 | */ |
| 1647 | work_done = true; |
| 1648 | pp->resp_idx++; |
| 1649 | } |
| 1650 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1651 | /* Update the software queue position index in hardware */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1652 | if (work_done) |
| 1653 | writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | |
| 1654 | (out_index << EDMA_RSP_Q_PTR_SHIFT), |
| 1655 | port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1656 | } |
| 1657 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1658 | /** |
| 1659 | * mv_host_intr - Handle all interrupts on the given host controller |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1660 | * @host: host specific structure |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1661 | * @relevant: port error bits relevant to this host controller |
| 1662 | * @hc: which host controller we're to look at |
| 1663 | * |
| 1664 | * Read then write clear the HC interrupt status then walk each |
| 1665 | * port connected to the HC and see if it needs servicing. Port |
| 1666 | * success ints are reported in the HC interrupt status reg, the |
| 1667 | * port error ints are reported in the higher level main |
| 1668 | * interrupt status register and thus are passed in via the |
| 1669 | * 'relevant' argument. |
| 1670 | * |
| 1671 | * LOCKING: |
| 1672 | * Inherited from caller. |
| 1673 | */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1674 | static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1675 | { |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 1676 | struct mv_host_priv *hpriv = host->private_data; |
| 1677 | void __iomem *mmio = hpriv->base; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1678 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1679 | u32 hc_irq_cause; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 1680 | int port, port0, last_port; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1681 | |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 1682 | if (hc == 0) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1683 | port0 = 0; |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 1684 | else |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1685 | port0 = MV_PORTS_PER_HC; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1686 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 1687 | if (HAS_PCI(host)) |
| 1688 | last_port = port0 + MV_PORTS_PER_HC; |
| 1689 | else |
| 1690 | last_port = port0 + hpriv->n_ports; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1691 | /* we'll need the HC success int register in most cases */ |
| 1692 | hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1693 | if (!hc_irq_cause) |
| 1694 | return; |
| 1695 | |
| 1696 | writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1697 | |
| 1698 | VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 1699 | hc, relevant, hc_irq_cause); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1700 | |
Yinghai Lu | 8f71efe | 2008-02-07 15:06:17 -0800 | [diff] [blame] | 1701 | for (port = port0; port < last_port; port++) { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1702 | struct ata_port *ap = host->ports[port]; |
Yinghai Lu | 8f71efe | 2008-02-07 15:06:17 -0800 | [diff] [blame] | 1703 | struct mv_port_priv *pp; |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1704 | int have_err_bits, hardport, shift; |
Jeff Garzik | 55d8ca4 | 2006-03-29 19:43:31 -0500 | [diff] [blame] | 1705 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1706 | if ((!ap) || (ap->flags & ATA_FLAG_DISABLED)) |
Jeff Garzik | a2c91a8 | 2005-11-17 05:44:44 -0500 | [diff] [blame] | 1707 | continue; |
| 1708 | |
Yinghai Lu | 8f71efe | 2008-02-07 15:06:17 -0800 | [diff] [blame] | 1709 | pp = ap->private_data; |
| 1710 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1711 | shift = port << 1; /* (port * 2) */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1712 | if (port >= MV_PORTS_PER_HC) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1713 | shift++; /* skip bit 8 in the HC Main IRQ reg */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1714 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1715 | have_err_bits = ((ERR_IRQ << shift) & relevant); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1716 | |
| 1717 | if (unlikely(have_err_bits)) { |
| 1718 | struct ata_queued_cmd *qc; |
| 1719 | |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1720 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1721 | if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) |
| 1722 | continue; |
| 1723 | |
| 1724 | mv_err_intr(ap, qc); |
| 1725 | continue; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1726 | } |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1727 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1728 | hardport = mv_hardport_from_port(port); /* range 0..3 */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1729 | |
| 1730 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1731 | if ((DMA_IRQ << hardport) & hc_irq_cause) |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1732 | mv_intr_edma(ap); |
| 1733 | } else { |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1734 | if ((DEV_IRQ << hardport) & hc_irq_cause) |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1735 | mv_intr_pio(ap); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1736 | } |
| 1737 | } |
| 1738 | VPRINTK("EXIT\n"); |
| 1739 | } |
| 1740 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1741 | static void mv_pci_error(struct ata_host *host, void __iomem *mmio) |
| 1742 | { |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 1743 | struct mv_host_priv *hpriv = host->private_data; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1744 | struct ata_port *ap; |
| 1745 | struct ata_queued_cmd *qc; |
| 1746 | struct ata_eh_info *ehi; |
| 1747 | unsigned int i, err_mask, printed = 0; |
| 1748 | u32 err_cause; |
| 1749 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 1750 | err_cause = readl(mmio + hpriv->irq_cause_ofs); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1751 | |
| 1752 | dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", |
| 1753 | err_cause); |
| 1754 | |
| 1755 | DPRINTK("All regs @ PCI error\n"); |
| 1756 | mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); |
| 1757 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 1758 | writelfl(0, mmio + hpriv->irq_cause_ofs); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1759 | |
| 1760 | for (i = 0; i < host->n_ports; i++) { |
| 1761 | ap = host->ports[i]; |
Tejun Heo | 936fd73 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1762 | if (!ata_link_offline(&ap->link)) { |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1763 | ehi = &ap->link.eh_info; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1764 | ata_ehi_clear_desc(ehi); |
| 1765 | if (!printed++) |
| 1766 | ata_ehi_push_desc(ehi, |
| 1767 | "PCI err cause 0x%08x", err_cause); |
| 1768 | err_mask = AC_ERR_HOST_BUS; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1769 | ehi->action = ATA_EH_RESET; |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1770 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1771 | if (qc) |
| 1772 | qc->err_mask |= err_mask; |
| 1773 | else |
| 1774 | ehi->err_mask |= err_mask; |
| 1775 | |
| 1776 | ata_port_freeze(ap); |
| 1777 | } |
| 1778 | } |
| 1779 | } |
| 1780 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1781 | /** |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1782 | * mv_interrupt - Main interrupt event handler |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1783 | * @irq: unused |
| 1784 | * @dev_instance: private data; in this case the host structure |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1785 | * |
| 1786 | * Read the read only register to determine if any host |
| 1787 | * controllers have pending interrupts. If so, call lower level |
| 1788 | * routine to handle. Also check for PCI errors which are only |
| 1789 | * reported here. |
| 1790 | * |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1791 | * LOCKING: |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1792 | * This routine holds the host lock while processing pending |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1793 | * interrupts. |
| 1794 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1795 | static irqreturn_t mv_interrupt(int irq, void *dev_instance) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1796 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1797 | struct ata_host *host = dev_instance; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 1798 | struct mv_host_priv *hpriv = host->private_data; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1799 | unsigned int hc, handled = 0, n_hcs; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 1800 | void __iomem *mmio = hpriv->base; |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1801 | u32 main_cause, main_mask; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1802 | |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 1803 | spin_lock(&host->lock); |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1804 | main_cause = readl(hpriv->main_cause_reg_addr); |
| 1805 | main_mask = readl(hpriv->main_mask_reg_addr); |
| 1806 | /* |
| 1807 | * Deal with cases where we either have nothing pending, or have read |
| 1808 | * a bogus register value which can indicate HW removal or PCI fault. |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1809 | */ |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1810 | if (!(main_cause & main_mask) || (main_cause == 0xffffffffU)) |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 1811 | goto out_unlock; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1812 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1813 | n_hcs = mv_get_hc_count(host->ports[0]->flags); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1814 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1815 | if (unlikely((main_cause & PCI_ERR) && HAS_PCI(host))) { |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1816 | mv_pci_error(host, mmio); |
| 1817 | handled = 1; |
| 1818 | goto out_unlock; /* skip all other HC irq handling */ |
| 1819 | } |
| 1820 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1821 | for (hc = 0; hc < n_hcs; hc++) { |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 1822 | u32 relevant = main_cause & (HC0_IRQ_PEND << (hc * HC_SHIFT)); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1823 | if (relevant) { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1824 | mv_host_intr(host, relevant, hc); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1825 | handled = 1; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1826 | } |
| 1827 | } |
Mark Lord | 615ab95 | 2006-05-19 16:24:56 -0400 | [diff] [blame] | 1828 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1829 | out_unlock: |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1830 | spin_unlock(&host->lock); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1831 | return IRQ_RETVAL(handled); |
| 1832 | } |
| 1833 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1834 | static unsigned int mv5_scr_offset(unsigned int sc_reg_in) |
| 1835 | { |
| 1836 | unsigned int ofs; |
| 1837 | |
| 1838 | switch (sc_reg_in) { |
| 1839 | case SCR_STATUS: |
| 1840 | case SCR_ERROR: |
| 1841 | case SCR_CONTROL: |
| 1842 | ofs = sc_reg_in * sizeof(u32); |
| 1843 | break; |
| 1844 | default: |
| 1845 | ofs = 0xffffffffU; |
| 1846 | break; |
| 1847 | } |
| 1848 | return ofs; |
| 1849 | } |
| 1850 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1851 | static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1852 | { |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 1853 | struct mv_host_priv *hpriv = ap->host->private_data; |
| 1854 | void __iomem *mmio = hpriv->base; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1855 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1856 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
| 1857 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1858 | if (ofs != 0xffffffffU) { |
| 1859 | *val = readl(addr + ofs); |
| 1860 | return 0; |
| 1861 | } else |
| 1862 | return -EINVAL; |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1863 | } |
| 1864 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1865 | static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1866 | { |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 1867 | struct mv_host_priv *hpriv = ap->host->private_data; |
| 1868 | void __iomem *mmio = hpriv->base; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1869 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1870 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
| 1871 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1872 | if (ofs != 0xffffffffU) { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1873 | writelfl(val, addr + ofs); |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1874 | return 0; |
| 1875 | } else |
| 1876 | return -EINVAL; |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1877 | } |
| 1878 | |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 1879 | static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1880 | { |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 1881 | struct pci_dev *pdev = to_pci_dev(host->dev); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1882 | int early_5080; |
| 1883 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 1884 | early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1885 | |
| 1886 | if (!early_5080) { |
| 1887 | u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); |
| 1888 | tmp |= (1 << 0); |
| 1889 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); |
| 1890 | } |
| 1891 | |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 1892 | mv_reset_pci_bus(host, mmio); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1893 | } |
| 1894 | |
| 1895 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) |
| 1896 | { |
| 1897 | writel(0x0fcfffff, mmio + MV_FLASH_CTL); |
| 1898 | } |
| 1899 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1900 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1901 | void __iomem *mmio) |
| 1902 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1903 | void __iomem *phy_mmio = mv5_phy_base(mmio, idx); |
| 1904 | u32 tmp; |
| 1905 | |
| 1906 | tmp = readl(phy_mmio + MV5_PHY_MODE); |
| 1907 | |
| 1908 | hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ |
| 1909 | hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1910 | } |
| 1911 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1912 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1913 | { |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1914 | u32 tmp; |
| 1915 | |
| 1916 | writel(0, mmio + MV_GPIO_PORT_CTL); |
| 1917 | |
| 1918 | /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ |
| 1919 | |
| 1920 | tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); |
| 1921 | tmp |= ~(1 << 0); |
| 1922 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1923 | } |
| 1924 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 1925 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1926 | unsigned int port) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1927 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1928 | void __iomem *phy_mmio = mv5_phy_base(mmio, port); |
| 1929 | const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); |
| 1930 | u32 tmp; |
| 1931 | int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); |
| 1932 | |
| 1933 | if (fix_apm_sq) { |
| 1934 | tmp = readl(phy_mmio + MV5_LT_MODE); |
| 1935 | tmp |= (1 << 19); |
| 1936 | writel(tmp, phy_mmio + MV5_LT_MODE); |
| 1937 | |
| 1938 | tmp = readl(phy_mmio + MV5_PHY_CTL); |
| 1939 | tmp &= ~0x3; |
| 1940 | tmp |= 0x1; |
| 1941 | writel(tmp, phy_mmio + MV5_PHY_CTL); |
| 1942 | } |
| 1943 | |
| 1944 | tmp = readl(phy_mmio + MV5_PHY_MODE); |
| 1945 | tmp &= ~mask; |
| 1946 | tmp |= hpriv->signal[port].pre; |
| 1947 | tmp |= hpriv->signal[port].amps; |
| 1948 | writel(tmp, phy_mmio + MV5_PHY_MODE); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1949 | } |
| 1950 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1951 | |
| 1952 | #undef ZERO |
| 1953 | #define ZERO(reg) writel(0, port_mmio + (reg)) |
| 1954 | static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1955 | unsigned int port) |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1956 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1957 | void __iomem *port_mmio = mv_port_base(mmio, port); |
| 1958 | |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 1959 | /* |
| 1960 | * The datasheet warns against setting ATA_RST when EDMA is active |
| 1961 | * (but doesn't say what the problem might be). So we first try |
| 1962 | * to disable the EDMA engine before doing the ATA_RST operation. |
| 1963 | */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1964 | mv_reset_channel(hpriv, mmio, port); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1965 | |
| 1966 | ZERO(0x028); /* command */ |
| 1967 | writel(0x11f, port_mmio + EDMA_CFG_OFS); |
| 1968 | ZERO(0x004); /* timer */ |
| 1969 | ZERO(0x008); /* irq err cause */ |
| 1970 | ZERO(0x00c); /* irq err mask */ |
| 1971 | ZERO(0x010); /* rq bah */ |
| 1972 | ZERO(0x014); /* rq inp */ |
| 1973 | ZERO(0x018); /* rq outp */ |
| 1974 | ZERO(0x01c); /* respq bah */ |
| 1975 | ZERO(0x024); /* respq outp */ |
| 1976 | ZERO(0x020); /* respq inp */ |
| 1977 | ZERO(0x02c); /* test control */ |
| 1978 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); |
| 1979 | } |
| 1980 | #undef ZERO |
| 1981 | |
| 1982 | #define ZERO(reg) writel(0, hc_mmio + (reg)) |
| 1983 | static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1984 | unsigned int hc) |
| 1985 | { |
| 1986 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
| 1987 | u32 tmp; |
| 1988 | |
| 1989 | ZERO(0x00c); |
| 1990 | ZERO(0x010); |
| 1991 | ZERO(0x014); |
| 1992 | ZERO(0x018); |
| 1993 | |
| 1994 | tmp = readl(hc_mmio + 0x20); |
| 1995 | tmp &= 0x1c1c1c1c; |
| 1996 | tmp |= 0x03030303; |
| 1997 | writel(tmp, hc_mmio + 0x20); |
| 1998 | } |
| 1999 | #undef ZERO |
| 2000 | |
| 2001 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 2002 | unsigned int n_hc) |
| 2003 | { |
| 2004 | unsigned int hc, port; |
| 2005 | |
| 2006 | for (hc = 0; hc < n_hc; hc++) { |
| 2007 | for (port = 0; port < MV_PORTS_PER_HC; port++) |
| 2008 | mv5_reset_hc_port(hpriv, mmio, |
| 2009 | (hc * MV_PORTS_PER_HC) + port); |
| 2010 | |
| 2011 | mv5_reset_one_hc(hpriv, mmio, hc); |
| 2012 | } |
| 2013 | |
| 2014 | return 0; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2015 | } |
| 2016 | |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2017 | #undef ZERO |
| 2018 | #define ZERO(reg) writel(0, mmio + (reg)) |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2019 | static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2020 | { |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 2021 | struct mv_host_priv *hpriv = host->private_data; |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2022 | u32 tmp; |
| 2023 | |
| 2024 | tmp = readl(mmio + MV_PCI_MODE); |
| 2025 | tmp &= 0xff00ffff; |
| 2026 | writel(tmp, mmio + MV_PCI_MODE); |
| 2027 | |
| 2028 | ZERO(MV_PCI_DISC_TIMER); |
| 2029 | ZERO(MV_PCI_MSI_TRIGGER); |
| 2030 | writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); |
| 2031 | ZERO(HC_MAIN_IRQ_MASK_OFS); |
| 2032 | ZERO(MV_PCI_SERR_MASK); |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 2033 | ZERO(hpriv->irq_cause_ofs); |
| 2034 | ZERO(hpriv->irq_mask_ofs); |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2035 | ZERO(MV_PCI_ERR_LOW_ADDRESS); |
| 2036 | ZERO(MV_PCI_ERR_HIGH_ADDRESS); |
| 2037 | ZERO(MV_PCI_ERR_ATTRIBUTE); |
| 2038 | ZERO(MV_PCI_ERR_COMMAND); |
| 2039 | } |
| 2040 | #undef ZERO |
| 2041 | |
| 2042 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) |
| 2043 | { |
| 2044 | u32 tmp; |
| 2045 | |
| 2046 | mv5_reset_flash(hpriv, mmio); |
| 2047 | |
| 2048 | tmp = readl(mmio + MV_GPIO_PORT_CTL); |
| 2049 | tmp &= 0x3; |
| 2050 | tmp |= (1 << 5) | (1 << 6); |
| 2051 | writel(tmp, mmio + MV_GPIO_PORT_CTL); |
| 2052 | } |
| 2053 | |
| 2054 | /** |
| 2055 | * mv6_reset_hc - Perform the 6xxx global soft reset |
| 2056 | * @mmio: base address of the HBA |
| 2057 | * |
| 2058 | * This routine only applies to 6xxx parts. |
| 2059 | * |
| 2060 | * LOCKING: |
| 2061 | * Inherited from caller. |
| 2062 | */ |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2063 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 2064 | unsigned int n_hc) |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2065 | { |
| 2066 | void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; |
| 2067 | int i, rc = 0; |
| 2068 | u32 t; |
| 2069 | |
| 2070 | /* Following procedure defined in PCI "main command and status |
| 2071 | * register" table. |
| 2072 | */ |
| 2073 | t = readl(reg); |
| 2074 | writel(t | STOP_PCI_MASTER, reg); |
| 2075 | |
| 2076 | for (i = 0; i < 1000; i++) { |
| 2077 | udelay(1); |
| 2078 | t = readl(reg); |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2079 | if (PCI_MASTER_EMPTY & t) |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2080 | break; |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2081 | } |
| 2082 | if (!(PCI_MASTER_EMPTY & t)) { |
| 2083 | printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); |
| 2084 | rc = 1; |
| 2085 | goto done; |
| 2086 | } |
| 2087 | |
| 2088 | /* set reset */ |
| 2089 | i = 5; |
| 2090 | do { |
| 2091 | writel(t | GLOB_SFT_RST, reg); |
| 2092 | t = readl(reg); |
| 2093 | udelay(1); |
| 2094 | } while (!(GLOB_SFT_RST & t) && (i-- > 0)); |
| 2095 | |
| 2096 | if (!(GLOB_SFT_RST & t)) { |
| 2097 | printk(KERN_ERR DRV_NAME ": can't set global reset\n"); |
| 2098 | rc = 1; |
| 2099 | goto done; |
| 2100 | } |
| 2101 | |
| 2102 | /* clear reset and *reenable the PCI master* (not mentioned in spec) */ |
| 2103 | i = 5; |
| 2104 | do { |
| 2105 | writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); |
| 2106 | t = readl(reg); |
| 2107 | udelay(1); |
| 2108 | } while ((GLOB_SFT_RST & t) && (i-- > 0)); |
| 2109 | |
| 2110 | if (GLOB_SFT_RST & t) { |
| 2111 | printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); |
| 2112 | rc = 1; |
| 2113 | } |
Mark Lord | 094e50b | 2008-04-16 15:01:19 -0400 | [diff] [blame] | 2114 | /* |
| 2115 | * Temporary: wait 3 seconds before port-probing can happen, |
| 2116 | * so that we don't miss finding sleepy SilXXXX port-multipliers. |
| 2117 | * This can go away once hotplug is fully/correctly implemented. |
| 2118 | */ |
| 2119 | if (rc == 0) |
| 2120 | msleep(3000); |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2121 | done: |
| 2122 | return rc; |
| 2123 | } |
| 2124 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2125 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 2126 | void __iomem *mmio) |
| 2127 | { |
| 2128 | void __iomem *port_mmio; |
| 2129 | u32 tmp; |
| 2130 | |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 2131 | tmp = readl(mmio + MV_RESET_CFG); |
| 2132 | if ((tmp & (1 << 0)) == 0) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2133 | hpriv->signal[idx].amps = 0x7 << 8; |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 2134 | hpriv->signal[idx].pre = 0x1 << 5; |
| 2135 | return; |
| 2136 | } |
| 2137 | |
| 2138 | port_mmio = mv_port_base(mmio, idx); |
| 2139 | tmp = readl(port_mmio + PHY_MODE2); |
| 2140 | |
| 2141 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ |
| 2142 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ |
| 2143 | } |
| 2144 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2145 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 2146 | { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2147 | writel(0x00000060, mmio + MV_GPIO_PORT_CTL); |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 2148 | } |
| 2149 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2150 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2151 | unsigned int port) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2152 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2153 | void __iomem *port_mmio = mv_port_base(mmio, port); |
| 2154 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2155 | u32 hp_flags = hpriv->hp_flags; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2156 | int fix_phy_mode2 = |
| 2157 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2158 | int fix_phy_mode4 = |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2159 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
| 2160 | u32 m2, tmp; |
| 2161 | |
| 2162 | if (fix_phy_mode2) { |
| 2163 | m2 = readl(port_mmio + PHY_MODE2); |
| 2164 | m2 &= ~(1 << 16); |
| 2165 | m2 |= (1 << 31); |
| 2166 | writel(m2, port_mmio + PHY_MODE2); |
| 2167 | |
| 2168 | udelay(200); |
| 2169 | |
| 2170 | m2 = readl(port_mmio + PHY_MODE2); |
| 2171 | m2 &= ~((1 << 16) | (1 << 31)); |
| 2172 | writel(m2, port_mmio + PHY_MODE2); |
| 2173 | |
| 2174 | udelay(200); |
| 2175 | } |
| 2176 | |
| 2177 | /* who knows what this magic does */ |
| 2178 | tmp = readl(port_mmio + PHY_MODE3); |
| 2179 | tmp &= ~0x7F800000; |
| 2180 | tmp |= 0x2A800000; |
| 2181 | writel(tmp, port_mmio + PHY_MODE3); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2182 | |
| 2183 | if (fix_phy_mode4) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2184 | u32 m4; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2185 | |
| 2186 | m4 = readl(port_mmio + PHY_MODE4); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2187 | |
| 2188 | if (hp_flags & MV_HP_ERRATA_60X1B2) |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 2189 | tmp = readl(port_mmio + PHY_MODE3); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2190 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 2191 | /* workaround for errata FEr SATA#10 (part 1) */ |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2192 | m4 = (m4 & ~(1 << 1)) | (1 << 0); |
| 2193 | |
| 2194 | writel(m4, port_mmio + PHY_MODE4); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2195 | |
| 2196 | if (hp_flags & MV_HP_ERRATA_60X1B2) |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 2197 | writel(tmp, port_mmio + PHY_MODE3); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2198 | } |
| 2199 | |
| 2200 | /* Revert values of pre-emphasis and signal amps to the saved ones */ |
| 2201 | m2 = readl(port_mmio + PHY_MODE2); |
| 2202 | |
| 2203 | m2 &= ~MV_M2_PREAMP_MASK; |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2204 | m2 |= hpriv->signal[port].amps; |
| 2205 | m2 |= hpriv->signal[port].pre; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2206 | m2 &= ~(1 << 16); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2207 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2208 | /* according to mvSata 3.6.1, some IIE values are fixed */ |
| 2209 | if (IS_GEN_IIE(hpriv)) { |
| 2210 | m2 &= ~0xC30FF01F; |
| 2211 | m2 |= 0x0000900F; |
| 2212 | } |
| 2213 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2214 | writel(m2, port_mmio + PHY_MODE2); |
| 2215 | } |
| 2216 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2217 | /* TODO: use the generic LED interface to configure the SATA Presence */ |
| 2218 | /* & Acitivy LEDs on the board */ |
| 2219 | static void mv_soc_enable_leds(struct mv_host_priv *hpriv, |
| 2220 | void __iomem *mmio) |
| 2221 | { |
| 2222 | return; |
| 2223 | } |
| 2224 | |
| 2225 | static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, |
| 2226 | void __iomem *mmio) |
| 2227 | { |
| 2228 | void __iomem *port_mmio; |
| 2229 | u32 tmp; |
| 2230 | |
| 2231 | port_mmio = mv_port_base(mmio, idx); |
| 2232 | tmp = readl(port_mmio + PHY_MODE2); |
| 2233 | |
| 2234 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ |
| 2235 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ |
| 2236 | } |
| 2237 | |
| 2238 | #undef ZERO |
| 2239 | #define ZERO(reg) writel(0, port_mmio + (reg)) |
| 2240 | static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, |
| 2241 | void __iomem *mmio, unsigned int port) |
| 2242 | { |
| 2243 | void __iomem *port_mmio = mv_port_base(mmio, port); |
| 2244 | |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 2245 | /* |
| 2246 | * The datasheet warns against setting ATA_RST when EDMA is active |
| 2247 | * (but doesn't say what the problem might be). So we first try |
| 2248 | * to disable the EDMA engine before doing the ATA_RST operation. |
| 2249 | */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 2250 | mv_reset_channel(hpriv, mmio, port); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2251 | |
| 2252 | ZERO(0x028); /* command */ |
| 2253 | writel(0x101f, port_mmio + EDMA_CFG_OFS); |
| 2254 | ZERO(0x004); /* timer */ |
| 2255 | ZERO(0x008); /* irq err cause */ |
| 2256 | ZERO(0x00c); /* irq err mask */ |
| 2257 | ZERO(0x010); /* rq bah */ |
| 2258 | ZERO(0x014); /* rq inp */ |
| 2259 | ZERO(0x018); /* rq outp */ |
| 2260 | ZERO(0x01c); /* respq bah */ |
| 2261 | ZERO(0x024); /* respq outp */ |
| 2262 | ZERO(0x020); /* respq inp */ |
| 2263 | ZERO(0x02c); /* test control */ |
| 2264 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); |
| 2265 | } |
| 2266 | |
| 2267 | #undef ZERO |
| 2268 | |
| 2269 | #define ZERO(reg) writel(0, hc_mmio + (reg)) |
| 2270 | static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, |
| 2271 | void __iomem *mmio) |
| 2272 | { |
| 2273 | void __iomem *hc_mmio = mv_hc_base(mmio, 0); |
| 2274 | |
| 2275 | ZERO(0x00c); |
| 2276 | ZERO(0x010); |
| 2277 | ZERO(0x014); |
| 2278 | |
| 2279 | } |
| 2280 | |
| 2281 | #undef ZERO |
| 2282 | |
| 2283 | static int mv_soc_reset_hc(struct mv_host_priv *hpriv, |
| 2284 | void __iomem *mmio, unsigned int n_hc) |
| 2285 | { |
| 2286 | unsigned int port; |
| 2287 | |
| 2288 | for (port = 0; port < hpriv->n_ports; port++) |
| 2289 | mv_soc_reset_hc_port(hpriv, mmio, port); |
| 2290 | |
| 2291 | mv_soc_reset_one_hc(hpriv, mmio); |
| 2292 | |
| 2293 | return 0; |
| 2294 | } |
| 2295 | |
| 2296 | static void mv_soc_reset_flash(struct mv_host_priv *hpriv, |
| 2297 | void __iomem *mmio) |
| 2298 | { |
| 2299 | return; |
| 2300 | } |
| 2301 | |
| 2302 | static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) |
| 2303 | { |
| 2304 | return; |
| 2305 | } |
| 2306 | |
Mark Lord | b67a106 | 2008-03-31 19:35:13 -0400 | [diff] [blame] | 2307 | static void mv_setup_ifctl(void __iomem *port_mmio, int want_gen2i) |
| 2308 | { |
| 2309 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); |
| 2310 | |
| 2311 | ifctl = (ifctl & 0xf7f) | 0x9b1000; /* from chip spec */ |
| 2312 | if (want_gen2i) |
| 2313 | ifctl |= (1 << 7); /* enable gen2i speed */ |
| 2314 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); |
| 2315 | } |
| 2316 | |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 2317 | /* |
| 2318 | * Caller must ensure that EDMA is not active, |
| 2319 | * by first doing mv_stop_edma() where needed. |
| 2320 | */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 2321 | static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2322 | unsigned int port_no) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2323 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2324 | void __iomem *port_mmio = mv_port_base(mmio, port_no); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2325 | |
Mark Lord | 0d8be5c | 2008-04-16 14:56:12 -0400 | [diff] [blame] | 2326 | mv_stop_edma_engine(port_mmio); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2327 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2328 | |
Mark Lord | b67a106 | 2008-03-31 19:35:13 -0400 | [diff] [blame] | 2329 | if (!IS_GEN_I(hpriv)) { |
| 2330 | /* Enable 3.0gb/s link speed */ |
| 2331 | mv_setup_ifctl(port_mmio, 1); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2332 | } |
Mark Lord | b67a106 | 2008-03-31 19:35:13 -0400 | [diff] [blame] | 2333 | /* |
| 2334 | * Strobing ATA_RST here causes a hard reset of the SATA transport, |
| 2335 | * link, and physical layers. It resets all SATA interface registers |
| 2336 | * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2337 | */ |
Mark Lord | b67a106 | 2008-03-31 19:35:13 -0400 | [diff] [blame] | 2338 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); |
| 2339 | udelay(25); /* allow reset propagation */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2340 | writelfl(0, port_mmio + EDMA_CMD_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2341 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2342 | hpriv->ops->phy_errata(hpriv, mmio, port_no); |
| 2343 | |
Jeff Garzik | ee9ccdf | 2007-07-12 15:51:22 -0400 | [diff] [blame] | 2344 | if (IS_GEN_I(hpriv)) |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2345 | mdelay(1); |
| 2346 | } |
| 2347 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 2348 | static void mv_pmp_select(struct ata_port *ap, int pmp) |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2349 | { |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 2350 | if (sata_pmp_supported(ap)) { |
| 2351 | void __iomem *port_mmio = mv_ap_base(ap); |
| 2352 | u32 reg = readl(port_mmio + SATA_IFCTL_OFS); |
| 2353 | int old = reg & 0xf; |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2354 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 2355 | if (old != pmp) { |
| 2356 | reg = (reg & ~0xf) | pmp; |
| 2357 | writelfl(reg, port_mmio + SATA_IFCTL_OFS); |
| 2358 | } |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 2359 | } |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2360 | } |
| 2361 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 2362 | static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, |
| 2363 | unsigned long deadline) |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2364 | { |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 2365 | mv_pmp_select(link->ap, sata_srst_pmp(link)); |
| 2366 | return sata_std_hardreset(link, class, deadline); |
| 2367 | } |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 2368 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 2369 | static int mv_softreset(struct ata_link *link, unsigned int *class, |
| 2370 | unsigned long deadline) |
| 2371 | { |
| 2372 | mv_pmp_select(link->ap, sata_srst_pmp(link)); |
| 2373 | return ata_sff_softreset(link, class, deadline); |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2374 | } |
| 2375 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 2376 | static int mv_hardreset(struct ata_link *link, unsigned int *class, |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2377 | unsigned long deadline) |
| 2378 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 2379 | struct ata_port *ap = link->ap; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2380 | struct mv_host_priv *hpriv = ap->host->private_data; |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 2381 | struct mv_port_priv *pp = ap->private_data; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2382 | void __iomem *mmio = hpriv->base; |
Mark Lord | 0d8be5c | 2008-04-16 14:56:12 -0400 | [diff] [blame] | 2383 | int rc, attempts = 0, extra = 0; |
| 2384 | u32 sstatus; |
| 2385 | bool online; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2386 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 2387 | mv_reset_channel(hpriv, mmio, ap->port_no); |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 2388 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2389 | |
Mark Lord | 0d8be5c | 2008-04-16 14:56:12 -0400 | [diff] [blame] | 2390 | /* Workaround for errata FEr SATA#10 (part 2) */ |
| 2391 | do { |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 2392 | const unsigned long *timing = |
| 2393 | sata_ehc_deb_timing(&link->eh_context); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2394 | |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 2395 | rc = sata_link_hardreset(link, timing, deadline + extra, |
| 2396 | &online, NULL); |
| 2397 | if (rc) |
Mark Lord | 0d8be5c | 2008-04-16 14:56:12 -0400 | [diff] [blame] | 2398 | return rc; |
Mark Lord | 0d8be5c | 2008-04-16 14:56:12 -0400 | [diff] [blame] | 2399 | sata_scr_read(link, SCR_STATUS, &sstatus); |
| 2400 | if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { |
| 2401 | /* Force 1.5gb/s link speed and try again */ |
| 2402 | mv_setup_ifctl(mv_ap_base(ap), 0); |
| 2403 | if (time_after(jiffies + HZ, deadline)) |
| 2404 | extra = HZ; /* only extend it once, max */ |
| 2405 | } |
| 2406 | } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2407 | |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 2408 | return rc; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2409 | } |
| 2410 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2411 | static void mv_eh_freeze(struct ata_port *ap) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2412 | { |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2413 | struct mv_host_priv *hpriv = ap->host->private_data; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2414 | unsigned int hc = (ap->port_no > 3) ? 1 : 0; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2415 | unsigned int shift; |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 2416 | u32 main_mask; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2417 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2418 | /* FIXME: handle coalescing completion events properly */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2419 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2420 | shift = ap->port_no * 2; |
| 2421 | if (hc > 0) |
| 2422 | shift++; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2423 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2424 | /* disable assertion of portN err, done events */ |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 2425 | main_mask = readl(hpriv->main_mask_reg_addr); |
| 2426 | main_mask &= ~((DONE_IRQ | ERR_IRQ) << shift); |
| 2427 | writelfl(main_mask, hpriv->main_mask_reg_addr); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2428 | } |
| 2429 | |
| 2430 | static void mv_eh_thaw(struct ata_port *ap) |
| 2431 | { |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2432 | struct mv_host_priv *hpriv = ap->host->private_data; |
| 2433 | void __iomem *mmio = hpriv->base; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2434 | unsigned int hc = (ap->port_no > 3) ? 1 : 0; |
| 2435 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
| 2436 | void __iomem *port_mmio = mv_ap_base(ap); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2437 | unsigned int shift, hc_port_no = ap->port_no; |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 2438 | u32 main_mask, hc_irq_cause; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2439 | |
| 2440 | /* FIXME: handle coalescing completion events properly */ |
| 2441 | |
| 2442 | shift = ap->port_no * 2; |
| 2443 | if (hc > 0) { |
| 2444 | shift++; |
| 2445 | hc_port_no -= 4; |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 2446 | } |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2447 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2448 | /* clear EDMA errors on this port */ |
| 2449 | writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 2450 | |
| 2451 | /* clear pending irq events */ |
| 2452 | hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 2453 | hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hc_port_no); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2454 | writel(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); |
| 2455 | |
| 2456 | /* enable assertion of portN err, done events */ |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 2457 | main_mask = readl(hpriv->main_mask_reg_addr); |
| 2458 | main_mask |= ((DONE_IRQ | ERR_IRQ) << shift); |
| 2459 | writelfl(main_mask, hpriv->main_mask_reg_addr); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2460 | } |
| 2461 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2462 | /** |
| 2463 | * mv_port_init - Perform some early initialization on a single port. |
| 2464 | * @port: libata data structure storing shadow register addresses |
| 2465 | * @port_mmio: base address of the port |
| 2466 | * |
| 2467 | * Initialize shadow register mmio addresses, clear outstanding |
| 2468 | * interrupts on the port, and unmask interrupts for the future |
| 2469 | * start of the port. |
| 2470 | * |
| 2471 | * LOCKING: |
| 2472 | * Inherited from caller. |
| 2473 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2474 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) |
| 2475 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2476 | void __iomem *shd_base = port_mmio + SHD_BLK_OFS; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2477 | unsigned serr_ofs; |
| 2478 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2479 | /* PIO related setup |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2480 | */ |
| 2481 | port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2482 | port->error_addr = |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2483 | port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); |
| 2484 | port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); |
| 2485 | port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); |
| 2486 | port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); |
| 2487 | port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); |
| 2488 | port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2489 | port->status_addr = |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2490 | port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); |
| 2491 | /* special case: control/altstatus doesn't have ATA_REG_ address */ |
| 2492 | port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; |
| 2493 | |
| 2494 | /* unused: */ |
Randy Dunlap | 8d9db2d | 2007-02-16 01:40:06 -0800 | [diff] [blame] | 2495 | port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2496 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2497 | /* Clear any currently outstanding port interrupt conditions */ |
| 2498 | serr_ofs = mv_scr_offset(SCR_ERROR); |
| 2499 | writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); |
| 2500 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 2501 | |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 2502 | /* unmask all non-transient EDMA error interrupts */ |
| 2503 | writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2504 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2505 | VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2506 | readl(port_mmio + EDMA_CFG_OFS), |
| 2507 | readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), |
| 2508 | readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2509 | } |
| 2510 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2511 | static int mv_chip_id(struct ata_host *host, unsigned int board_idx) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2512 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2513 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 2514 | struct mv_host_priv *hpriv = host->private_data; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2515 | u32 hp_flags = hpriv->hp_flags; |
| 2516 | |
Jeff Garzik | 5796d1c | 2007-10-26 00:03:37 -0400 | [diff] [blame] | 2517 | switch (board_idx) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2518 | case chip_5080: |
| 2519 | hpriv->ops = &mv5xxx_ops; |
Jeff Garzik | ee9ccdf | 2007-07-12 15:51:22 -0400 | [diff] [blame] | 2520 | hp_flags |= MV_HP_GEN_I; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2521 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 2522 | switch (pdev->revision) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2523 | case 0x1: |
| 2524 | hp_flags |= MV_HP_ERRATA_50XXB0; |
| 2525 | break; |
| 2526 | case 0x3: |
| 2527 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2528 | break; |
| 2529 | default: |
| 2530 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2531 | "Applying 50XXB2 workarounds to unknown rev\n"); |
| 2532 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2533 | break; |
| 2534 | } |
| 2535 | break; |
| 2536 | |
| 2537 | case chip_504x: |
| 2538 | case chip_508x: |
| 2539 | hpriv->ops = &mv5xxx_ops; |
Jeff Garzik | ee9ccdf | 2007-07-12 15:51:22 -0400 | [diff] [blame] | 2540 | hp_flags |= MV_HP_GEN_I; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2541 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 2542 | switch (pdev->revision) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2543 | case 0x0: |
| 2544 | hp_flags |= MV_HP_ERRATA_50XXB0; |
| 2545 | break; |
| 2546 | case 0x3: |
| 2547 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2548 | break; |
| 2549 | default: |
| 2550 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2551 | "Applying B2 workarounds to unknown rev\n"); |
| 2552 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2553 | break; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2554 | } |
| 2555 | break; |
| 2556 | |
| 2557 | case chip_604x: |
| 2558 | case chip_608x: |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2559 | hpriv->ops = &mv6xxx_ops; |
Jeff Garzik | ee9ccdf | 2007-07-12 15:51:22 -0400 | [diff] [blame] | 2560 | hp_flags |= MV_HP_GEN_II; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2561 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 2562 | switch (pdev->revision) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2563 | case 0x7: |
| 2564 | hp_flags |= MV_HP_ERRATA_60X1B2; |
| 2565 | break; |
| 2566 | case 0x9: |
| 2567 | hp_flags |= MV_HP_ERRATA_60X1C0; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2568 | break; |
| 2569 | default: |
| 2570 | dev_printk(KERN_WARNING, &pdev->dev, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2571 | "Applying B2 workarounds to unknown rev\n"); |
| 2572 | hp_flags |= MV_HP_ERRATA_60X1B2; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2573 | break; |
| 2574 | } |
| 2575 | break; |
| 2576 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2577 | case chip_7042: |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 2578 | hp_flags |= MV_HP_PCIE; |
Mark Lord | 306b30f | 2007-12-04 14:07:52 -0500 | [diff] [blame] | 2579 | if (pdev->vendor == PCI_VENDOR_ID_TTI && |
| 2580 | (pdev->device == 0x2300 || pdev->device == 0x2310)) |
| 2581 | { |
Mark Lord | 4e52003 | 2007-12-11 12:58:05 -0500 | [diff] [blame] | 2582 | /* |
| 2583 | * Highpoint RocketRAID PCIe 23xx series cards: |
| 2584 | * |
| 2585 | * Unconfigured drives are treated as "Legacy" |
| 2586 | * by the BIOS, and it overwrites sector 8 with |
| 2587 | * a "Lgcy" metadata block prior to Linux boot. |
| 2588 | * |
| 2589 | * Configured drives (RAID or JBOD) leave sector 8 |
| 2590 | * alone, but instead overwrite a high numbered |
| 2591 | * sector for the RAID metadata. This sector can |
| 2592 | * be determined exactly, by truncating the physical |
| 2593 | * drive capacity to a nice even GB value. |
| 2594 | * |
| 2595 | * RAID metadata is at: (dev->n_sectors & ~0xfffff) |
| 2596 | * |
| 2597 | * Warn the user, lest they think we're just buggy. |
| 2598 | */ |
| 2599 | printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" |
| 2600 | " BIOS CORRUPTS DATA on all attached drives," |
| 2601 | " regardless of if/how they are configured." |
| 2602 | " BEWARE!\n"); |
| 2603 | printk(KERN_WARNING DRV_NAME ": For data safety, do not" |
| 2604 | " use sectors 8-9 on \"Legacy\" drives," |
| 2605 | " and avoid the final two gigabytes on" |
| 2606 | " all RocketRAID BIOS initialized drives.\n"); |
Mark Lord | 306b30f | 2007-12-04 14:07:52 -0500 | [diff] [blame] | 2607 | } |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2608 | case chip_6042: |
| 2609 | hpriv->ops = &mv6xxx_ops; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2610 | hp_flags |= MV_HP_GEN_IIE; |
| 2611 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 2612 | switch (pdev->revision) { |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2613 | case 0x0: |
| 2614 | hp_flags |= MV_HP_ERRATA_XX42A0; |
| 2615 | break; |
| 2616 | case 0x1: |
| 2617 | hp_flags |= MV_HP_ERRATA_60X1C0; |
| 2618 | break; |
| 2619 | default: |
| 2620 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2621 | "Applying 60X1C0 workarounds to unknown rev\n"); |
| 2622 | hp_flags |= MV_HP_ERRATA_60X1C0; |
| 2623 | break; |
| 2624 | } |
| 2625 | break; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2626 | case chip_soc: |
| 2627 | hpriv->ops = &mv_soc_ops; |
| 2628 | hp_flags |= MV_HP_ERRATA_60X1C0; |
| 2629 | break; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2630 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2631 | default: |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2632 | dev_printk(KERN_ERR, host->dev, |
Jeff Garzik | 5796d1c | 2007-10-26 00:03:37 -0400 | [diff] [blame] | 2633 | "BUG: invalid board index %u\n", board_idx); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2634 | return 1; |
| 2635 | } |
| 2636 | |
| 2637 | hpriv->hp_flags = hp_flags; |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 2638 | if (hp_flags & MV_HP_PCIE) { |
| 2639 | hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; |
| 2640 | hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; |
| 2641 | hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; |
| 2642 | } else { |
| 2643 | hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; |
| 2644 | hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; |
| 2645 | hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; |
| 2646 | } |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2647 | |
| 2648 | return 0; |
| 2649 | } |
| 2650 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2651 | /** |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2652 | * mv_init_host - Perform some early initialization of the host. |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2653 | * @host: ATA host to initialize |
| 2654 | * @board_idx: controller index |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2655 | * |
| 2656 | * If possible, do an early global reset of the host. Then do |
| 2657 | * our port init and clear/unmask all/relevant host interrupts. |
| 2658 | * |
| 2659 | * LOCKING: |
| 2660 | * Inherited from caller. |
| 2661 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2662 | static int mv_init_host(struct ata_host *host, unsigned int board_idx) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2663 | { |
| 2664 | int rc = 0, n_hc, port, hc; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2665 | struct mv_host_priv *hpriv = host->private_data; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2666 | void __iomem *mmio = hpriv->base; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2667 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2668 | rc = mv_chip_id(host, board_idx); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2669 | if (rc) |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 2670 | goto done; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2671 | |
| 2672 | if (HAS_PCI(host)) { |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 2673 | hpriv->main_cause_reg_addr = mmio + HC_MAIN_IRQ_CAUSE_OFS; |
| 2674 | hpriv->main_mask_reg_addr = mmio + HC_MAIN_IRQ_MASK_OFS; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2675 | } else { |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 2676 | hpriv->main_cause_reg_addr = mmio + HC_SOC_MAIN_IRQ_CAUSE_OFS; |
| 2677 | hpriv->main_mask_reg_addr = mmio + HC_SOC_MAIN_IRQ_MASK_OFS; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2678 | } |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame^] | 2679 | |
| 2680 | /* global interrupt mask: 0 == mask everything */ |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2681 | writel(0, hpriv->main_mask_reg_addr); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2682 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2683 | n_hc = mv_get_hc_count(host->ports[0]->flags); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2684 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2685 | for (port = 0; port < host->n_ports; port++) |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2686 | hpriv->ops->read_preamp(hpriv, port, mmio); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2687 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2688 | rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2689 | if (rc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2690 | goto done; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2691 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 2692 | hpriv->ops->reset_flash(hpriv, mmio); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2693 | hpriv->ops->reset_bus(host, mmio); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2694 | hpriv->ops->enable_leds(hpriv, mmio); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2695 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2696 | for (port = 0; port < host->n_ports; port++) { |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 2697 | struct ata_port *ap = host->ports[port]; |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2698 | void __iomem *port_mmio = mv_port_base(mmio, port); |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 2699 | |
| 2700 | mv_port_init(&ap->ioaddr, port_mmio); |
| 2701 | |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2702 | #ifdef CONFIG_PCI |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2703 | if (HAS_PCI(host)) { |
| 2704 | unsigned int offset = port_mmio - mmio; |
| 2705 | ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); |
| 2706 | ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); |
| 2707 | } |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2708 | #endif |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2709 | } |
| 2710 | |
| 2711 | for (hc = 0; hc < n_hc; hc++) { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2712 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
| 2713 | |
| 2714 | VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " |
| 2715 | "(before clear)=0x%08x\n", hc, |
| 2716 | readl(hc_mmio + HC_CFG_OFS), |
| 2717 | readl(hc_mmio + HC_IRQ_CAUSE_OFS)); |
| 2718 | |
| 2719 | /* Clear any currently outstanding hc interrupt conditions */ |
| 2720 | writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2721 | } |
| 2722 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2723 | if (HAS_PCI(host)) { |
| 2724 | /* Clear any currently outstanding host interrupt conditions */ |
| 2725 | writelfl(0, mmio + hpriv->irq_cause_ofs); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2726 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2727 | /* and unmask interrupt generation for host regs */ |
| 2728 | writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); |
| 2729 | if (IS_GEN_I(hpriv)) |
| 2730 | writelfl(~HC_MAIN_MASKED_IRQS_5, |
| 2731 | hpriv->main_mask_reg_addr); |
| 2732 | else |
| 2733 | writelfl(~HC_MAIN_MASKED_IRQS, |
| 2734 | hpriv->main_mask_reg_addr); |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 2735 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2736 | VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " |
| 2737 | "PCI int cause/mask=0x%08x/0x%08x\n", |
| 2738 | readl(hpriv->main_cause_reg_addr), |
| 2739 | readl(hpriv->main_mask_reg_addr), |
| 2740 | readl(mmio + hpriv->irq_cause_ofs), |
| 2741 | readl(mmio + hpriv->irq_mask_ofs)); |
| 2742 | } else { |
| 2743 | writelfl(~HC_MAIN_MASKED_IRQS_SOC, |
| 2744 | hpriv->main_mask_reg_addr); |
| 2745 | VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n", |
| 2746 | readl(hpriv->main_cause_reg_addr), |
| 2747 | readl(hpriv->main_mask_reg_addr)); |
| 2748 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2749 | done: |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2750 | return rc; |
| 2751 | } |
| 2752 | |
Byron Bradley | fbf14e2 | 2008-02-10 21:17:30 +0000 | [diff] [blame] | 2753 | static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) |
| 2754 | { |
| 2755 | hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, |
| 2756 | MV_CRQB_Q_SZ, 0); |
| 2757 | if (!hpriv->crqb_pool) |
| 2758 | return -ENOMEM; |
| 2759 | |
| 2760 | hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, |
| 2761 | MV_CRPB_Q_SZ, 0); |
| 2762 | if (!hpriv->crpb_pool) |
| 2763 | return -ENOMEM; |
| 2764 | |
| 2765 | hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, |
| 2766 | MV_SG_TBL_SZ, 0); |
| 2767 | if (!hpriv->sg_tbl_pool) |
| 2768 | return -ENOMEM; |
| 2769 | |
| 2770 | return 0; |
| 2771 | } |
| 2772 | |
Lennert Buytenhek | 15a3263 | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 2773 | static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, |
| 2774 | struct mbus_dram_target_info *dram) |
| 2775 | { |
| 2776 | int i; |
| 2777 | |
| 2778 | for (i = 0; i < 4; i++) { |
| 2779 | writel(0, hpriv->base + WINDOW_CTRL(i)); |
| 2780 | writel(0, hpriv->base + WINDOW_BASE(i)); |
| 2781 | } |
| 2782 | |
| 2783 | for (i = 0; i < dram->num_cs; i++) { |
| 2784 | struct mbus_dram_window *cs = dram->cs + i; |
| 2785 | |
| 2786 | writel(((cs->size - 1) & 0xffff0000) | |
| 2787 | (cs->mbus_attr << 8) | |
| 2788 | (dram->mbus_dram_target_id << 4) | 1, |
| 2789 | hpriv->base + WINDOW_CTRL(i)); |
| 2790 | writel(cs->base, hpriv->base + WINDOW_BASE(i)); |
| 2791 | } |
| 2792 | } |
| 2793 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2794 | /** |
| 2795 | * mv_platform_probe - handle a positive probe of an soc Marvell |
| 2796 | * host |
| 2797 | * @pdev: platform device found |
| 2798 | * |
| 2799 | * LOCKING: |
| 2800 | * Inherited from caller. |
| 2801 | */ |
| 2802 | static int mv_platform_probe(struct platform_device *pdev) |
| 2803 | { |
| 2804 | static int printed_version; |
| 2805 | const struct mv_sata_platform_data *mv_platform_data; |
| 2806 | const struct ata_port_info *ppi[] = |
| 2807 | { &mv_port_info[chip_soc], NULL }; |
| 2808 | struct ata_host *host; |
| 2809 | struct mv_host_priv *hpriv; |
| 2810 | struct resource *res; |
| 2811 | int n_ports, rc; |
| 2812 | |
| 2813 | if (!printed_version++) |
| 2814 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); |
| 2815 | |
| 2816 | /* |
| 2817 | * Simple resource validation .. |
| 2818 | */ |
| 2819 | if (unlikely(pdev->num_resources != 2)) { |
| 2820 | dev_err(&pdev->dev, "invalid number of resources\n"); |
| 2821 | return -EINVAL; |
| 2822 | } |
| 2823 | |
| 2824 | /* |
| 2825 | * Get the register base first |
| 2826 | */ |
| 2827 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 2828 | if (res == NULL) |
| 2829 | return -EINVAL; |
| 2830 | |
| 2831 | /* allocate host */ |
| 2832 | mv_platform_data = pdev->dev.platform_data; |
| 2833 | n_ports = mv_platform_data->n_ports; |
| 2834 | |
| 2835 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
| 2836 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); |
| 2837 | |
| 2838 | if (!host || !hpriv) |
| 2839 | return -ENOMEM; |
| 2840 | host->private_data = hpriv; |
| 2841 | hpriv->n_ports = n_ports; |
| 2842 | |
| 2843 | host->iomap = NULL; |
Saeed Bishara | f1cb0ea | 2008-02-18 07:42:28 -1100 | [diff] [blame] | 2844 | hpriv->base = devm_ioremap(&pdev->dev, res->start, |
| 2845 | res->end - res->start + 1); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2846 | hpriv->base -= MV_SATAHC0_REG_BASE; |
| 2847 | |
Lennert Buytenhek | 15a3263 | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 2848 | /* |
| 2849 | * (Re-)program MBUS remapping windows if we are asked to. |
| 2850 | */ |
| 2851 | if (mv_platform_data->dram != NULL) |
| 2852 | mv_conf_mbus_windows(hpriv, mv_platform_data->dram); |
| 2853 | |
Byron Bradley | fbf14e2 | 2008-02-10 21:17:30 +0000 | [diff] [blame] | 2854 | rc = mv_create_dma_pools(hpriv, &pdev->dev); |
| 2855 | if (rc) |
| 2856 | return rc; |
| 2857 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2858 | /* initialize adapter */ |
| 2859 | rc = mv_init_host(host, chip_soc); |
| 2860 | if (rc) |
| 2861 | return rc; |
| 2862 | |
| 2863 | dev_printk(KERN_INFO, &pdev->dev, |
| 2864 | "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, |
| 2865 | host->n_ports); |
| 2866 | |
| 2867 | return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, |
| 2868 | IRQF_SHARED, &mv6_sht); |
| 2869 | } |
| 2870 | |
| 2871 | /* |
| 2872 | * |
| 2873 | * mv_platform_remove - unplug a platform interface |
| 2874 | * @pdev: platform device |
| 2875 | * |
| 2876 | * A platform bus SATA device has been unplugged. Perform the needed |
| 2877 | * cleanup. Also called on module unload for any active devices. |
| 2878 | */ |
| 2879 | static int __devexit mv_platform_remove(struct platform_device *pdev) |
| 2880 | { |
| 2881 | struct device *dev = &pdev->dev; |
| 2882 | struct ata_host *host = dev_get_drvdata(dev); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2883 | |
| 2884 | ata_host_detach(host); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2885 | return 0; |
| 2886 | } |
| 2887 | |
| 2888 | static struct platform_driver mv_platform_driver = { |
| 2889 | .probe = mv_platform_probe, |
| 2890 | .remove = __devexit_p(mv_platform_remove), |
| 2891 | .driver = { |
| 2892 | .name = DRV_NAME, |
| 2893 | .owner = THIS_MODULE, |
| 2894 | }, |
| 2895 | }; |
| 2896 | |
| 2897 | |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2898 | #ifdef CONFIG_PCI |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2899 | static int mv_pci_init_one(struct pci_dev *pdev, |
| 2900 | const struct pci_device_id *ent); |
| 2901 | |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2902 | |
| 2903 | static struct pci_driver mv_pci_driver = { |
| 2904 | .name = DRV_NAME, |
| 2905 | .id_table = mv_pci_tbl, |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2906 | .probe = mv_pci_init_one, |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2907 | .remove = ata_pci_remove_one, |
| 2908 | }; |
| 2909 | |
| 2910 | /* |
| 2911 | * module options |
| 2912 | */ |
| 2913 | static int msi; /* Use PCI msi; either zero (off, default) or non-zero */ |
| 2914 | |
| 2915 | |
| 2916 | /* move to PCI layer or libata core? */ |
| 2917 | static int pci_go_64(struct pci_dev *pdev) |
| 2918 | { |
| 2919 | int rc; |
| 2920 | |
| 2921 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 2922 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| 2923 | if (rc) { |
| 2924 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 2925 | if (rc) { |
| 2926 | dev_printk(KERN_ERR, &pdev->dev, |
| 2927 | "64-bit DMA enable failed\n"); |
| 2928 | return rc; |
| 2929 | } |
| 2930 | } |
| 2931 | } else { |
| 2932 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 2933 | if (rc) { |
| 2934 | dev_printk(KERN_ERR, &pdev->dev, |
| 2935 | "32-bit DMA enable failed\n"); |
| 2936 | return rc; |
| 2937 | } |
| 2938 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 2939 | if (rc) { |
| 2940 | dev_printk(KERN_ERR, &pdev->dev, |
| 2941 | "32-bit consistent DMA enable failed\n"); |
| 2942 | return rc; |
| 2943 | } |
| 2944 | } |
| 2945 | |
| 2946 | return rc; |
| 2947 | } |
| 2948 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2949 | /** |
| 2950 | * mv_print_info - Dump key info to kernel log for perusal. |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2951 | * @host: ATA host to print info about |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2952 | * |
| 2953 | * FIXME: complete this. |
| 2954 | * |
| 2955 | * LOCKING: |
| 2956 | * Inherited from caller. |
| 2957 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2958 | static void mv_print_info(struct ata_host *host) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2959 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2960 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 2961 | struct mv_host_priv *hpriv = host->private_data; |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 2962 | u8 scc; |
Jeff Garzik | c1e4fe7 | 2007-07-09 12:29:31 -0400 | [diff] [blame] | 2963 | const char *scc_s, *gen; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2964 | |
| 2965 | /* Use this to determine the HW stepping of the chip so we know |
| 2966 | * what errata to workaround |
| 2967 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2968 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); |
| 2969 | if (scc == 0) |
| 2970 | scc_s = "SCSI"; |
| 2971 | else if (scc == 0x01) |
| 2972 | scc_s = "RAID"; |
| 2973 | else |
Jeff Garzik | c1e4fe7 | 2007-07-09 12:29:31 -0400 | [diff] [blame] | 2974 | scc_s = "?"; |
| 2975 | |
| 2976 | if (IS_GEN_I(hpriv)) |
| 2977 | gen = "I"; |
| 2978 | else if (IS_GEN_II(hpriv)) |
| 2979 | gen = "II"; |
| 2980 | else if (IS_GEN_IIE(hpriv)) |
| 2981 | gen = "IIE"; |
| 2982 | else |
| 2983 | gen = "?"; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2984 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2985 | dev_printk(KERN_INFO, &pdev->dev, |
Jeff Garzik | c1e4fe7 | 2007-07-09 12:29:31 -0400 | [diff] [blame] | 2986 | "Gen-%s %u slots %u ports %s mode IRQ via %s\n", |
| 2987 | gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2988 | scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); |
| 2989 | } |
| 2990 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2991 | /** |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2992 | * mv_pci_init_one - handle a positive probe of a PCI Marvell host |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2993 | * @pdev: PCI device found |
| 2994 | * @ent: PCI device ID entry for the matched host |
| 2995 | * |
| 2996 | * LOCKING: |
| 2997 | * Inherited from caller. |
| 2998 | */ |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2999 | static int mv_pci_init_one(struct pci_dev *pdev, |
| 3000 | const struct pci_device_id *ent) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3001 | { |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 3002 | static int printed_version; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3003 | unsigned int board_idx = (unsigned int)ent->driver_data; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3004 | const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; |
| 3005 | struct ata_host *host; |
| 3006 | struct mv_host_priv *hpriv; |
| 3007 | int n_ports, rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3008 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 3009 | if (!printed_version++) |
| 3010 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3011 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3012 | /* allocate host */ |
| 3013 | n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; |
| 3014 | |
| 3015 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
| 3016 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); |
| 3017 | if (!host || !hpriv) |
| 3018 | return -ENOMEM; |
| 3019 | host->private_data = hpriv; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 3020 | hpriv->n_ports = n_ports; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3021 | |
| 3022 | /* acquire resources */ |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 3023 | rc = pcim_enable_device(pdev); |
| 3024 | if (rc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3025 | return rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3026 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 3027 | rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); |
| 3028 | if (rc == -EBUSY) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 3029 | pcim_pin_device(pdev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 3030 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 3031 | return rc; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3032 | host->iomap = pcim_iomap_table(pdev); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 3033 | hpriv->base = host->iomap[MV_PRIMARY_BAR]; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3034 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 3035 | rc = pci_go_64(pdev); |
| 3036 | if (rc) |
| 3037 | return rc; |
| 3038 | |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 3039 | rc = mv_create_dma_pools(hpriv, &pdev->dev); |
| 3040 | if (rc) |
| 3041 | return rc; |
| 3042 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3043 | /* initialize adapter */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3044 | rc = mv_init_host(host, board_idx); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 3045 | if (rc) |
| 3046 | return rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3047 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 3048 | /* Enable interrupts */ |
Tejun Heo | 6a59dcf | 2007-02-24 15:12:31 +0900 | [diff] [blame] | 3049 | if (msi && pci_enable_msi(pdev)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 3050 | pci_intx(pdev, 1); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3051 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 3052 | mv_dump_pci_cfg(pdev, 0x68); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3053 | mv_print_info(host); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3054 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3055 | pci_set_master(pdev); |
Jeff Garzik | ea8b4db | 2007-07-17 02:21:50 -0400 | [diff] [blame] | 3056 | pci_try_set_mwi(pdev); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3057 | return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 3058 | IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3059 | } |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3060 | #endif |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3061 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 3062 | static int mv_platform_probe(struct platform_device *pdev); |
| 3063 | static int __devexit mv_platform_remove(struct platform_device *pdev); |
| 3064 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3065 | static int __init mv_init(void) |
| 3066 | { |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3067 | int rc = -ENODEV; |
| 3068 | #ifdef CONFIG_PCI |
| 3069 | rc = pci_register_driver(&mv_pci_driver); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 3070 | if (rc < 0) |
| 3071 | return rc; |
| 3072 | #endif |
| 3073 | rc = platform_driver_register(&mv_platform_driver); |
| 3074 | |
| 3075 | #ifdef CONFIG_PCI |
| 3076 | if (rc < 0) |
| 3077 | pci_unregister_driver(&mv_pci_driver); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3078 | #endif |
| 3079 | return rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3080 | } |
| 3081 | |
| 3082 | static void __exit mv_exit(void) |
| 3083 | { |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3084 | #ifdef CONFIG_PCI |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3085 | pci_unregister_driver(&mv_pci_driver); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3086 | #endif |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 3087 | platform_driver_unregister(&mv_platform_driver); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3088 | } |
| 3089 | |
| 3090 | MODULE_AUTHOR("Brett Russ"); |
| 3091 | MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); |
| 3092 | MODULE_LICENSE("GPL"); |
| 3093 | MODULE_DEVICE_TABLE(pci, mv_pci_tbl); |
| 3094 | MODULE_VERSION(DRV_VERSION); |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 3095 | MODULE_ALIAS("platform:" DRV_NAME); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3096 | |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3097 | #ifdef CONFIG_PCI |
Jeff Garzik | ddef9bb | 2006-02-02 16:17:06 -0500 | [diff] [blame] | 3098 | module_param(msi, int, 0444); |
| 3099 | MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3100 | #endif |
Jeff Garzik | ddef9bb | 2006-02-02 16:17:06 -0500 | [diff] [blame] | 3101 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3102 | module_init(mv_init); |
| 3103 | module_exit(mv_exit); |