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Joerg Roedelf6e2e6b2008-06-26 21:27:39 +02001/*
Joerg Roedel5d0d7152010-10-13 11:13:21 +02002 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
Joerg Roedel63ce3ae2015-02-04 16:12:55 +01003 * Author: Joerg Roedel <jroedel@suse.de>
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +02004 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/pci.h>
21#include <linux/acpi.h>
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020022#include <linux/list.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090023#include <linux/slab.h>
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +010024#include <linux/syscore_ops.h>
Joerg Roedela80dc3e2008-09-11 16:51:41 +020025#include <linux/interrupt.h>
26#include <linux/msi.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020027#include <linux/amd-iommu.h>
Joerg Roedel400a28a2011-11-28 15:11:02 +010028#include <linux/export.h>
Alex Williamson066f2e92014-06-12 16:12:37 -060029#include <linux/iommu.h>
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020030#include <asm/pci-direct.h>
FUJITA Tomonori46a7fa22008-07-11 10:23:42 +090031#include <asm/iommu.h>
Joerg Roedel1d9b16d2008-11-27 18:39:15 +010032#include <asm/gart.h>
FUJITA Tomonoriea1b0d32009-11-10 19:46:15 +090033#include <asm/x86_init.h>
Konrad Rzeszutek Wilk22e6daf2010-08-26 13:58:03 -040034#include <asm/iommu_table.h>
Joerg Roedeleb1eb7a2012-07-05 11:58:02 +020035#include <asm/io_apic.h>
Joerg Roedel6b474b82012-06-26 16:46:04 +020036#include <asm/irq_remapping.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020037
38#include "amd_iommu_proto.h"
39#include "amd_iommu_types.h"
Joerg Roedel05152a02012-06-15 16:53:51 +020040#include "irq_remapping.h"
Joerg Roedel403f81d2011-06-14 16:44:25 +020041
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020042/*
43 * definitions for the ACPI scanning code
44 */
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020045#define IVRS_HEADER_LENGTH 48
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020046
47#define ACPI_IVHD_TYPE 0x10
48#define ACPI_IVMD_TYPE_ALL 0x20
49#define ACPI_IVMD_TYPE 0x21
50#define ACPI_IVMD_TYPE_RANGE 0x22
51
52#define IVHD_DEV_ALL 0x01
53#define IVHD_DEV_SELECT 0x02
54#define IVHD_DEV_SELECT_RANGE_START 0x03
55#define IVHD_DEV_RANGE_END 0x04
56#define IVHD_DEV_ALIAS 0x42
57#define IVHD_DEV_ALIAS_RANGE 0x43
58#define IVHD_DEV_EXT_SELECT 0x46
59#define IVHD_DEV_EXT_SELECT_RANGE 0x47
Joerg Roedel6efed632012-06-14 15:52:58 +020060#define IVHD_DEV_SPECIAL 0x48
61
62#define IVHD_SPECIAL_IOAPIC 1
63#define IVHD_SPECIAL_HPET 2
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020064
Joerg Roedel6da73422009-05-04 11:44:38 +020065#define IVHD_FLAG_HT_TUN_EN_MASK 0x01
66#define IVHD_FLAG_PASSPW_EN_MASK 0x02
67#define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
68#define IVHD_FLAG_ISOC_EN_MASK 0x08
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020069
70#define IVMD_FLAG_EXCL_RANGE 0x08
71#define IVMD_FLAG_UNITY_MAP 0x01
72
73#define ACPI_DEVFLAG_INITPASS 0x01
74#define ACPI_DEVFLAG_EXTINT 0x02
75#define ACPI_DEVFLAG_NMI 0x04
76#define ACPI_DEVFLAG_SYSMGT1 0x10
77#define ACPI_DEVFLAG_SYSMGT2 0x20
78#define ACPI_DEVFLAG_LINT0 0x40
79#define ACPI_DEVFLAG_LINT1 0x80
80#define ACPI_DEVFLAG_ATSDIS 0x10000000
81
Joerg Roedelb65233a2008-07-11 17:14:21 +020082/*
83 * ACPI table definitions
84 *
85 * These data structures are laid over the table to parse the important values
86 * out of it.
87 */
88
89/*
90 * structure describing one IOMMU in the ACPI table. Typically followed by one
91 * or more ivhd_entrys.
92 */
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020093struct ivhd_header {
94 u8 type;
95 u8 flags;
96 u16 length;
97 u16 devid;
98 u16 cap_ptr;
99 u64 mmio_phys;
100 u16 pci_seg;
101 u16 info;
Steven L Kinney30861dd2013-06-05 16:11:48 -0500102 u32 efr;
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +0200103} __attribute__((packed));
104
Joerg Roedelb65233a2008-07-11 17:14:21 +0200105/*
106 * A device entry describing which devices a specific IOMMU translates and
107 * which requestor ids they use.
108 */
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +0200109struct ivhd_entry {
110 u8 type;
111 u16 devid;
112 u8 flags;
113 u32 ext;
114} __attribute__((packed));
115
Joerg Roedelb65233a2008-07-11 17:14:21 +0200116/*
117 * An AMD IOMMU memory definition structure. It defines things like exclusion
118 * ranges for devices and regions that should be unity mapped.
119 */
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +0200120struct ivmd_header {
121 u8 type;
122 u8 flags;
123 u16 length;
124 u16 devid;
125 u16 aux;
126 u64 resv;
127 u64 range_start;
128 u64 range_length;
129} __attribute__((packed));
130
Joerg Roedelfefda112009-05-20 12:21:42 +0200131bool amd_iommu_dump;
Joerg Roedel05152a02012-06-15 16:53:51 +0200132bool amd_iommu_irq_remap __read_mostly;
Joerg Roedelfefda112009-05-20 12:21:42 +0200133
Joerg Roedel02f3b3f2012-06-11 17:45:25 +0200134static bool amd_iommu_detected;
Joerg Roedela5235722010-05-11 17:12:33 +0200135static bool __initdata amd_iommu_disabled;
Joerg Roedelc1cbebe2008-07-03 19:35:10 +0200136
Joerg Roedelb65233a2008-07-11 17:14:21 +0200137u16 amd_iommu_last_bdf; /* largest PCI device id we have
138 to handle */
Joerg Roedel2e228472008-07-11 17:14:31 +0200139LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
Joerg Roedelb65233a2008-07-11 17:14:21 +0200140 we find in ACPI */
Viresh Kumar621a5f72015-09-26 15:04:07 -0700141bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
Joerg Roedel928abd22008-06-26 21:27:40 +0200142
Joerg Roedel2e228472008-07-11 17:14:31 +0200143LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
Joerg Roedelb65233a2008-07-11 17:14:21 +0200144 system */
145
Joerg Roedelbb527772009-11-20 14:31:51 +0100146/* Array to assign indices to IOMMUs*/
147struct amd_iommu *amd_iommus[MAX_IOMMUS];
148int amd_iommus_present;
149
Joerg Roedel318afd42009-11-23 18:32:38 +0100150/* IOMMUs have a non-present cache? */
151bool amd_iommu_np_cache __read_mostly;
Joerg Roedel60f723b2011-04-05 12:50:24 +0200152bool amd_iommu_iotlb_sup __read_mostly = true;
Joerg Roedel318afd42009-11-23 18:32:38 +0100153
Suravee Suthikulpanita919a012014-03-05 18:54:18 -0600154u32 amd_iommu_max_pasid __read_mostly = ~0;
Joerg Roedel62f71ab2011-11-10 14:41:57 +0100155
Joerg Roedel400a28a2011-11-28 15:11:02 +0100156bool amd_iommu_v2_present __read_mostly;
Joerg Roedel4160cd92015-08-13 11:31:48 +0200157static bool amd_iommu_pc_present __read_mostly;
Joerg Roedel400a28a2011-11-28 15:11:02 +0100158
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100159bool amd_iommu_force_isolation __read_mostly;
160
Joerg Roedelb65233a2008-07-11 17:14:21 +0200161/*
Joerg Roedelaeb26f52009-11-20 16:44:01 +0100162 * List of protection domains - used during resume
163 */
164LIST_HEAD(amd_iommu_pd_list);
165spinlock_t amd_iommu_pd_lock;
166
167/*
Joerg Roedelb65233a2008-07-11 17:14:21 +0200168 * Pointer to the device table which is shared by all AMD IOMMUs
169 * it is indexed by the PCI device id or the HT unit id and contains
170 * information about the domain the device belongs to as well as the
171 * page table root pointer.
172 */
Joerg Roedel928abd22008-06-26 21:27:40 +0200173struct dev_table_entry *amd_iommu_dev_table;
Joerg Roedelb65233a2008-07-11 17:14:21 +0200174
175/*
176 * The alias table is a driver specific data structure which contains the
177 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
178 * More than one device can share the same requestor id.
179 */
Joerg Roedel928abd22008-06-26 21:27:40 +0200180u16 *amd_iommu_alias_table;
Joerg Roedelb65233a2008-07-11 17:14:21 +0200181
182/*
183 * The rlookup table is used to find the IOMMU which is responsible
184 * for a specific device. It is also indexed by the PCI device id.
185 */
Joerg Roedel928abd22008-06-26 21:27:40 +0200186struct amd_iommu **amd_iommu_rlookup_table;
Joerg Roedelb65233a2008-07-11 17:14:21 +0200187
188/*
Joerg Roedel0ea2c422012-06-15 18:05:20 +0200189 * This table is used to find the irq remapping table for a given device id
190 * quickly.
191 */
192struct irq_remap_table **irq_lookup_table;
193
194/*
Frank Arnolddf805ab2012-08-27 19:21:04 +0200195 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
Joerg Roedelb65233a2008-07-11 17:14:21 +0200196 * to know which ones are already in use.
197 */
Joerg Roedel928abd22008-06-26 21:27:40 +0200198unsigned long *amd_iommu_pd_alloc_bitmap;
199
Joerg Roedelb65233a2008-07-11 17:14:21 +0200200static u32 dev_table_size; /* size of the device table */
201static u32 alias_table_size; /* size of the alias table */
202static u32 rlookup_table_size; /* size if the rlookup table */
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200203
Joerg Roedel2c0ae172012-06-12 15:59:30 +0200204enum iommu_init_state {
205 IOMMU_START_STATE,
206 IOMMU_IVRS_DETECTED,
207 IOMMU_ACPI_FINISHED,
208 IOMMU_ENABLED,
209 IOMMU_PCI_INIT,
210 IOMMU_INTERRUPTS_EN,
211 IOMMU_DMA_OPS,
212 IOMMU_INITIALIZED,
213 IOMMU_NOT_FOUND,
214 IOMMU_INIT_ERROR,
215};
216
Joerg Roedel235dacb2013-04-09 17:53:14 +0200217/* Early ioapic and hpet maps from kernel command line */
218#define EARLY_MAP_SIZE 4
219static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
220static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
221static int __initdata early_ioapic_map_size;
222static int __initdata early_hpet_map_size;
Joerg Roedeldfbb6d42013-04-09 19:06:18 +0200223static bool __initdata cmdline_maps;
Joerg Roedel235dacb2013-04-09 17:53:14 +0200224
Joerg Roedel2c0ae172012-06-12 15:59:30 +0200225static enum iommu_init_state init_state = IOMMU_START_STATE;
226
Gerard Snitselaarae295142012-03-16 11:38:22 -0700227static int amd_iommu_enable_interrupts(void);
Joerg Roedel2c0ae172012-06-12 15:59:30 +0200228static int __init iommu_go_to_state(enum iommu_init_state state);
Joerg Roedelaafd8ba2015-05-28 18:41:39 +0200229static void init_device_table_dma(void);
Joerg Roedel3d9761e2012-03-15 16:39:21 +0100230
Suravee Suthikulpanit38e45d02016-02-23 13:03:30 +0100231static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
232 u8 bank, u8 cntr, u8 fxn,
233 u64 *value, bool is_write);
234
Joerg Roedel208ec8c2008-07-11 17:14:24 +0200235static inline void update_last_devid(u16 devid)
236{
237 if (devid > amd_iommu_last_bdf)
238 amd_iommu_last_bdf = devid;
239}
240
Joerg Roedelc5714842008-07-11 17:14:25 +0200241static inline unsigned long tbl_size(int entry_size)
242{
243 unsigned shift = PAGE_SHIFT +
Neil Turton421f9092009-05-14 14:00:35 +0100244 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
Joerg Roedelc5714842008-07-11 17:14:25 +0200245
246 return 1UL << shift;
247}
248
Matthew Garrett5bcd7572010-10-04 14:59:31 -0400249/* Access to l1 and l2 indexed register spaces */
250
251static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
252{
253 u32 val;
254
255 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
256 pci_read_config_dword(iommu->dev, 0xfc, &val);
257 return val;
258}
259
260static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
261{
262 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
263 pci_write_config_dword(iommu->dev, 0xfc, val);
264 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
265}
266
267static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
268{
269 u32 val;
270
271 pci_write_config_dword(iommu->dev, 0xf0, address);
272 pci_read_config_dword(iommu->dev, 0xf4, &val);
273 return val;
274}
275
276static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
277{
278 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
279 pci_write_config_dword(iommu->dev, 0xf4, val);
280}
281
Joerg Roedelb65233a2008-07-11 17:14:21 +0200282/****************************************************************************
283 *
284 * AMD IOMMU MMIO register space handling functions
285 *
286 * These functions are used to program the IOMMU device registers in
287 * MMIO space required for that driver.
288 *
289 ****************************************************************************/
290
291/*
292 * This function set the exclusion range in the IOMMU. DMA accesses to the
293 * exclusion range are passed through untranslated
294 */
Joerg Roedel05f92db2009-05-12 09:52:46 +0200295static void iommu_set_exclusion_range(struct amd_iommu *iommu)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200296{
297 u64 start = iommu->exclusion_start & PAGE_MASK;
298 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
299 u64 entry;
300
301 if (!iommu->exclusion_start)
302 return;
303
304 entry = start | MMIO_EXCL_ENABLE_MASK;
305 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
306 &entry, sizeof(entry));
307
308 entry = limit;
309 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
310 &entry, sizeof(entry));
311}
312
Joerg Roedelb65233a2008-07-11 17:14:21 +0200313/* Programs the physical address of the device table into the IOMMU hardware */
Jan Beulich6b7f0002012-03-08 08:58:13 +0000314static void iommu_set_device_table(struct amd_iommu *iommu)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200315{
Andreas Herrmannf6098912008-10-16 16:27:36 +0200316 u64 entry;
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200317
318 BUG_ON(iommu->mmio_base == NULL);
319
320 entry = virt_to_phys(amd_iommu_dev_table);
321 entry |= (dev_table_size >> 12) - 1;
322 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
323 &entry, sizeof(entry));
324}
325
Joerg Roedelb65233a2008-07-11 17:14:21 +0200326/* Generic functions to enable/disable certain features of the IOMMU. */
Joerg Roedel05f92db2009-05-12 09:52:46 +0200327static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200328{
329 u32 ctrl;
330
331 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
332 ctrl |= (1 << bit);
333 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
334}
335
Joerg Roedelca0207112009-10-28 18:02:26 +0100336static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200337{
338 u32 ctrl;
339
Joerg Roedel199d0d52008-09-17 16:45:59 +0200340 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200341 ctrl &= ~(1 << bit);
342 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
343}
344
Joerg Roedel1456e9d2011-12-22 14:51:53 +0100345static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
346{
347 u32 ctrl;
348
349 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
350 ctrl &= ~CTRL_INV_TO_MASK;
351 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
352 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
353}
354
Joerg Roedelb65233a2008-07-11 17:14:21 +0200355/* Function to enable the hardware */
Joerg Roedel05f92db2009-05-12 09:52:46 +0200356static void iommu_enable(struct amd_iommu *iommu)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200357{
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200358 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200359}
360
Joerg Roedel92ac4322009-05-19 19:06:27 +0200361static void iommu_disable(struct amd_iommu *iommu)
Joerg Roedel126c52b2008-09-09 16:47:35 +0200362{
Chris Wrighta8c485b2009-06-15 15:53:45 +0200363 /* Disable command buffer */
364 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
365
366 /* Disable event logging and event interrupts */
367 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
368 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
369
370 /* Disable IOMMU hardware itself */
Joerg Roedel92ac4322009-05-19 19:06:27 +0200371 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
Joerg Roedel126c52b2008-09-09 16:47:35 +0200372}
373
Joerg Roedelb65233a2008-07-11 17:14:21 +0200374/*
375 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
376 * the system has one.
377 */
Steven L Kinney30861dd2013-06-05 16:11:48 -0500378static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
Joerg Roedel6c567472008-06-26 21:27:43 +0200379{
Steven L Kinney30861dd2013-06-05 16:11:48 -0500380 if (!request_mem_region(address, end, "amd_iommu")) {
381 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
382 address, end);
Joerg Roedele82752d2010-05-28 14:26:48 +0200383 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
Joerg Roedel6c567472008-06-26 21:27:43 +0200384 return NULL;
Joerg Roedele82752d2010-05-28 14:26:48 +0200385 }
Joerg Roedel6c567472008-06-26 21:27:43 +0200386
Steven L Kinney30861dd2013-06-05 16:11:48 -0500387 return (u8 __iomem *)ioremap_nocache(address, end);
Joerg Roedel6c567472008-06-26 21:27:43 +0200388}
389
390static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
391{
392 if (iommu->mmio_base)
393 iounmap(iommu->mmio_base);
Steven L Kinney30861dd2013-06-05 16:11:48 -0500394 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
Joerg Roedel6c567472008-06-26 21:27:43 +0200395}
396
Joerg Roedelb65233a2008-07-11 17:14:21 +0200397/****************************************************************************
398 *
399 * The functions below belong to the first pass of AMD IOMMU ACPI table
400 * parsing. In this pass we try to find out the highest device id this
401 * code has to handle. Upon this information the size of the shared data
402 * structures is determined later.
403 *
404 ****************************************************************************/
405
406/*
Joerg Roedelb514e552008-09-17 17:14:27 +0200407 * This function calculates the length of a given IVHD entry
408 */
409static inline int ivhd_entry_length(u8 *ivhd)
410{
411 return 0x04 << (*ivhd >> 6);
412}
413
414/*
Joerg Roedelb65233a2008-07-11 17:14:21 +0200415 * After reading the highest device id from the IOMMU PCI capability header
416 * this function looks if there is a higher device id defined in the ACPI table
417 */
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200418static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
419{
420 u8 *p = (void *)h, *end = (void *)h;
421 struct ivhd_entry *dev;
422
423 p += sizeof(*h);
424 end += h->length;
425
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200426 while (p < end) {
427 dev = (struct ivhd_entry *)p;
428 switch (dev->type) {
Joerg Roedeld1259412015-10-20 17:33:43 +0200429 case IVHD_DEV_ALL:
430 /* Use maximum BDF value for DEV_ALL */
431 update_last_devid(0xffff);
432 break;
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200433 case IVHD_DEV_SELECT:
434 case IVHD_DEV_RANGE_END:
435 case IVHD_DEV_ALIAS:
436 case IVHD_DEV_EXT_SELECT:
Joerg Roedelb65233a2008-07-11 17:14:21 +0200437 /* all the above subfield types refer to device ids */
Joerg Roedel208ec8c2008-07-11 17:14:24 +0200438 update_last_devid(dev->devid);
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200439 break;
440 default:
441 break;
442 }
Joerg Roedelb514e552008-09-17 17:14:27 +0200443 p += ivhd_entry_length(p);
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200444 }
445
446 WARN_ON(p != end);
447
448 return 0;
449}
450
Joerg Roedelb65233a2008-07-11 17:14:21 +0200451/*
452 * Iterate over all IVHD entries in the ACPI table and find the highest device
453 * id which we need to handle. This is the first of three functions which parse
454 * the ACPI table. So we check the checksum here.
455 */
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200456static int __init find_last_devid_acpi(struct acpi_table_header *table)
457{
458 int i;
459 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
460 struct ivhd_header *h;
461
462 /*
463 * Validate checksum here so we don't need to do it when
464 * we actually parse the table
465 */
466 for (i = 0; i < table->length; ++i)
467 checksum += p[i];
Joerg Roedel02f3b3f2012-06-11 17:45:25 +0200468 if (checksum != 0)
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200469 /* ACPI table corrupt */
Joerg Roedel02f3b3f2012-06-11 17:45:25 +0200470 return -ENODEV;
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200471
472 p += IVRS_HEADER_LENGTH;
473
474 end += table->length;
475 while (p < end) {
476 h = (struct ivhd_header *)p;
477 switch (h->type) {
478 case ACPI_IVHD_TYPE:
479 find_last_devid_from_ivhd(h);
480 break;
481 default:
482 break;
483 }
484 p += h->length;
485 }
486 WARN_ON(p != end);
487
488 return 0;
489}
490
Joerg Roedelb65233a2008-07-11 17:14:21 +0200491/****************************************************************************
492 *
Frank Arnolddf805ab2012-08-27 19:21:04 +0200493 * The following functions belong to the code path which parses the ACPI table
Joerg Roedelb65233a2008-07-11 17:14:21 +0200494 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
495 * data structures, initialize the device/alias/rlookup table and also
496 * basically initialize the hardware.
497 *
498 ****************************************************************************/
499
500/*
501 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
502 * write commands to that buffer later and the IOMMU will execute them
503 * asynchronously
504 */
Joerg Roedelf2c2db52015-10-20 17:33:42 +0200505static int __init alloc_command_buffer(struct amd_iommu *iommu)
Joerg Roedelb36ca912008-06-26 21:27:45 +0200506{
Joerg Roedelf2c2db52015-10-20 17:33:42 +0200507 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
508 get_order(CMD_BUFFER_SIZE));
Joerg Roedelb36ca912008-06-26 21:27:45 +0200509
Joerg Roedelf2c2db52015-10-20 17:33:42 +0200510 return iommu->cmd_buf ? 0 : -ENOMEM;
Joerg Roedel58492e12009-05-04 18:41:16 +0200511}
512
513/*
Joerg Roedel93f1cc672009-09-03 14:50:20 +0200514 * This function resets the command buffer if the IOMMU stopped fetching
515 * commands from it.
516 */
517void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
518{
519 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
520
521 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
522 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
523
524 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
525}
526
527/*
Joerg Roedel58492e12009-05-04 18:41:16 +0200528 * This function writes the command buffer address to the hardware and
529 * enables it.
530 */
531static void iommu_enable_command_buffer(struct amd_iommu *iommu)
532{
533 u64 entry;
534
535 BUG_ON(iommu->cmd_buf == NULL);
536
537 entry = (u64)virt_to_phys(iommu->cmd_buf);
Joerg Roedelb36ca912008-06-26 21:27:45 +0200538 entry |= MMIO_CMD_SIZE_512;
Joerg Roedel58492e12009-05-04 18:41:16 +0200539
Joerg Roedelb36ca912008-06-26 21:27:45 +0200540 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
Joerg Roedel58492e12009-05-04 18:41:16 +0200541 &entry, sizeof(entry));
Joerg Roedelb36ca912008-06-26 21:27:45 +0200542
Joerg Roedel93f1cc672009-09-03 14:50:20 +0200543 amd_iommu_reset_cmd_buffer(iommu);
Joerg Roedelb36ca912008-06-26 21:27:45 +0200544}
545
546static void __init free_command_buffer(struct amd_iommu *iommu)
547{
Joerg Roedeldeba4bc2015-10-20 17:33:41 +0200548 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
Joerg Roedelb36ca912008-06-26 21:27:45 +0200549}
550
Joerg Roedel335503e2008-09-05 14:29:07 +0200551/* allocates the memory where the IOMMU will log its events to */
Joerg Roedelf2c2db52015-10-20 17:33:42 +0200552static int __init alloc_event_buffer(struct amd_iommu *iommu)
Joerg Roedel335503e2008-09-05 14:29:07 +0200553{
Joerg Roedelf2c2db52015-10-20 17:33:42 +0200554 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
555 get_order(EVT_BUFFER_SIZE));
Joerg Roedel335503e2008-09-05 14:29:07 +0200556
Joerg Roedelf2c2db52015-10-20 17:33:42 +0200557 return iommu->evt_buf ? 0 : -ENOMEM;
Joerg Roedel58492e12009-05-04 18:41:16 +0200558}
559
560static void iommu_enable_event_buffer(struct amd_iommu *iommu)
561{
562 u64 entry;
563
564 BUG_ON(iommu->evt_buf == NULL);
565
Joerg Roedel335503e2008-09-05 14:29:07 +0200566 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
Joerg Roedel58492e12009-05-04 18:41:16 +0200567
Joerg Roedel335503e2008-09-05 14:29:07 +0200568 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
569 &entry, sizeof(entry));
570
Joerg Roedel090672072009-06-15 16:06:48 +0200571 /* set head and tail to zero manually */
572 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
573 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
574
Joerg Roedel58492e12009-05-04 18:41:16 +0200575 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
Joerg Roedel335503e2008-09-05 14:29:07 +0200576}
577
578static void __init free_event_buffer(struct amd_iommu *iommu)
579{
580 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
581}
582
Joerg Roedel1a29ac02011-11-10 15:41:40 +0100583/* allocates the memory where the IOMMU will log its events to */
Joerg Roedelf2c2db52015-10-20 17:33:42 +0200584static int __init alloc_ppr_log(struct amd_iommu *iommu)
Joerg Roedel1a29ac02011-11-10 15:41:40 +0100585{
Joerg Roedelf2c2db52015-10-20 17:33:42 +0200586 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
587 get_order(PPR_LOG_SIZE));
Joerg Roedel1a29ac02011-11-10 15:41:40 +0100588
Joerg Roedelf2c2db52015-10-20 17:33:42 +0200589 return iommu->ppr_log ? 0 : -ENOMEM;
Joerg Roedel1a29ac02011-11-10 15:41:40 +0100590}
591
592static void iommu_enable_ppr_log(struct amd_iommu *iommu)
593{
594 u64 entry;
595
596 if (iommu->ppr_log == NULL)
597 return;
598
599 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
600
601 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
602 &entry, sizeof(entry));
603
604 /* set head and tail to zero manually */
605 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
606 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
607
608 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
609 iommu_feature_enable(iommu, CONTROL_PPR_EN);
610}
611
612static void __init free_ppr_log(struct amd_iommu *iommu)
613{
614 if (iommu->ppr_log == NULL)
615 return;
616
617 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
618}
619
Joerg Roedelcbc33a92011-11-25 11:41:31 +0100620static void iommu_enable_gt(struct amd_iommu *iommu)
621{
622 if (!iommu_feature(iommu, FEATURE_GT))
623 return;
624
625 iommu_feature_enable(iommu, CONTROL_GT_EN);
626}
627
Joerg Roedelb65233a2008-07-11 17:14:21 +0200628/* sets a specific bit in the device table entry. */
Joerg Roedel3566b772008-06-26 21:27:46 +0200629static void set_dev_entry_bit(u16 devid, u8 bit)
630{
Joerg Roedelee6c2862011-11-09 12:06:03 +0100631 int i = (bit >> 6) & 0x03;
632 int _bit = bit & 0x3f;
Joerg Roedel3566b772008-06-26 21:27:46 +0200633
Joerg Roedelee6c2862011-11-09 12:06:03 +0100634 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
Joerg Roedel3566b772008-06-26 21:27:46 +0200635}
636
Joerg Roedelc5cca142009-10-09 18:31:20 +0200637static int get_dev_entry_bit(u16 devid, u8 bit)
638{
Joerg Roedelee6c2862011-11-09 12:06:03 +0100639 int i = (bit >> 6) & 0x03;
640 int _bit = bit & 0x3f;
Joerg Roedelc5cca142009-10-09 18:31:20 +0200641
Joerg Roedelee6c2862011-11-09 12:06:03 +0100642 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
Joerg Roedelc5cca142009-10-09 18:31:20 +0200643}
644
645
646void amd_iommu_apply_erratum_63(u16 devid)
647{
648 int sysmgt;
649
650 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
651 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
652
653 if (sysmgt == 0x01)
654 set_dev_entry_bit(devid, DEV_ENTRY_IW);
655}
656
Joerg Roedel5ff47892008-07-14 20:11:18 +0200657/* Writes the specific IOMMU for a device into the rlookup table */
658static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
659{
660 amd_iommu_rlookup_table[devid] = iommu;
661}
662
Joerg Roedelb65233a2008-07-11 17:14:21 +0200663/*
664 * This function takes the device specific flags read from the ACPI
665 * table and sets up the device table entry with that information
666 */
Joerg Roedel5ff47892008-07-14 20:11:18 +0200667static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
668 u16 devid, u32 flags, u32 ext_flags)
Joerg Roedel3566b772008-06-26 21:27:46 +0200669{
670 if (flags & ACPI_DEVFLAG_INITPASS)
671 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
672 if (flags & ACPI_DEVFLAG_EXTINT)
673 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
674 if (flags & ACPI_DEVFLAG_NMI)
675 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
676 if (flags & ACPI_DEVFLAG_SYSMGT1)
677 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
678 if (flags & ACPI_DEVFLAG_SYSMGT2)
679 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
680 if (flags & ACPI_DEVFLAG_LINT0)
681 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
682 if (flags & ACPI_DEVFLAG_LINT1)
683 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
Joerg Roedel3566b772008-06-26 21:27:46 +0200684
Joerg Roedelc5cca142009-10-09 18:31:20 +0200685 amd_iommu_apply_erratum_63(devid);
686
Joerg Roedel5ff47892008-07-14 20:11:18 +0200687 set_iommu_for_device(iommu, devid);
Joerg Roedel3566b772008-06-26 21:27:46 +0200688}
689
Joerg Roedelc50e3242014-09-09 15:59:37 +0200690static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
Joerg Roedel6efed632012-06-14 15:52:58 +0200691{
692 struct devid_map *entry;
693 struct list_head *list;
694
Joerg Roedel31cff672013-04-09 16:53:58 +0200695 if (type == IVHD_SPECIAL_IOAPIC)
696 list = &ioapic_map;
697 else if (type == IVHD_SPECIAL_HPET)
698 list = &hpet_map;
699 else
Joerg Roedel6efed632012-06-14 15:52:58 +0200700 return -EINVAL;
701
Joerg Roedel31cff672013-04-09 16:53:58 +0200702 list_for_each_entry(entry, list, list) {
703 if (!(entry->id == id && entry->cmd_line))
704 continue;
705
706 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
707 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
708
Joerg Roedelc50e3242014-09-09 15:59:37 +0200709 *devid = entry->devid;
710
Joerg Roedel31cff672013-04-09 16:53:58 +0200711 return 0;
712 }
713
Joerg Roedel6efed632012-06-14 15:52:58 +0200714 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
715 if (!entry)
716 return -ENOMEM;
717
Joerg Roedel31cff672013-04-09 16:53:58 +0200718 entry->id = id;
Joerg Roedelc50e3242014-09-09 15:59:37 +0200719 entry->devid = *devid;
Joerg Roedel31cff672013-04-09 16:53:58 +0200720 entry->cmd_line = cmd_line;
Joerg Roedel6efed632012-06-14 15:52:58 +0200721
722 list_add_tail(&entry->list, list);
723
724 return 0;
725}
726
Joerg Roedel235dacb2013-04-09 17:53:14 +0200727static int __init add_early_maps(void)
728{
729 int i, ret;
730
731 for (i = 0; i < early_ioapic_map_size; ++i) {
732 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
733 early_ioapic_map[i].id,
Joerg Roedelc50e3242014-09-09 15:59:37 +0200734 &early_ioapic_map[i].devid,
Joerg Roedel235dacb2013-04-09 17:53:14 +0200735 early_ioapic_map[i].cmd_line);
736 if (ret)
737 return ret;
738 }
739
740 for (i = 0; i < early_hpet_map_size; ++i) {
741 ret = add_special_device(IVHD_SPECIAL_HPET,
742 early_hpet_map[i].id,
Joerg Roedelc50e3242014-09-09 15:59:37 +0200743 &early_hpet_map[i].devid,
Joerg Roedel235dacb2013-04-09 17:53:14 +0200744 early_hpet_map[i].cmd_line);
745 if (ret)
746 return ret;
747 }
748
749 return 0;
750}
751
Joerg Roedelb65233a2008-07-11 17:14:21 +0200752/*
Frank Arnolddf805ab2012-08-27 19:21:04 +0200753 * Reads the device exclusion range from ACPI and initializes the IOMMU with
Joerg Roedelb65233a2008-07-11 17:14:21 +0200754 * it
755 */
Joerg Roedel3566b772008-06-26 21:27:46 +0200756static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
757{
758 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
759
760 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
761 return;
762
763 if (iommu) {
Joerg Roedelb65233a2008-07-11 17:14:21 +0200764 /*
765 * We only can configure exclusion ranges per IOMMU, not
766 * per device. But we can enable the exclusion range per
767 * device. This is done here
768 */
Su Friendy2c16c9f2014-05-07 13:54:52 +0800769 set_dev_entry_bit(devid, DEV_ENTRY_EX);
Joerg Roedel3566b772008-06-26 21:27:46 +0200770 iommu->exclusion_start = m->range_start;
771 iommu->exclusion_length = m->range_length;
772 }
773}
774
Joerg Roedelb65233a2008-07-11 17:14:21 +0200775/*
Joerg Roedelb65233a2008-07-11 17:14:21 +0200776 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
777 * initializes the hardware and our data structures with it.
778 */
Joerg Roedel6efed632012-06-14 15:52:58 +0200779static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200780 struct ivhd_header *h)
781{
782 u8 *p = (u8 *)h;
783 u8 *end = p, flags = 0;
Joerg Roedel0de66d52011-06-06 16:04:02 +0200784 u16 devid = 0, devid_start = 0, devid_to = 0;
785 u32 dev_i, ext_flags = 0;
Joerg Roedel58a3bee2008-07-11 17:14:30 +0200786 bool alias = false;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200787 struct ivhd_entry *e;
Joerg Roedel235dacb2013-04-09 17:53:14 +0200788 int ret;
789
790
791 ret = add_early_maps();
792 if (ret)
793 return ret;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200794
795 /*
Joerg Roedele9bf5192010-09-20 14:33:07 +0200796 * First save the recommended feature enable bits from ACPI
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200797 */
Joerg Roedele9bf5192010-09-20 14:33:07 +0200798 iommu->acpi_flags = h->flags;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200799
800 /*
801 * Done. Now parse the device entries
802 */
803 p += sizeof(struct ivhd_header);
804 end += h->length;
805
Joerg Roedel42a698f2009-05-20 15:41:28 +0200806
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200807 while (p < end) {
808 e = (struct ivhd_entry *)p;
809 switch (e->type) {
810 case IVHD_DEV_ALL:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200811
Joerg Roedel226e8892015-10-20 17:33:44 +0200812 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
Joerg Roedel42a698f2009-05-20 15:41:28 +0200813
Joerg Roedel226e8892015-10-20 17:33:44 +0200814 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
815 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200816 break;
817 case IVHD_DEV_SELECT:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200818
819 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
820 "flags: %02x\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700821 PCI_BUS_NUM(e->devid),
Joerg Roedel42a698f2009-05-20 15:41:28 +0200822 PCI_SLOT(e->devid),
823 PCI_FUNC(e->devid),
824 e->flags);
825
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200826 devid = e->devid;
Joerg Roedel5ff47892008-07-14 20:11:18 +0200827 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200828 break;
829 case IVHD_DEV_SELECT_RANGE_START:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200830
831 DUMP_printk(" DEV_SELECT_RANGE_START\t "
832 "devid: %02x:%02x.%x flags: %02x\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700833 PCI_BUS_NUM(e->devid),
Joerg Roedel42a698f2009-05-20 15:41:28 +0200834 PCI_SLOT(e->devid),
835 PCI_FUNC(e->devid),
836 e->flags);
837
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200838 devid_start = e->devid;
839 flags = e->flags;
840 ext_flags = 0;
Joerg Roedel58a3bee2008-07-11 17:14:30 +0200841 alias = false;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200842 break;
843 case IVHD_DEV_ALIAS:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200844
845 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
846 "flags: %02x devid_to: %02x:%02x.%x\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700847 PCI_BUS_NUM(e->devid),
Joerg Roedel42a698f2009-05-20 15:41:28 +0200848 PCI_SLOT(e->devid),
849 PCI_FUNC(e->devid),
850 e->flags,
Shuah Khanc5081cd2013-02-27 17:07:19 -0700851 PCI_BUS_NUM(e->ext >> 8),
Joerg Roedel42a698f2009-05-20 15:41:28 +0200852 PCI_SLOT(e->ext >> 8),
853 PCI_FUNC(e->ext >> 8));
854
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200855 devid = e->devid;
856 devid_to = e->ext >> 8;
Joerg Roedel7a6a3a02009-07-02 12:23:23 +0200857 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
Neil Turton7455aab2009-05-14 14:08:11 +0100858 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200859 amd_iommu_alias_table[devid] = devid_to;
860 break;
861 case IVHD_DEV_ALIAS_RANGE:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200862
863 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
864 "devid: %02x:%02x.%x flags: %02x "
865 "devid_to: %02x:%02x.%x\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700866 PCI_BUS_NUM(e->devid),
Joerg Roedel42a698f2009-05-20 15:41:28 +0200867 PCI_SLOT(e->devid),
868 PCI_FUNC(e->devid),
869 e->flags,
Shuah Khanc5081cd2013-02-27 17:07:19 -0700870 PCI_BUS_NUM(e->ext >> 8),
Joerg Roedel42a698f2009-05-20 15:41:28 +0200871 PCI_SLOT(e->ext >> 8),
872 PCI_FUNC(e->ext >> 8));
873
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200874 devid_start = e->devid;
875 flags = e->flags;
876 devid_to = e->ext >> 8;
877 ext_flags = 0;
Joerg Roedel58a3bee2008-07-11 17:14:30 +0200878 alias = true;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200879 break;
880 case IVHD_DEV_EXT_SELECT:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200881
882 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
883 "flags: %02x ext: %08x\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700884 PCI_BUS_NUM(e->devid),
Joerg Roedel42a698f2009-05-20 15:41:28 +0200885 PCI_SLOT(e->devid),
886 PCI_FUNC(e->devid),
887 e->flags, e->ext);
888
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200889 devid = e->devid;
Joerg Roedel5ff47892008-07-14 20:11:18 +0200890 set_dev_entry_from_acpi(iommu, devid, e->flags,
891 e->ext);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200892 break;
893 case IVHD_DEV_EXT_SELECT_RANGE:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200894
895 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
896 "%02x:%02x.%x flags: %02x ext: %08x\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700897 PCI_BUS_NUM(e->devid),
Joerg Roedel42a698f2009-05-20 15:41:28 +0200898 PCI_SLOT(e->devid),
899 PCI_FUNC(e->devid),
900 e->flags, e->ext);
901
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200902 devid_start = e->devid;
903 flags = e->flags;
904 ext_flags = e->ext;
Joerg Roedel58a3bee2008-07-11 17:14:30 +0200905 alias = false;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200906 break;
907 case IVHD_DEV_RANGE_END:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200908
909 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700910 PCI_BUS_NUM(e->devid),
Joerg Roedel42a698f2009-05-20 15:41:28 +0200911 PCI_SLOT(e->devid),
912 PCI_FUNC(e->devid));
913
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200914 devid = e->devid;
915 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
Joerg Roedel7a6a3a02009-07-02 12:23:23 +0200916 if (alias) {
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200917 amd_iommu_alias_table[dev_i] = devid_to;
Joerg Roedel7a6a3a02009-07-02 12:23:23 +0200918 set_dev_entry_from_acpi(iommu,
919 devid_to, flags, ext_flags);
920 }
921 set_dev_entry_from_acpi(iommu, dev_i,
922 flags, ext_flags);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200923 }
924 break;
Joerg Roedel6efed632012-06-14 15:52:58 +0200925 case IVHD_DEV_SPECIAL: {
926 u8 handle, type;
927 const char *var;
928 u16 devid;
929 int ret;
930
931 handle = e->ext & 0xff;
932 devid = (e->ext >> 8) & 0xffff;
933 type = (e->ext >> 24) & 0xff;
934
935 if (type == IVHD_SPECIAL_IOAPIC)
936 var = "IOAPIC";
937 else if (type == IVHD_SPECIAL_HPET)
938 var = "HPET";
939 else
940 var = "UNKNOWN";
941
942 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
943 var, (int)handle,
Shuah Khanc5081cd2013-02-27 17:07:19 -0700944 PCI_BUS_NUM(devid),
Joerg Roedel6efed632012-06-14 15:52:58 +0200945 PCI_SLOT(devid),
946 PCI_FUNC(devid));
947
Joerg Roedelc50e3242014-09-09 15:59:37 +0200948 ret = add_special_device(type, handle, &devid, false);
Joerg Roedel6efed632012-06-14 15:52:58 +0200949 if (ret)
950 return ret;
Joerg Roedelc50e3242014-09-09 15:59:37 +0200951
952 /*
953 * add_special_device might update the devid in case a
954 * command-line override is present. So call
955 * set_dev_entry_from_acpi after add_special_device.
956 */
957 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
958
Joerg Roedel6efed632012-06-14 15:52:58 +0200959 break;
960 }
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200961 default:
962 break;
963 }
964
Joerg Roedelb514e552008-09-17 17:14:27 +0200965 p += ivhd_entry_length(p);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200966 }
Joerg Roedel6efed632012-06-14 15:52:58 +0200967
968 return 0;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200969}
970
Joerg Roedele47d4022008-06-26 21:27:48 +0200971static void __init free_iommu_one(struct amd_iommu *iommu)
972{
973 free_command_buffer(iommu);
Joerg Roedel335503e2008-09-05 14:29:07 +0200974 free_event_buffer(iommu);
Joerg Roedel1a29ac02011-11-10 15:41:40 +0100975 free_ppr_log(iommu);
Joerg Roedele47d4022008-06-26 21:27:48 +0200976 iommu_unmap_mmio_space(iommu);
977}
978
979static void __init free_iommu_all(void)
980{
981 struct amd_iommu *iommu, *next;
982
Joerg Roedel3bd22172009-05-04 15:06:20 +0200983 for_each_iommu_safe(iommu, next) {
Joerg Roedele47d4022008-06-26 21:27:48 +0200984 list_del(&iommu->list);
985 free_iommu_one(iommu);
986 kfree(iommu);
987 }
988}
989
Joerg Roedelb65233a2008-07-11 17:14:21 +0200990/*
Suravee Suthikulpanit318fe782013-01-24 13:17:53 -0600991 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
992 * Workaround:
993 * BIOS should disable L2B micellaneous clock gating by setting
994 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
995 */
Nikola Pajkovskye2f1a3b2013-02-26 16:12:05 +0100996static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
Suravee Suthikulpanit318fe782013-01-24 13:17:53 -0600997{
998 u32 value;
999
1000 if ((boot_cpu_data.x86 != 0x15) ||
1001 (boot_cpu_data.x86_model < 0x10) ||
1002 (boot_cpu_data.x86_model > 0x1f))
1003 return;
1004
1005 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1006 pci_read_config_dword(iommu->dev, 0xf4, &value);
1007
1008 if (value & BIT(2))
1009 return;
1010
1011 /* Select NB indirect register 0x90 and enable writing */
1012 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1013
1014 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1015 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1016 dev_name(&iommu->dev->dev));
1017
1018 /* Clear the enable writing bit */
1019 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1020}
1021
1022/*
Jay Cornwall358875f2016-02-10 15:48:01 -06001023 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1024 * Workaround:
1025 * BIOS should enable ATS write permission check by setting
1026 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1027 */
1028static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1029{
1030 u32 value;
1031
1032 if ((boot_cpu_data.x86 != 0x15) ||
1033 (boot_cpu_data.x86_model < 0x30) ||
1034 (boot_cpu_data.x86_model > 0x3f))
1035 return;
1036
1037 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1038 value = iommu_read_l2(iommu, 0x47);
1039
1040 if (value & BIT(0))
1041 return;
1042
1043 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1044 iommu_write_l2(iommu, 0x47, value | BIT(0));
1045
1046 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1047 dev_name(&iommu->dev->dev));
1048}
1049
1050/*
Joerg Roedelb65233a2008-07-11 17:14:21 +02001051 * This function clues the initialization function for one IOMMU
1052 * together and also allocates the command buffer and programs the
1053 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1054 */
Joerg Roedele47d4022008-06-26 21:27:48 +02001055static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1056{
Joerg Roedel6efed632012-06-14 15:52:58 +02001057 int ret;
1058
Joerg Roedele47d4022008-06-26 21:27:48 +02001059 spin_lock_init(&iommu->lock);
Joerg Roedelbb527772009-11-20 14:31:51 +01001060
1061 /* Add IOMMU to internal data structures */
Joerg Roedele47d4022008-06-26 21:27:48 +02001062 list_add_tail(&iommu->list, &amd_iommu_list);
Joerg Roedelbb527772009-11-20 14:31:51 +01001063 iommu->index = amd_iommus_present++;
1064
1065 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1066 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1067 return -ENOSYS;
1068 }
1069
1070 /* Index is fine - add IOMMU to the array */
1071 amd_iommus[iommu->index] = iommu;
Joerg Roedele47d4022008-06-26 21:27:48 +02001072
1073 /*
1074 * Copy data from ACPI table entry to the iommu struct
1075 */
Joerg Roedel23c742d2012-06-12 11:47:34 +02001076 iommu->devid = h->devid;
Joerg Roedele47d4022008-06-26 21:27:48 +02001077 iommu->cap_ptr = h->cap_ptr;
Joerg Roedelee893c22008-09-08 14:48:04 +02001078 iommu->pci_seg = h->pci_seg;
Joerg Roedele47d4022008-06-26 21:27:48 +02001079 iommu->mmio_phys = h->mmio_phys;
Steven L Kinney30861dd2013-06-05 16:11:48 -05001080
1081 /* Check if IVHD EFR contains proper max banks/counters */
1082 if ((h->efr != 0) &&
1083 ((h->efr & (0xF << 13)) != 0) &&
1084 ((h->efr & (0x3F << 17)) != 0)) {
1085 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1086 } else {
1087 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1088 }
1089
1090 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1091 iommu->mmio_phys_end);
Joerg Roedele47d4022008-06-26 21:27:48 +02001092 if (!iommu->mmio_base)
1093 return -ENOMEM;
1094
Joerg Roedelf2c2db52015-10-20 17:33:42 +02001095 if (alloc_command_buffer(iommu))
Joerg Roedele47d4022008-06-26 21:27:48 +02001096 return -ENOMEM;
1097
Joerg Roedelf2c2db52015-10-20 17:33:42 +02001098 if (alloc_event_buffer(iommu))
Joerg Roedel335503e2008-09-05 14:29:07 +02001099 return -ENOMEM;
1100
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001101 iommu->int_enabled = false;
1102
Joerg Roedel6efed632012-06-14 15:52:58 +02001103 ret = init_iommu_from_acpi(iommu, h);
1104 if (ret)
1105 return ret;
Joerg Roedelf6fec002012-06-21 16:51:25 +02001106
Jiang Liu7c71d302015-04-13 14:11:33 +08001107 ret = amd_iommu_create_irq_domain(iommu);
1108 if (ret)
1109 return ret;
1110
Joerg Roedelf6fec002012-06-21 16:51:25 +02001111 /*
1112 * Make sure IOMMU is not considered to translate itself. The IVRS
1113 * table tells us so, but this is a lie!
1114 */
1115 amd_iommu_rlookup_table[iommu->devid] = NULL;
1116
Joerg Roedel23c742d2012-06-12 11:47:34 +02001117 return 0;
Joerg Roedele47d4022008-06-26 21:27:48 +02001118}
1119
Joerg Roedelb65233a2008-07-11 17:14:21 +02001120/*
1121 * Iterates over all IOMMU entries in the ACPI table, allocates the
1122 * IOMMU structure and initializes it with init_iommu_one()
1123 */
Joerg Roedele47d4022008-06-26 21:27:48 +02001124static int __init init_iommu_all(struct acpi_table_header *table)
1125{
1126 u8 *p = (u8 *)table, *end = (u8 *)table;
1127 struct ivhd_header *h;
1128 struct amd_iommu *iommu;
1129 int ret;
1130
Joerg Roedele47d4022008-06-26 21:27:48 +02001131 end += table->length;
1132 p += IVRS_HEADER_LENGTH;
1133
1134 while (p < end) {
1135 h = (struct ivhd_header *)p;
1136 switch (*p) {
1137 case ACPI_IVHD_TYPE:
Joerg Roedel9c720412009-05-20 13:53:57 +02001138
Joerg Roedelae908c22009-09-01 16:52:16 +02001139 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
Joerg Roedel9c720412009-05-20 13:53:57 +02001140 "seg: %d flags: %01x info %04x\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -07001141 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
Joerg Roedel9c720412009-05-20 13:53:57 +02001142 PCI_FUNC(h->devid), h->cap_ptr,
1143 h->pci_seg, h->flags, h->info);
1144 DUMP_printk(" mmio-addr: %016llx\n",
1145 h->mmio_phys);
1146
Joerg Roedele47d4022008-06-26 21:27:48 +02001147 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
Joerg Roedel02f3b3f2012-06-11 17:45:25 +02001148 if (iommu == NULL)
1149 return -ENOMEM;
Joerg Roedel3551a702010-03-01 13:52:19 +01001150
Joerg Roedele47d4022008-06-26 21:27:48 +02001151 ret = init_iommu_one(iommu, h);
Joerg Roedel02f3b3f2012-06-11 17:45:25 +02001152 if (ret)
1153 return ret;
Joerg Roedele47d4022008-06-26 21:27:48 +02001154 break;
1155 default:
1156 break;
1157 }
1158 p += h->length;
1159
1160 }
1161 WARN_ON(p != end);
1162
1163 return 0;
1164}
1165
Steven L Kinney30861dd2013-06-05 16:11:48 -05001166
1167static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1168{
1169 u64 val = 0xabcd, val2 = 0;
1170
1171 if (!iommu_feature(iommu, FEATURE_PC))
1172 return;
1173
1174 amd_iommu_pc_present = true;
1175
1176 /* Check if the performance counters can be written to */
Suravee Suthikulpanit38e45d02016-02-23 13:03:30 +01001177 if ((0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val, true)) ||
1178 (0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val2, false)) ||
Steven L Kinney30861dd2013-06-05 16:11:48 -05001179 (val != val2)) {
1180 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1181 amd_iommu_pc_present = false;
1182 return;
1183 }
1184
1185 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1186
1187 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1188 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1189 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1190}
1191
Alex Williamson066f2e92014-06-12 16:12:37 -06001192static ssize_t amd_iommu_show_cap(struct device *dev,
1193 struct device_attribute *attr,
1194 char *buf)
1195{
1196 struct amd_iommu *iommu = dev_get_drvdata(dev);
1197 return sprintf(buf, "%x\n", iommu->cap);
1198}
1199static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1200
1201static ssize_t amd_iommu_show_features(struct device *dev,
1202 struct device_attribute *attr,
1203 char *buf)
1204{
1205 struct amd_iommu *iommu = dev_get_drvdata(dev);
1206 return sprintf(buf, "%llx\n", iommu->features);
1207}
1208static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1209
1210static struct attribute *amd_iommu_attrs[] = {
1211 &dev_attr_cap.attr,
1212 &dev_attr_features.attr,
1213 NULL,
1214};
1215
1216static struct attribute_group amd_iommu_group = {
1217 .name = "amd-iommu",
1218 .attrs = amd_iommu_attrs,
1219};
1220
1221static const struct attribute_group *amd_iommu_groups[] = {
1222 &amd_iommu_group,
1223 NULL,
1224};
Steven L Kinney30861dd2013-06-05 16:11:48 -05001225
Joerg Roedel23c742d2012-06-12 11:47:34 +02001226static int iommu_init_pci(struct amd_iommu *iommu)
1227{
1228 int cap_ptr = iommu->cap_ptr;
1229 u32 range, misc, low, high;
1230
Shuah Khanc5081cd2013-02-27 17:07:19 -07001231 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
Joerg Roedel23c742d2012-06-12 11:47:34 +02001232 iommu->devid & 0xff);
1233 if (!iommu->dev)
1234 return -ENODEV;
1235
Jiang Liucbbc00b2015-10-09 22:07:31 +08001236 /* Prevent binding other PCI device drivers to IOMMU devices */
1237 iommu->dev->match_driver = false;
1238
Joerg Roedel23c742d2012-06-12 11:47:34 +02001239 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1240 &iommu->cap);
1241 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1242 &range);
1243 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1244 &misc);
1245
Joerg Roedel23c742d2012-06-12 11:47:34 +02001246 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1247 amd_iommu_iotlb_sup = false;
1248
1249 /* read extended feature bits */
1250 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1251 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1252
1253 iommu->features = ((u64)high << 32) | low;
1254
1255 if (iommu_feature(iommu, FEATURE_GT)) {
1256 int glxval;
Suravee Suthikulpanita919a012014-03-05 18:54:18 -06001257 u32 max_pasid;
1258 u64 pasmax;
Joerg Roedel23c742d2012-06-12 11:47:34 +02001259
Suravee Suthikulpanita919a012014-03-05 18:54:18 -06001260 pasmax = iommu->features & FEATURE_PASID_MASK;
1261 pasmax >>= FEATURE_PASID_SHIFT;
1262 max_pasid = (1 << (pasmax + 1)) - 1;
Joerg Roedel23c742d2012-06-12 11:47:34 +02001263
Suravee Suthikulpanita919a012014-03-05 18:54:18 -06001264 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1265
1266 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
Joerg Roedel23c742d2012-06-12 11:47:34 +02001267
1268 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1269 glxval >>= FEATURE_GLXVAL_SHIFT;
1270
1271 if (amd_iommu_max_glx_val == -1)
1272 amd_iommu_max_glx_val = glxval;
1273 else
1274 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1275 }
1276
1277 if (iommu_feature(iommu, FEATURE_GT) &&
1278 iommu_feature(iommu, FEATURE_PPR)) {
1279 iommu->is_iommu_v2 = true;
1280 amd_iommu_v2_present = true;
1281 }
1282
Joerg Roedelf2c2db52015-10-20 17:33:42 +02001283 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1284 return -ENOMEM;
Joerg Roedel23c742d2012-06-12 11:47:34 +02001285
1286 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1287 amd_iommu_np_cache = true;
1288
Steven L Kinney30861dd2013-06-05 16:11:48 -05001289 init_iommu_perf_ctr(iommu);
1290
Joerg Roedel23c742d2012-06-12 11:47:34 +02001291 if (is_rd890_iommu(iommu->dev)) {
1292 int i, j;
1293
1294 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1295 PCI_DEVFN(0, 0));
1296
1297 /*
1298 * Some rd890 systems may not be fully reconfigured by the
1299 * BIOS, so it's necessary for us to store this information so
1300 * it can be reprogrammed on resume
1301 */
1302 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1303 &iommu->stored_addr_lo);
1304 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1305 &iommu->stored_addr_hi);
1306
1307 /* Low bit locks writes to configuration space */
1308 iommu->stored_addr_lo &= ~1;
1309
1310 for (i = 0; i < 6; i++)
1311 for (j = 0; j < 0x12; j++)
1312 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1313
1314 for (i = 0; i < 0x83; i++)
1315 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1316 }
1317
Suravee Suthikulpanit318fe782013-01-24 13:17:53 -06001318 amd_iommu_erratum_746_workaround(iommu);
Jay Cornwall358875f2016-02-10 15:48:01 -06001319 amd_iommu_ats_write_check_workaround(iommu);
Suravee Suthikulpanit318fe782013-01-24 13:17:53 -06001320
Alex Williamson066f2e92014-06-12 16:12:37 -06001321 iommu->iommu_dev = iommu_device_create(&iommu->dev->dev, iommu,
1322 amd_iommu_groups, "ivhd%d",
1323 iommu->index);
1324
Joerg Roedel23c742d2012-06-12 11:47:34 +02001325 return pci_enable_device(iommu->dev);
1326}
1327
Joerg Roedel4d121c32012-06-14 12:21:55 +02001328static void print_iommu_info(void)
1329{
1330 static const char * const feat_str[] = {
1331 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1332 "IA", "GA", "HE", "PC"
1333 };
1334 struct amd_iommu *iommu;
1335
1336 for_each_iommu(iommu) {
1337 int i;
1338
1339 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1340 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1341
1342 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1343 pr_info("AMD-Vi: Extended features: ");
Joerg Roedel2bd5ed02012-08-10 11:34:08 +02001344 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
Joerg Roedel4d121c32012-06-14 12:21:55 +02001345 if (iommu_feature(iommu, (1ULL << i)))
1346 pr_cont(" %s", feat_str[i]);
1347 }
Steven L Kinney30861dd2013-06-05 16:11:48 -05001348 pr_cont("\n");
Borislav Petkov500c25e2012-09-28 16:22:26 +02001349 }
Joerg Roedel4d121c32012-06-14 12:21:55 +02001350 }
Joerg Roedelebe60bb2012-07-02 18:36:03 +02001351 if (irq_remapping_enabled)
1352 pr_info("AMD-Vi: Interrupt remapping enabled\n");
Joerg Roedel4d121c32012-06-14 12:21:55 +02001353}
1354
Joerg Roedel2c0ae172012-06-12 15:59:30 +02001355static int __init amd_iommu_init_pci(void)
Joerg Roedel23c742d2012-06-12 11:47:34 +02001356{
1357 struct amd_iommu *iommu;
1358 int ret = 0;
1359
1360 for_each_iommu(iommu) {
1361 ret = iommu_init_pci(iommu);
1362 if (ret)
1363 break;
1364 }
1365
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02001366 init_device_table_dma();
Joerg Roedel23c742d2012-06-12 11:47:34 +02001367
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02001368 for_each_iommu(iommu)
1369 iommu_flush_all_caches(iommu);
1370
Joerg Roedel3a18404c2015-05-28 18:41:45 +02001371 ret = amd_iommu_init_api();
Joerg Roedel23c742d2012-06-12 11:47:34 +02001372
Joerg Roedel3a18404c2015-05-28 18:41:45 +02001373 if (!ret)
1374 print_iommu_info();
Joerg Roedel4d121c32012-06-14 12:21:55 +02001375
Joerg Roedel23c742d2012-06-12 11:47:34 +02001376 return ret;
1377}
1378
Joerg Roedelb65233a2008-07-11 17:14:21 +02001379/****************************************************************************
1380 *
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001381 * The following functions initialize the MSI interrupts for all IOMMUs
Frank Arnolddf805ab2012-08-27 19:21:04 +02001382 * in the system. It's a bit challenging because there could be multiple
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001383 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1384 * pci_dev.
1385 *
1386 ****************************************************************************/
1387
Joerg Roedel9f800de2009-11-23 12:45:25 +01001388static int iommu_setup_msi(struct amd_iommu *iommu)
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001389{
1390 int r;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001391
Joerg Roedel9ddd5922012-03-15 16:29:47 +01001392 r = pci_enable_msi(iommu->dev);
1393 if (r)
1394 return r;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001395
Joerg Roedel72fe00f2011-05-10 10:50:42 +02001396 r = request_threaded_irq(iommu->dev->irq,
1397 amd_iommu_int_handler,
1398 amd_iommu_int_thread,
1399 0, "AMD-Vi",
Suravee Suthikulpanit3f398bc2013-04-22 16:32:34 -05001400 iommu);
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001401
1402 if (r) {
1403 pci_disable_msi(iommu->dev);
Joerg Roedel9ddd5922012-03-15 16:29:47 +01001404 return r;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001405 }
1406
Joerg Roedelfab6afa2009-05-04 18:46:34 +02001407 iommu->int_enabled = true;
Joerg Roedel1a29ac02011-11-10 15:41:40 +01001408
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001409 return 0;
1410}
1411
Joerg Roedel05f92db2009-05-12 09:52:46 +02001412static int iommu_init_msi(struct amd_iommu *iommu)
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001413{
Joerg Roedel9ddd5922012-03-15 16:29:47 +01001414 int ret;
1415
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001416 if (iommu->int_enabled)
Joerg Roedel9ddd5922012-03-15 16:29:47 +01001417 goto enable_faults;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001418
Yijing Wang82fcfc62013-08-08 21:12:36 +08001419 if (iommu->dev->msi_cap)
Joerg Roedel9ddd5922012-03-15 16:29:47 +01001420 ret = iommu_setup_msi(iommu);
1421 else
1422 ret = -ENODEV;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001423
Joerg Roedel9ddd5922012-03-15 16:29:47 +01001424 if (ret)
1425 return ret;
1426
1427enable_faults:
1428 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1429
1430 if (iommu->ppr_log != NULL)
1431 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1432
1433 return 0;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001434}
1435
1436/****************************************************************************
1437 *
Joerg Roedelb65233a2008-07-11 17:14:21 +02001438 * The next functions belong to the third pass of parsing the ACPI
1439 * table. In this last pass the memory mapping requirements are
Frank Arnolddf805ab2012-08-27 19:21:04 +02001440 * gathered (like exclusion and unity mapping ranges).
Joerg Roedelb65233a2008-07-11 17:14:21 +02001441 *
1442 ****************************************************************************/
1443
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001444static void __init free_unity_maps(void)
1445{
1446 struct unity_map_entry *entry, *next;
1447
1448 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1449 list_del(&entry->list);
1450 kfree(entry);
1451 }
1452}
1453
Joerg Roedelb65233a2008-07-11 17:14:21 +02001454/* called when we find an exclusion range definition in ACPI */
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001455static int __init init_exclusion_range(struct ivmd_header *m)
1456{
1457 int i;
1458
1459 switch (m->type) {
1460 case ACPI_IVMD_TYPE:
1461 set_device_exclusion_range(m->devid, m);
1462 break;
1463 case ACPI_IVMD_TYPE_ALL:
Joerg Roedel3a61ec32008-07-25 13:07:50 +02001464 for (i = 0; i <= amd_iommu_last_bdf; ++i)
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001465 set_device_exclusion_range(i, m);
1466 break;
1467 case ACPI_IVMD_TYPE_RANGE:
1468 for (i = m->devid; i <= m->aux; ++i)
1469 set_device_exclusion_range(i, m);
1470 break;
1471 default:
1472 break;
1473 }
1474
1475 return 0;
1476}
1477
Joerg Roedelb65233a2008-07-11 17:14:21 +02001478/* called for unity map ACPI definition */
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001479static int __init init_unity_map_range(struct ivmd_header *m)
1480{
Joerg Roedel98f1ad22012-07-06 13:28:37 +02001481 struct unity_map_entry *e = NULL;
Joerg Roedel02acc432009-05-20 16:24:21 +02001482 char *s;
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001483
1484 e = kzalloc(sizeof(*e), GFP_KERNEL);
1485 if (e == NULL)
1486 return -ENOMEM;
1487
1488 switch (m->type) {
1489 default:
Joerg Roedel0bc252f2009-05-22 12:48:05 +02001490 kfree(e);
1491 return 0;
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001492 case ACPI_IVMD_TYPE:
Joerg Roedel02acc432009-05-20 16:24:21 +02001493 s = "IVMD_TYPEi\t\t\t";
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001494 e->devid_start = e->devid_end = m->devid;
1495 break;
1496 case ACPI_IVMD_TYPE_ALL:
Joerg Roedel02acc432009-05-20 16:24:21 +02001497 s = "IVMD_TYPE_ALL\t\t";
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001498 e->devid_start = 0;
1499 e->devid_end = amd_iommu_last_bdf;
1500 break;
1501 case ACPI_IVMD_TYPE_RANGE:
Joerg Roedel02acc432009-05-20 16:24:21 +02001502 s = "IVMD_TYPE_RANGE\t\t";
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001503 e->devid_start = m->devid;
1504 e->devid_end = m->aux;
1505 break;
1506 }
1507 e->address_start = PAGE_ALIGN(m->range_start);
1508 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1509 e->prot = m->flags >> 1;
1510
Joerg Roedel02acc432009-05-20 16:24:21 +02001511 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1512 " range_start: %016llx range_end: %016llx flags: %x\n", s,
Shuah Khanc5081cd2013-02-27 17:07:19 -07001513 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1514 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
Joerg Roedel02acc432009-05-20 16:24:21 +02001515 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1516 e->address_start, e->address_end, m->flags);
1517
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001518 list_add_tail(&e->list, &amd_iommu_unity_map);
1519
1520 return 0;
1521}
1522
Joerg Roedelb65233a2008-07-11 17:14:21 +02001523/* iterates over all memory definitions we find in the ACPI table */
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001524static int __init init_memory_definitions(struct acpi_table_header *table)
1525{
1526 u8 *p = (u8 *)table, *end = (u8 *)table;
1527 struct ivmd_header *m;
1528
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001529 end += table->length;
1530 p += IVRS_HEADER_LENGTH;
1531
1532 while (p < end) {
1533 m = (struct ivmd_header *)p;
1534 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1535 init_exclusion_range(m);
1536 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1537 init_unity_map_range(m);
1538
1539 p += m->length;
1540 }
1541
1542 return 0;
1543}
1544
Joerg Roedelb65233a2008-07-11 17:14:21 +02001545/*
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001546 * Init the device table to not allow DMA access for devices and
1547 * suppress all page faults
1548 */
Joerg Roedel33f28c52012-06-15 18:03:31 +02001549static void init_device_table_dma(void)
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001550{
Joerg Roedel0de66d52011-06-06 16:04:02 +02001551 u32 devid;
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001552
1553 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1554 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1555 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001556 }
1557}
1558
Joerg Roedeld04e0ba2012-07-02 16:02:20 +02001559static void __init uninit_device_table_dma(void)
1560{
1561 u32 devid;
1562
1563 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1564 amd_iommu_dev_table[devid].data[0] = 0ULL;
1565 amd_iommu_dev_table[devid].data[1] = 0ULL;
1566 }
1567}
1568
Joerg Roedel33f28c52012-06-15 18:03:31 +02001569static void init_device_table(void)
1570{
1571 u32 devid;
1572
1573 if (!amd_iommu_irq_remap)
1574 return;
1575
1576 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1577 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1578}
1579
Joerg Roedele9bf5192010-09-20 14:33:07 +02001580static void iommu_init_flags(struct amd_iommu *iommu)
1581{
1582 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1583 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1584 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1585
1586 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1587 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1588 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1589
1590 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1591 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1592 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1593
1594 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1595 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1596 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1597
1598 /*
1599 * make IOMMU memory accesses cache coherent
1600 */
1601 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
Joerg Roedel1456e9d2011-12-22 14:51:53 +01001602
1603 /* Set IOTLB invalidation timeout to 1s */
1604 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
Joerg Roedele9bf5192010-09-20 14:33:07 +02001605}
1606
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001607static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
Joerg Roedel4c894f42010-09-23 15:15:19 +02001608{
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001609 int i, j;
1610 u32 ioc_feature_control;
Joerg Roedelc1bf94e2012-05-31 17:38:11 +02001611 struct pci_dev *pdev = iommu->root_pdev;
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001612
1613 /* RD890 BIOSes may not have completely reconfigured the iommu */
Joerg Roedelc1bf94e2012-05-31 17:38:11 +02001614 if (!is_rd890_iommu(iommu->dev) || !pdev)
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001615 return;
1616
1617 /*
1618 * First, we need to ensure that the iommu is enabled. This is
1619 * controlled by a register in the northbridge
1620 */
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001621
1622 /* Select Northbridge indirect register 0x75 and enable writing */
1623 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1624 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1625
1626 /* Enable the iommu */
1627 if (!(ioc_feature_control & 0x1))
1628 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1629
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001630 /* Restore the iommu BAR */
1631 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1632 iommu->stored_addr_lo);
1633 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1634 iommu->stored_addr_hi);
1635
1636 /* Restore the l1 indirect regs for each of the 6 l1s */
1637 for (i = 0; i < 6; i++)
1638 for (j = 0; j < 0x12; j++)
1639 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1640
1641 /* Restore the l2 indirect regs */
1642 for (i = 0; i < 0x83; i++)
1643 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1644
1645 /* Lock PCI setup registers */
1646 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1647 iommu->stored_addr_lo | 1);
Joerg Roedel4c894f42010-09-23 15:15:19 +02001648}
1649
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001650/*
Joerg Roedelb65233a2008-07-11 17:14:21 +02001651 * This function finally enables all IOMMUs found in the system after
1652 * they have been initialized
1653 */
Joerg Roedel11ee5ac2012-06-12 16:30:06 +02001654static void early_enable_iommus(void)
Joerg Roedel87361972008-06-26 21:28:07 +02001655{
1656 struct amd_iommu *iommu;
1657
Joerg Roedel3bd22172009-05-04 15:06:20 +02001658 for_each_iommu(iommu) {
Chris Wrighta8c485b2009-06-15 15:53:45 +02001659 iommu_disable(iommu);
Joerg Roedele9bf5192010-09-20 14:33:07 +02001660 iommu_init_flags(iommu);
Joerg Roedel58492e12009-05-04 18:41:16 +02001661 iommu_set_device_table(iommu);
1662 iommu_enable_command_buffer(iommu);
1663 iommu_enable_event_buffer(iommu);
Joerg Roedel87361972008-06-26 21:28:07 +02001664 iommu_set_exclusion_range(iommu);
1665 iommu_enable(iommu);
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001666 iommu_flush_all_caches(iommu);
Joerg Roedel87361972008-06-26 21:28:07 +02001667 }
1668}
1669
Joerg Roedel11ee5ac2012-06-12 16:30:06 +02001670static void enable_iommus_v2(void)
1671{
1672 struct amd_iommu *iommu;
1673
1674 for_each_iommu(iommu) {
1675 iommu_enable_ppr_log(iommu);
1676 iommu_enable_gt(iommu);
1677 }
1678}
1679
1680static void enable_iommus(void)
1681{
1682 early_enable_iommus();
1683
1684 enable_iommus_v2();
1685}
1686
Joerg Roedel92ac4322009-05-19 19:06:27 +02001687static void disable_iommus(void)
1688{
1689 struct amd_iommu *iommu;
1690
1691 for_each_iommu(iommu)
1692 iommu_disable(iommu);
1693}
1694
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001695/*
1696 * Suspend/Resume support
1697 * disable suspend until real resume implemented
1698 */
1699
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01001700static void amd_iommu_resume(void)
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001701{
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001702 struct amd_iommu *iommu;
1703
1704 for_each_iommu(iommu)
1705 iommu_apply_resume_quirks(iommu);
1706
Joerg Roedel736501e2009-05-12 09:56:12 +02001707 /* re-load the hardware */
1708 enable_iommus();
Joerg Roedel3d9761e2012-03-15 16:39:21 +01001709
1710 amd_iommu_enable_interrupts();
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001711}
1712
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01001713static int amd_iommu_suspend(void)
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001714{
Joerg Roedel736501e2009-05-12 09:56:12 +02001715 /* disable IOMMUs to go out of the way for BIOS */
1716 disable_iommus();
1717
1718 return 0;
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001719}
1720
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01001721static struct syscore_ops amd_iommu_syscore_ops = {
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001722 .suspend = amd_iommu_suspend,
1723 .resume = amd_iommu_resume,
1724};
1725
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001726static void __init free_on_init_error(void)
1727{
Joerg Roedel0ea2c422012-06-15 18:05:20 +02001728 free_pages((unsigned long)irq_lookup_table,
1729 get_order(rlookup_table_size));
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001730
Julia Lawalla5919892015-09-13 14:15:31 +02001731 kmem_cache_destroy(amd_iommu_irq_cache);
1732 amd_iommu_irq_cache = NULL;
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001733
1734 free_pages((unsigned long)amd_iommu_rlookup_table,
1735 get_order(rlookup_table_size));
1736
1737 free_pages((unsigned long)amd_iommu_alias_table,
1738 get_order(alias_table_size));
1739
1740 free_pages((unsigned long)amd_iommu_dev_table,
1741 get_order(dev_table_size));
1742
1743 free_iommu_all();
1744
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001745#ifdef CONFIG_GART_IOMMU
1746 /*
1747 * We failed to initialize the AMD IOMMU - try fallback to GART
1748 * if possible.
1749 */
1750 gart_iommu_init();
1751
1752#endif
1753}
1754
Joerg Roedelc2ff5cf52012-10-16 14:52:51 +02001755/* SB IOAPIC is always on this device in AMD systems */
1756#define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
1757
Joerg Roedeleb1eb7a2012-07-05 11:58:02 +02001758static bool __init check_ioapic_information(void)
1759{
Joerg Roedeldfbb6d42013-04-09 19:06:18 +02001760 const char *fw_bug = FW_BUG;
Joerg Roedelc2ff5cf52012-10-16 14:52:51 +02001761 bool ret, has_sb_ioapic;
Joerg Roedeleb1eb7a2012-07-05 11:58:02 +02001762 int idx;
1763
Joerg Roedelc2ff5cf52012-10-16 14:52:51 +02001764 has_sb_ioapic = false;
1765 ret = false;
Joerg Roedeleb1eb7a2012-07-05 11:58:02 +02001766
Joerg Roedeldfbb6d42013-04-09 19:06:18 +02001767 /*
1768 * If we have map overrides on the kernel command line the
1769 * messages in this function might not describe firmware bugs
1770 * anymore - so be careful
1771 */
1772 if (cmdline_maps)
1773 fw_bug = "";
1774
Joerg Roedelc2ff5cf52012-10-16 14:52:51 +02001775 for (idx = 0; idx < nr_ioapics; idx++) {
1776 int devid, id = mpc_ioapic_id(idx);
1777
1778 devid = get_ioapic_devid(id);
1779 if (devid < 0) {
Joerg Roedeldfbb6d42013-04-09 19:06:18 +02001780 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
1781 fw_bug, id);
Joerg Roedelc2ff5cf52012-10-16 14:52:51 +02001782 ret = false;
1783 } else if (devid == IOAPIC_SB_DEVID) {
1784 has_sb_ioapic = true;
1785 ret = true;
Joerg Roedeleb1eb7a2012-07-05 11:58:02 +02001786 }
1787 }
1788
Joerg Roedelc2ff5cf52012-10-16 14:52:51 +02001789 if (!has_sb_ioapic) {
1790 /*
1791 * We expect the SB IOAPIC to be listed in the IVRS
1792 * table. The system timer is connected to the SB IOAPIC
1793 * and if we don't have it in the list the system will
1794 * panic at boot time. This situation usually happens
1795 * when the BIOS is buggy and provides us the wrong
1796 * device id for the IOAPIC in the system.
1797 */
Joerg Roedeldfbb6d42013-04-09 19:06:18 +02001798 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
Joerg Roedelc2ff5cf52012-10-16 14:52:51 +02001799 }
1800
1801 if (!ret)
Joerg Roedeldfbb6d42013-04-09 19:06:18 +02001802 pr_err("AMD-Vi: Disabling interrupt remapping\n");
Joerg Roedelc2ff5cf52012-10-16 14:52:51 +02001803
1804 return ret;
Joerg Roedeleb1eb7a2012-07-05 11:58:02 +02001805}
1806
Joerg Roedeld04e0ba2012-07-02 16:02:20 +02001807static void __init free_dma_resources(void)
1808{
Joerg Roedeld04e0ba2012-07-02 16:02:20 +02001809 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1810 get_order(MAX_DOMAIN_ID/8));
1811
1812 free_unity_maps();
1813}
1814
Joerg Roedelb65233a2008-07-11 17:14:21 +02001815/*
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001816 * This is the hardware init function for AMD IOMMU in the system.
1817 * This function is called either from amd_iommu_init or from the interrupt
1818 * remapping setup code.
Joerg Roedelb65233a2008-07-11 17:14:21 +02001819 *
1820 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1821 * three times:
1822 *
1823 * 1 pass) Find the highest PCI device id the driver has to handle.
1824 * Upon this information the size of the data structures is
1825 * determined that needs to be allocated.
1826 *
1827 * 2 pass) Initialize the data structures just allocated with the
1828 * information in the ACPI table about available AMD IOMMUs
1829 * in the system. It also maps the PCI devices in the
1830 * system to specific IOMMUs
1831 *
1832 * 3 pass) After the basic data structures are allocated and
1833 * initialized we update them with information about memory
1834 * remapping requirements parsed out of the ACPI table in
1835 * this last pass.
1836 *
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001837 * After everything is set up the IOMMUs are enabled and the necessary
1838 * hotplug and suspend notifiers are registered.
Joerg Roedelb65233a2008-07-11 17:14:21 +02001839 */
Joerg Roedel643511b2012-06-12 12:09:35 +02001840static int __init early_amd_iommu_init(void)
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001841{
Joerg Roedel02f3b3f2012-06-11 17:45:25 +02001842 struct acpi_table_header *ivrs_base;
1843 acpi_size ivrs_size;
1844 acpi_status status;
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001845 int i, ret = 0;
1846
Joerg Roedel643511b2012-06-12 12:09:35 +02001847 if (!amd_iommu_detected)
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001848 return -ENODEV;
1849
Joerg Roedel02f3b3f2012-06-11 17:45:25 +02001850 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1851 if (status == AE_NOT_FOUND)
1852 return -ENODEV;
1853 else if (ACPI_FAILURE(status)) {
1854 const char *err = acpi_format_exception(status);
1855 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1856 return -EINVAL;
1857 }
1858
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001859 /*
1860 * First parse ACPI tables to find the largest Bus/Dev/Func
1861 * we need to handle. Upon this information the shared data
1862 * structures for the IOMMUs in the system will be allocated
1863 */
Joerg Roedel2c0ae172012-06-12 15:59:30 +02001864 ret = find_last_devid_acpi(ivrs_base);
1865 if (ret)
Joerg Roedel3551a702010-03-01 13:52:19 +01001866 goto out;
1867
Joerg Roedelc5714842008-07-11 17:14:25 +02001868 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1869 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1870 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001871
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001872 /* Device table - directly used by all IOMMUs */
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001873 ret = -ENOMEM;
Joerg Roedel5dc8bff2008-07-11 17:14:32 +02001874 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001875 get_order(dev_table_size));
1876 if (amd_iommu_dev_table == NULL)
1877 goto out;
1878
1879 /*
1880 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1881 * IOMMU see for that device
1882 */
1883 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1884 get_order(alias_table_size));
1885 if (amd_iommu_alias_table == NULL)
Joerg Roedel2c0ae172012-06-12 15:59:30 +02001886 goto out;
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001887
1888 /* IOMMU rlookup table - find the IOMMU for a specific device */
Joerg Roedel83fd5cc2008-12-16 19:17:11 +01001889 amd_iommu_rlookup_table = (void *)__get_free_pages(
1890 GFP_KERNEL | __GFP_ZERO,
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001891 get_order(rlookup_table_size));
1892 if (amd_iommu_rlookup_table == NULL)
Joerg Roedel2c0ae172012-06-12 15:59:30 +02001893 goto out;
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001894
Joerg Roedel5dc8bff2008-07-11 17:14:32 +02001895 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1896 GFP_KERNEL | __GFP_ZERO,
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001897 get_order(MAX_DOMAIN_ID/8));
1898 if (amd_iommu_pd_alloc_bitmap == NULL)
Joerg Roedel2c0ae172012-06-12 15:59:30 +02001899 goto out;
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001900
1901 /*
Joerg Roedel5dc8bff2008-07-11 17:14:32 +02001902 * let all alias entries point to itself
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001903 */
Joerg Roedel3a61ec32008-07-25 13:07:50 +02001904 for (i = 0; i <= amd_iommu_last_bdf; ++i)
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001905 amd_iommu_alias_table[i] = i;
1906
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001907 /*
1908 * never allocate domain 0 because its used as the non-allocated and
1909 * error value placeholder
1910 */
1911 amd_iommu_pd_alloc_bitmap[0] = 1;
1912
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001913 spin_lock_init(&amd_iommu_pd_lock);
1914
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001915 /*
1916 * now the data structures are allocated and basically initialized
1917 * start the real acpi table scan
1918 */
Joerg Roedel02f3b3f2012-06-11 17:45:25 +02001919 ret = init_iommu_all(ivrs_base);
1920 if (ret)
Joerg Roedel2c0ae172012-06-12 15:59:30 +02001921 goto out;
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001922
Joerg Roedeleb1eb7a2012-07-05 11:58:02 +02001923 if (amd_iommu_irq_remap)
1924 amd_iommu_irq_remap = check_ioapic_information();
1925
Joerg Roedel05152a02012-06-15 16:53:51 +02001926 if (amd_iommu_irq_remap) {
1927 /*
1928 * Interrupt remapping enabled, create kmem_cache for the
1929 * remapping tables.
1930 */
Wei Yongjun83ed9c12013-04-23 10:47:44 +08001931 ret = -ENOMEM;
Joerg Roedel05152a02012-06-15 16:53:51 +02001932 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
1933 MAX_IRQS_PER_TABLE * sizeof(u32),
1934 IRQ_TABLE_ALIGNMENT,
1935 0, NULL);
1936 if (!amd_iommu_irq_cache)
1937 goto out;
Joerg Roedel0ea2c422012-06-15 18:05:20 +02001938
1939 irq_lookup_table = (void *)__get_free_pages(
1940 GFP_KERNEL | __GFP_ZERO,
1941 get_order(rlookup_table_size));
1942 if (!irq_lookup_table)
1943 goto out;
Joerg Roedel05152a02012-06-15 16:53:51 +02001944 }
1945
Joerg Roedel02f3b3f2012-06-11 17:45:25 +02001946 ret = init_memory_definitions(ivrs_base);
1947 if (ret)
Joerg Roedel2c0ae172012-06-12 15:59:30 +02001948 goto out;
Joerg Roedel3551a702010-03-01 13:52:19 +01001949
Joerg Roedeleb1eb7a2012-07-05 11:58:02 +02001950 /* init the device table */
1951 init_device_table();
1952
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001953out:
Joerg Roedel02f3b3f2012-06-11 17:45:25 +02001954 /* Don't leak any ACPI memory */
1955 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1956 ivrs_base = NULL;
1957
Joerg Roedel8704a1b2012-03-01 15:57:53 +01001958 return ret;
Joerg Roedel643511b2012-06-12 12:09:35 +02001959}
1960
Gerard Snitselaarae295142012-03-16 11:38:22 -07001961static int amd_iommu_enable_interrupts(void)
Joerg Roedel3d9761e2012-03-15 16:39:21 +01001962{
1963 struct amd_iommu *iommu;
1964 int ret = 0;
1965
1966 for_each_iommu(iommu) {
1967 ret = iommu_init_msi(iommu);
1968 if (ret)
1969 goto out;
1970 }
1971
1972out:
1973 return ret;
1974}
1975
Joerg Roedel02f3b3f2012-06-11 17:45:25 +02001976static bool detect_ivrs(void)
1977{
1978 struct acpi_table_header *ivrs_base;
1979 acpi_size ivrs_size;
1980 acpi_status status;
1981
1982 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1983 if (status == AE_NOT_FOUND)
1984 return false;
1985 else if (ACPI_FAILURE(status)) {
1986 const char *err = acpi_format_exception(status);
1987 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1988 return false;
1989 }
1990
1991 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1992
Joerg Roedel1adb7d32012-08-06 14:18:42 +02001993 /* Make sure ACS will be enabled during PCI probe */
1994 pci_request_acs();
1995
Joerg Roedel02f3b3f2012-06-11 17:45:25 +02001996 return true;
1997}
1998
Joerg Roedel2c0ae172012-06-12 15:59:30 +02001999/****************************************************************************
2000 *
2001 * AMD IOMMU Initialization State Machine
2002 *
2003 ****************************************************************************/
2004
2005static int __init state_next(void)
2006{
2007 int ret = 0;
2008
2009 switch (init_state) {
2010 case IOMMU_START_STATE:
2011 if (!detect_ivrs()) {
2012 init_state = IOMMU_NOT_FOUND;
2013 ret = -ENODEV;
2014 } else {
2015 init_state = IOMMU_IVRS_DETECTED;
2016 }
2017 break;
2018 case IOMMU_IVRS_DETECTED:
2019 ret = early_amd_iommu_init();
2020 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2021 break;
2022 case IOMMU_ACPI_FINISHED:
2023 early_enable_iommus();
2024 register_syscore_ops(&amd_iommu_syscore_ops);
2025 x86_platform.iommu_shutdown = disable_iommus;
2026 init_state = IOMMU_ENABLED;
2027 break;
2028 case IOMMU_ENABLED:
2029 ret = amd_iommu_init_pci();
2030 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2031 enable_iommus_v2();
2032 break;
2033 case IOMMU_PCI_INIT:
2034 ret = amd_iommu_enable_interrupts();
2035 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2036 break;
2037 case IOMMU_INTERRUPTS_EN:
Joerg Roedel1e6a7b02015-07-28 16:58:48 +02002038 ret = amd_iommu_init_dma_ops();
Joerg Roedel2c0ae172012-06-12 15:59:30 +02002039 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2040 break;
2041 case IOMMU_DMA_OPS:
2042 init_state = IOMMU_INITIALIZED;
2043 break;
2044 case IOMMU_INITIALIZED:
2045 /* Nothing to do */
2046 break;
2047 case IOMMU_NOT_FOUND:
2048 case IOMMU_INIT_ERROR:
2049 /* Error states => do nothing */
2050 ret = -EINVAL;
2051 break;
2052 default:
2053 /* Unknown state */
2054 BUG();
2055 }
2056
2057 return ret;
2058}
2059
2060static int __init iommu_go_to_state(enum iommu_init_state state)
2061{
2062 int ret = 0;
2063
2064 while (init_state != state) {
2065 ret = state_next();
2066 if (init_state == IOMMU_NOT_FOUND ||
2067 init_state == IOMMU_INIT_ERROR)
2068 break;
2069 }
2070
2071 return ret;
2072}
2073
Joerg Roedel6b474b82012-06-26 16:46:04 +02002074#ifdef CONFIG_IRQ_REMAP
2075int __init amd_iommu_prepare(void)
2076{
Thomas Gleixner3f4cb7c2015-01-23 14:32:46 +01002077 int ret;
2078
Jiang Liu7fa1c842015-01-07 15:31:42 +08002079 amd_iommu_irq_remap = true;
Joerg Roedel84d07792015-01-07 15:31:39 +08002080
Thomas Gleixner3f4cb7c2015-01-23 14:32:46 +01002081 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2082 if (ret)
2083 return ret;
2084 return amd_iommu_irq_remap ? 0 : -ENODEV;
Joerg Roedel6b474b82012-06-26 16:46:04 +02002085}
Joerg Roedel2c0ae172012-06-12 15:59:30 +02002086
Joerg Roedel6b474b82012-06-26 16:46:04 +02002087int __init amd_iommu_enable(void)
2088{
2089 int ret;
2090
2091 ret = iommu_go_to_state(IOMMU_ENABLED);
2092 if (ret)
2093 return ret;
2094
2095 irq_remapping_enabled = 1;
2096
2097 return 0;
2098}
2099
2100void amd_iommu_disable(void)
2101{
2102 amd_iommu_suspend();
2103}
2104
2105int amd_iommu_reenable(int mode)
2106{
2107 amd_iommu_resume();
2108
2109 return 0;
2110}
2111
2112int __init amd_iommu_enable_faulting(void)
2113{
2114 /* We enable MSI later when PCI is initialized */
2115 return 0;
2116}
2117#endif
Joerg Roedel2c0ae172012-06-12 15:59:30 +02002118
Joerg Roedel8704a1b2012-03-01 15:57:53 +01002119/*
2120 * This is the core init function for AMD IOMMU hardware in the system.
2121 * This function is called from the generic x86 DMA layer initialization
2122 * code.
Joerg Roedel8704a1b2012-03-01 15:57:53 +01002123 */
2124static int __init amd_iommu_init(void)
2125{
Joerg Roedel2c0ae172012-06-12 15:59:30 +02002126 int ret;
Joerg Roedel8704a1b2012-03-01 15:57:53 +01002127
Joerg Roedel2c0ae172012-06-12 15:59:30 +02002128 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2129 if (ret) {
Joerg Roedeld04e0ba2012-07-02 16:02:20 +02002130 free_dma_resources();
2131 if (!irq_remapping_enabled) {
2132 disable_iommus();
2133 free_on_init_error();
2134 } else {
2135 struct amd_iommu *iommu;
2136
2137 uninit_device_table_dma();
2138 for_each_iommu(iommu)
2139 iommu_flush_all_caches(iommu);
2140 }
Joerg Roedel2c0ae172012-06-12 15:59:30 +02002141 }
Joerg Roedel8704a1b2012-03-01 15:57:53 +01002142
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02002143 return ret;
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02002144}
2145
Joerg Roedelb65233a2008-07-11 17:14:21 +02002146/****************************************************************************
2147 *
2148 * Early detect code. This code runs at IOMMU detection time in the DMA
2149 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2150 * IOMMUs
2151 *
2152 ****************************************************************************/
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04002153int __init amd_iommu_detect(void)
Joerg Roedelae7877d2008-06-26 21:27:51 +02002154{
Joerg Roedel2c0ae172012-06-12 15:59:30 +02002155 int ret;
Joerg Roedel02f3b3f2012-06-11 17:45:25 +02002156
FUJITA Tomonori75f1cdf2009-11-10 19:46:20 +09002157 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04002158 return -ENODEV;
Joerg Roedelae7877d2008-06-26 21:27:51 +02002159
Joerg Roedela5235722010-05-11 17:12:33 +02002160 if (amd_iommu_disabled)
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04002161 return -ENODEV;
Joerg Roedela5235722010-05-11 17:12:33 +02002162
Joerg Roedel2c0ae172012-06-12 15:59:30 +02002163 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2164 if (ret)
2165 return ret;
Linus Torvalds11bd04f2009-12-11 12:18:16 -08002166
Joerg Roedel02f3b3f2012-06-11 17:45:25 +02002167 amd_iommu_detected = true;
2168 iommu_detected = 1;
2169 x86_init.iommu.iommu_init = amd_iommu_init;
2170
Jérôme Glisse4781bc42015-08-31 18:13:03 -04002171 return 1;
Joerg Roedelae7877d2008-06-26 21:27:51 +02002172}
2173
Joerg Roedelb65233a2008-07-11 17:14:21 +02002174/****************************************************************************
2175 *
2176 * Parsing functions for the AMD IOMMU specific kernel command line
2177 * options.
2178 *
2179 ****************************************************************************/
2180
Joerg Roedelfefda112009-05-20 12:21:42 +02002181static int __init parse_amd_iommu_dump(char *str)
2182{
2183 amd_iommu_dump = true;
2184
2185 return 1;
2186}
2187
Joerg Roedel918ad6c2008-06-26 21:27:52 +02002188static int __init parse_amd_iommu_options(char *str)
2189{
2190 for (; *str; ++str) {
Joerg Roedel695b5672008-11-17 15:16:43 +01002191 if (strncmp(str, "fullflush", 9) == 0)
FUJITA Tomonoriafa9fdc2008-09-20 01:23:30 +09002192 amd_iommu_unmap_flush = true;
Joerg Roedela5235722010-05-11 17:12:33 +02002193 if (strncmp(str, "off", 3) == 0)
2194 amd_iommu_disabled = true;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002195 if (strncmp(str, "force_isolation", 15) == 0)
2196 amd_iommu_force_isolation = true;
Joerg Roedel918ad6c2008-06-26 21:27:52 +02002197 }
2198
2199 return 1;
2200}
2201
Joerg Roedel440e89982013-04-09 16:35:28 +02002202static int __init parse_ivrs_ioapic(char *str)
2203{
2204 unsigned int bus, dev, fn;
2205 int ret, id, i;
2206 u16 devid;
2207
2208 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2209
2210 if (ret != 4) {
2211 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2212 return 1;
2213 }
2214
2215 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2216 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2217 str);
2218 return 1;
2219 }
2220
2221 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2222
Joerg Roedeldfbb6d42013-04-09 19:06:18 +02002223 cmdline_maps = true;
Joerg Roedel440e89982013-04-09 16:35:28 +02002224 i = early_ioapic_map_size++;
2225 early_ioapic_map[i].id = id;
2226 early_ioapic_map[i].devid = devid;
2227 early_ioapic_map[i].cmd_line = true;
2228
2229 return 1;
2230}
2231
2232static int __init parse_ivrs_hpet(char *str)
2233{
2234 unsigned int bus, dev, fn;
2235 int ret, id, i;
2236 u16 devid;
2237
2238 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2239
2240 if (ret != 4) {
2241 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2242 return 1;
2243 }
2244
2245 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2246 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2247 str);
2248 return 1;
2249 }
2250
2251 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2252
Joerg Roedeldfbb6d42013-04-09 19:06:18 +02002253 cmdline_maps = true;
Joerg Roedel440e89982013-04-09 16:35:28 +02002254 i = early_hpet_map_size++;
2255 early_hpet_map[i].id = id;
2256 early_hpet_map[i].devid = devid;
2257 early_hpet_map[i].cmd_line = true;
2258
2259 return 1;
2260}
2261
2262__setup("amd_iommu_dump", parse_amd_iommu_dump);
2263__setup("amd_iommu=", parse_amd_iommu_options);
2264__setup("ivrs_ioapic", parse_ivrs_ioapic);
2265__setup("ivrs_hpet", parse_ivrs_hpet);
Konrad Rzeszutek Wilk22e6daf2010-08-26 13:58:03 -04002266
2267IOMMU_INIT_FINISH(amd_iommu_detect,
2268 gart_iommu_hole_init,
Joerg Roedel98f1ad22012-07-06 13:28:37 +02002269 NULL,
2270 NULL);
Joerg Roedel400a28a2011-11-28 15:11:02 +01002271
2272bool amd_iommu_v2_supported(void)
2273{
2274 return amd_iommu_v2_present;
2275}
2276EXPORT_SYMBOL(amd_iommu_v2_supported);
Steven L Kinney30861dd2013-06-05 16:11:48 -05002277
2278/****************************************************************************
2279 *
2280 * IOMMU EFR Performance Counter support functionality. This code allows
2281 * access to the IOMMU PC functionality.
2282 *
2283 ****************************************************************************/
2284
2285u8 amd_iommu_pc_get_max_banks(u16 devid)
2286{
2287 struct amd_iommu *iommu;
2288 u8 ret = 0;
2289
2290 /* locate the iommu governing the devid */
2291 iommu = amd_iommu_rlookup_table[devid];
2292 if (iommu)
2293 ret = iommu->max_banks;
2294
2295 return ret;
2296}
2297EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2298
2299bool amd_iommu_pc_supported(void)
2300{
2301 return amd_iommu_pc_present;
2302}
2303EXPORT_SYMBOL(amd_iommu_pc_supported);
2304
2305u8 amd_iommu_pc_get_max_counters(u16 devid)
2306{
2307 struct amd_iommu *iommu;
2308 u8 ret = 0;
2309
2310 /* locate the iommu governing the devid */
2311 iommu = amd_iommu_rlookup_table[devid];
2312 if (iommu)
2313 ret = iommu->max_counters;
2314
2315 return ret;
2316}
2317EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2318
Suravee Suthikulpanit38e45d02016-02-23 13:03:30 +01002319static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
2320 u8 bank, u8 cntr, u8 fxn,
Steven L Kinney30861dd2013-06-05 16:11:48 -05002321 u64 *value, bool is_write)
2322{
Steven L Kinney30861dd2013-06-05 16:11:48 -05002323 u32 offset;
2324 u32 max_offset_lim;
2325
Steven L Kinney30861dd2013-06-05 16:11:48 -05002326 /* Check for valid iommu and pc register indexing */
Suravee Suthikulpanit38e45d02016-02-23 13:03:30 +01002327 if (WARN_ON((fxn > 0x28) || (fxn & 7)))
Steven L Kinney30861dd2013-06-05 16:11:48 -05002328 return -ENODEV;
2329
2330 offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
2331
2332 /* Limit the offset to the hw defined mmio region aperture */
2333 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
2334 (iommu->max_counters << 8) | 0x28);
2335 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2336 (offset > max_offset_lim))
2337 return -EINVAL;
2338
2339 if (is_write) {
2340 writel((u32)*value, iommu->mmio_base + offset);
2341 writel((*value >> 32), iommu->mmio_base + offset + 4);
2342 } else {
2343 *value = readl(iommu->mmio_base + offset + 4);
2344 *value <<= 32;
2345 *value = readl(iommu->mmio_base + offset);
2346 }
2347
2348 return 0;
2349}
2350EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
Suravee Suthikulpanit38e45d02016-02-23 13:03:30 +01002351
2352int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
2353 u64 *value, bool is_write)
2354{
2355 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2356
2357 /* Make sure the IOMMU PC resource is available */
2358 if (!amd_iommu_pc_present || iommu == NULL)
2359 return -ENODEV;
2360
2361 return iommu_pc_get_set_reg_val(iommu, bank, cntr, fxn,
2362 value, is_write);
2363}