blob: 314daf55e7f77791d075065a427b531bb361cce1 [file] [log] [blame]
Kim Phillips9c4a7962008-06-23 19:50:15 +08001/*
2 * Freescale SEC (talitos) device register and descriptor header defines
3 *
Kim Phillipsad42d5f2011-11-21 16:13:27 +08004 * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
Kim Phillips9c4a7962008-06-23 19:50:15 +08005 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 */
30
Horia Geantad1a0eb92012-07-03 19:16:51 +030031#define TALITOS_TIMEOUT 100000
LEROY Christophe6f65f6a2015-04-17 16:32:15 +020032#define TALITOS1_MAX_DATA_LEN 32768
33#define TALITOS2_MAX_DATA_LEN 65535
Horia Geantad1a0eb92012-07-03 19:16:51 +030034
35#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
36#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
37#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
38
39/* descriptor pointer entry */
40struct talitos_ptr {
LEROY Christophe90490752015-04-17 16:32:01 +020041 union {
42 struct { /* SEC2 format */
43 __be16 len; /* length */
44 u8 j_extent; /* jump to sg link table and/or extent*/
45 u8 eptr; /* extended address */
46 };
47 struct { /* SEC1 format */
48 __be16 res;
49 __be16 len1; /* length */
50 };
51 };
Horia Geantad1a0eb92012-07-03 19:16:51 +030052 __be32 ptr; /* address */
53};
54
55static const struct talitos_ptr zero_entry = {
56 .len = 0,
57 .j_extent = 0,
58 .eptr = 0,
59 .ptr = 0
60};
61
62/* descriptor */
63struct talitos_desc {
64 __be32 hdr; /* header high bits */
LEROY Christophe90490752015-04-17 16:32:01 +020065 union {
66 __be32 hdr_lo; /* header low bits */
67 __be32 hdr1; /* header for SEC1 */
68 };
Horia Geantad1a0eb92012-07-03 19:16:51 +030069 struct talitos_ptr ptr[7]; /* ptr/len pair array */
LEROY Christophe90490752015-04-17 16:32:01 +020070 __be32 next_desc; /* next descriptor (SEC1) */
Horia Geantad1a0eb92012-07-03 19:16:51 +030071};
72
LEROY Christophe7d607c6a2015-04-17 16:32:09 +020073#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32))
74
Horia Geantad1a0eb92012-07-03 19:16:51 +030075/**
76 * talitos_request - descriptor submission request
77 * @desc: descriptor pointer (kernel virtual)
78 * @dma_desc: descriptor's physical bus address
79 * @callback: whom to call when descriptor processing is done
80 * @context: caller context (optional)
81 */
82struct talitos_request {
83 struct talitos_desc *desc;
84 dma_addr_t dma_desc;
85 void (*callback) (struct device *dev, struct talitos_desc *desc,
86 void *context, int error);
87 void *context;
88};
89
90/* per-channel fifo management */
91struct talitos_channel {
92 void __iomem *reg;
93
94 /* request fifo */
95 struct talitos_request *fifo;
96
97 /* number of requests pending in channel h/w fifo */
98 atomic_t submit_count ____cacheline_aligned;
99
100 /* request submission (head) lock */
101 spinlock_t head_lock ____cacheline_aligned;
102 /* index to next free descriptor request */
103 int head;
104
105 /* request release (tail) lock */
106 spinlock_t tail_lock ____cacheline_aligned;
107 /* index to next in-progress/done descriptor request */
108 int tail;
109};
110
111struct talitos_private {
112 struct device *dev;
113 struct platform_device *ofdev;
114 void __iomem *reg;
LEROY Christophe5fa7fa12015-04-17 16:32:11 +0200115 void __iomem *reg_deu;
116 void __iomem *reg_aesu;
117 void __iomem *reg_mdeu;
118 void __iomem *reg_afeu;
119 void __iomem *reg_rngu;
120 void __iomem *reg_pkeu;
121 void __iomem *reg_keu;
122 void __iomem *reg_crcu;
Horia Geantad1a0eb92012-07-03 19:16:51 +0300123 int irq[2];
124
125 /* SEC global registers lock */
126 spinlock_t reg_lock ____cacheline_aligned;
127
128 /* SEC version geometry (from device tree node) */
129 unsigned int num_channels;
130 unsigned int chfifo_len;
131 unsigned int exec_units;
132 unsigned int desc_types;
133
134 /* SEC Compatibility info */
135 unsigned long features;
136
137 /*
138 * length of the request fifo
139 * fifo_len is chfifo_len rounded up to next power of 2
140 * so we can use bitwise ops to wrap
141 */
142 unsigned int fifo_len;
143
144 struct talitos_channel *chan;
145
146 /* next channel to be assigned next incoming descriptor */
147 atomic_t last_chan ____cacheline_aligned;
148
149 /* request callback tasklet */
150 struct tasklet_struct done_task[2];
151
152 /* list of registered algorithms */
153 struct list_head alg_list;
154
155 /* hwrng device */
156 struct hwrng rng;
157};
158
Horia Geanta865d5062012-07-03 19:16:52 +0300159extern int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
160 void (*callback)(struct device *dev,
161 struct talitos_desc *desc,
162 void *context, int error),
163 void *context);
164
Horia Geantad1a0eb92012-07-03 19:16:51 +0300165/* .features flag */
166#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
167#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
168#define TALITOS_FTR_SHA224_HWINIT 0x00000004
169#define TALITOS_FTR_HMAC_OK 0x00000008
LEROY Christophe21590882015-04-17 16:32:05 +0200170#define TALITOS_FTR_SEC1 0x00000010
171
172/*
173 * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are
174 * defined, we check the features which are set according to the device tree.
175 * Otherwise, we answer true or false directly
176 */
177static inline bool has_ftr_sec1(struct talitos_private *priv)
178{
179#if defined(CONFIG_CRYPTO_DEV_TALITOS1) && defined(CONFIG_CRYPTO_DEV_TALITOS2)
180 return priv->features & TALITOS_FTR_SEC1 ? true : false;
181#elif defined(CONFIG_CRYPTO_DEV_TALITOS1)
182 return true;
183#else
184 return false;
185#endif
186}
Horia Geantad1a0eb92012-07-03 19:16:51 +0300187
Kim Phillips9c4a7962008-06-23 19:50:15 +0800188/*
189 * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
190 */
191
LEROY Christophedd3c0982015-04-17 16:32:13 +0200192#define ISR1_FORMAT(x) (((x) << 28) | ((x) << 16))
193#define ISR2_FORMAT(x) (((x) << 4) | (x))
194
Kim Phillips9c4a7962008-06-23 19:50:15 +0800195/* global register offset addresses */
196#define TALITOS_MCR 0x1030 /* master control register */
Kim Phillipsc3e337f2011-11-21 16:13:27 +0800197#define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */
198#define TALITOS_MCR_RCA1 (1 << 14) /* remap channel 1 */
199#define TALITOS_MCR_RCA2 (1 << 13) /* remap channel 2 */
200#define TALITOS_MCR_RCA3 (1 << 12) /* remap channel 3 */
LEROY Christophedd3c0982015-04-17 16:32:13 +0200201#define TALITOS1_MCR_SWR 0x1000000 /* s/w reset */
202#define TALITOS2_MCR_SWR 0x1 /* s/w reset */
Kim Phillipsc3e337f2011-11-21 16:13:27 +0800203#define TALITOS_MCR_LO 0x1034
Kim Phillips9c4a7962008-06-23 19:50:15 +0800204#define TALITOS_IMR 0x1008 /* interrupt mask register */
LEROY Christophedd3c0982015-04-17 16:32:13 +0200205/* enable channel IRQs */
206#define TALITOS1_IMR_INIT ISR1_FORMAT(0xf)
207#define TALITOS1_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */
208/* enable channel IRQs */
209#define TALITOS2_IMR_INIT (ISR2_FORMAT(0xf) | 0x10000)
210#define TALITOS2_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800211#define TALITOS_IMR_LO 0x100C
LEROY Christophedd3c0982015-04-17 16:32:13 +0200212#define TALITOS1_IMR_LO_INIT 0x2000000 /* allow RNGU error IRQs */
213#define TALITOS2_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800214#define TALITOS_ISR 0x1010 /* interrupt status register */
LEROY Christophedd3c0982015-04-17 16:32:13 +0200215#define TALITOS1_ISR_4CHERR ISR1_FORMAT(0xa) /* 4 ch errors mask */
216#define TALITOS1_ISR_4CHDONE ISR1_FORMAT(0x5) /* 4 ch done mask */
217#define TALITOS1_ISR_TEA_ERR 0x00000040
218#define TALITOS2_ISR_4CHERR ISR2_FORMAT(0xa) /* 4 ch errors mask */
219#define TALITOS2_ISR_4CHDONE ISR2_FORMAT(0x5) /* 4 ch done mask */
220#define TALITOS2_ISR_CH_0_2_ERR ISR2_FORMAT(0x2) /* ch 0, 2 err mask */
221#define TALITOS2_ISR_CH_0_2_DONE ISR2_FORMAT(0x1) /* ch 0, 2 done mask */
222#define TALITOS2_ISR_CH_1_3_ERR ISR2_FORMAT(0x8) /* ch 1, 3 err mask */
223#define TALITOS2_ISR_CH_1_3_DONE ISR2_FORMAT(0x4) /* ch 1, 3 done mask */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800224#define TALITOS_ISR_LO 0x1014
225#define TALITOS_ICR 0x1018 /* interrupt clear register */
226#define TALITOS_ICR_LO 0x101C
227
228/* channel register address stride */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800229#define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */
LEROY Christophe5fa7fa12015-04-17 16:32:11 +0200230#define TALITOS1_CH_STRIDE 0x1000
231#define TALITOS2_CH_STRIDE 0x100
Kim Phillips9c4a7962008-06-23 19:50:15 +0800232
233/* channel configuration register */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800234#define TALITOS_CCCR 0x8
LEROY Christophedd3c0982015-04-17 16:32:13 +0200235#define TALITOS2_CCCR_CONT 0x2 /* channel continue on SEC2 */
236#define TALITOS2_CCCR_RESET 0x1 /* channel reset on SEC2 */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800237#define TALITOS_CCCR_LO 0xc
Kim Phillipsfe5720e2008-10-12 20:33:14 +0800238#define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
Kim Phillips81eb0242009-08-13 11:51:51 +1000239#define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800240#define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
241#define TALITOS_CCCR_LO_NT 0x4 /* notification type */
242#define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
LEROY Christophedd3c0982015-04-17 16:32:13 +0200243#define TALITOS1_CCCR_LO_RESET 0x1 /* channel reset on SEC1 */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800244
245/* CCPSR: channel pointer status register */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800246#define TALITOS_CCPSR 0x10
247#define TALITOS_CCPSR_LO 0x14
Kim Phillips9c4a7962008-06-23 19:50:15 +0800248#define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
249#define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
250#define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
251#define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
252#define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
253#define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
254#define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
255#define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
256#define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
257#define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
258#define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
259#define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
260
261/* channel fetch fifo register */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800262#define TALITOS_FF 0x48
263#define TALITOS_FF_LO 0x4c
Kim Phillips9c4a7962008-06-23 19:50:15 +0800264
265/* current descriptor pointer register */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800266#define TALITOS_CDPR 0x40
267#define TALITOS_CDPR_LO 0x44
Kim Phillips9c4a7962008-06-23 19:50:15 +0800268
269/* descriptor buffer register */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800270#define TALITOS_DESCBUF 0x80
271#define TALITOS_DESCBUF_LO 0x84
Kim Phillips9c4a7962008-06-23 19:50:15 +0800272
273/* gather link table */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800274#define TALITOS_GATHER 0xc0
275#define TALITOS_GATHER_LO 0xc4
Kim Phillips9c4a7962008-06-23 19:50:15 +0800276
277/* scatter link table */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800278#define TALITOS_SCATTER 0xe0
279#define TALITOS_SCATTER_LO 0xe4
Kim Phillips9c4a7962008-06-23 19:50:15 +0800280
LEROY Christophe5fa7fa12015-04-17 16:32:11 +0200281/* execution unit registers base */
282#define TALITOS2_DEU 0x2000
283#define TALITOS2_AESU 0x4000
284#define TALITOS2_MDEU 0x6000
285#define TALITOS2_AFEU 0x8000
286#define TALITOS2_RNGU 0xa000
287#define TALITOS2_PKEU 0xc000
288#define TALITOS2_KEU 0xe000
289#define TALITOS2_CRCU 0xf000
290
291#define TALITOS12_AESU 0x4000
292#define TALITOS12_DEU 0x5000
293#define TALITOS12_MDEU 0x6000
294
295#define TALITOS10_AFEU 0x8000
296#define TALITOS10_DEU 0xa000
297#define TALITOS10_MDEU 0xc000
298#define TALITOS10_RNGU 0xe000
299#define TALITOS10_PKEU 0x10000
300#define TALITOS10_AESU 0x12000
301
Kim Phillips9c4a7962008-06-23 19:50:15 +0800302/* execution unit interrupt status registers */
LEROY Christophe5fa7fa12015-04-17 16:32:11 +0200303#define TALITOS_EUDSR 0x10 /* data size */
304#define TALITOS_EUDSR_LO 0x14
305#define TALITOS_EURCR 0x18 /* reset control*/
306#define TALITOS_EURCR_LO 0x1c
307#define TALITOS_EUSR 0x28 /* rng status */
308#define TALITOS_EUSR_LO 0x2c
309#define TALITOS_EUISR 0x30
310#define TALITOS_EUISR_LO 0x34
311#define TALITOS_EUICR 0x38 /* int. control */
312#define TALITOS_EUICR_LO 0x3c
313#define TALITOS_EU_FIFO 0x800 /* output FIFO */
314#define TALITOS_EU_FIFO_LO 0x804 /* output FIFO */
LEROY Christophedd3c0982015-04-17 16:32:13 +0200315/* DES unit */
316#define TALITOS1_DEUICR_KPE 0x00200000 /* Key Parity Error */
LEROY Christophe5fa7fa12015-04-17 16:32:11 +0200317/* message digest unit */
Kim Phillipsfe5720e2008-10-12 20:33:14 +0800318#define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
LEROY Christophe5fa7fa12015-04-17 16:32:11 +0200319/* random number unit */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800320#define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
321#define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800322#define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800323
Lee Nipper497f2e62010-05-19 19:20:36 +1000324#define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
325#define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
326
Kim Phillips9c4a7962008-06-23 19:50:15 +0800327/*
328 * talitos descriptor header (hdr) bits
329 */
330
331/* written back when done */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800332#define DESC_HDR_DONE cpu_to_be32(0xff000000)
333#define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
334#define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
335#define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800336
337/* primary execution unit select */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800338#define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
339#define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
340#define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
341#define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
342#define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
343#define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
344#define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
345#define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
346#define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
347#define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800348
349/* primary execution unit mode (MODE0) and derivatives */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800350#define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
351#define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
352#define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
353#define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
Lee Nipper497f2e62010-05-19 19:20:36 +1000354#define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
Harvey Harrisondad3df22008-11-28 20:49:19 +0800355#define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
356#define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
357#define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
Kim Phillips60f208d2010-05-19 19:21:53 +1000358#define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
Harvey Harrisondad3df22008-11-28 20:49:19 +0800359#define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
360#define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
361#define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
Lee Nipper497f2e62010-05-19 19:20:36 +1000362#define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
363#define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800364#define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
365 DESC_HDR_MODE0_MDEU_HMAC)
366#define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
367 DESC_HDR_MODE0_MDEU_HMAC)
368#define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
369 DESC_HDR_MODE0_MDEU_HMAC)
370
371/* secondary execution unit select (SEL1) */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800372#define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
373#define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
374#define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
375#define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800376
377/* secondary execution unit mode (MODE1) and derivatives */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800378#define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
379#define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
380#define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
381#define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
Kim Phillips60f208d2010-05-19 19:21:53 +1000382#define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
Harvey Harrisondad3df22008-11-28 20:49:19 +0800383#define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
384#define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
385#define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
Lee Nipper497f2e62010-05-19 19:20:36 +1000386#define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
387#define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800388#define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
389 DESC_HDR_MODE1_MDEU_HMAC)
390#define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
391 DESC_HDR_MODE1_MDEU_HMAC)
392#define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
393 DESC_HDR_MODE1_MDEU_HMAC)
Horia Geanta357fb602012-07-03 19:16:53 +0300394#define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
395 DESC_HDR_MODE1_MDEU_HMAC)
396#define DESC_HDR_MODE1_MDEUB_SHA384_HMAC (DESC_HDR_MODE1_MDEUB_SHA384 | \
397 DESC_HDR_MODE1_MDEU_HMAC)
398#define DESC_HDR_MODE1_MDEUB_SHA512_HMAC (DESC_HDR_MODE1_MDEUB_SHA512 | \
399 DESC_HDR_MODE1_MDEU_HMAC)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800400
401/* direction of overall data flow (DIR) */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800402#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800403
404/* request done notification (DN) */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800405#define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800406
407/* descriptor types */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800408#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
409#define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
410#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
411#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800412
413/* link table extent field bits */
414#define DESC_PTR_LNKTBL_JUMP 0x80
415#define DESC_PTR_LNKTBL_RETURN 0x02
416#define DESC_PTR_LNKTBL_NEXT 0x01