Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 29 | #include <drm/drm_vma_manager.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/i915_drm.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 34 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 36 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include <linux/pci.h> |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 38 | #include <linux/dma-buf.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 39 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
| 42 | bool force); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 43 | static __must_check int |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 44 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 45 | bool readonly); |
| 46 | static __must_check int |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 47 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| 48 | struct i915_address_space *vm, |
| 49 | unsigned alignment, |
| 50 | bool map_and_fenceable, |
| 51 | bool nonblocking); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 52 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 53 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 54 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 55 | struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 56 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 57 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 58 | struct drm_i915_gem_object *obj); |
| 59 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 60 | struct drm_i915_fence_reg *fence, |
| 61 | bool enable); |
| 62 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 63 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 64 | struct shrink_control *sc); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 65 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
| 66 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 67 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 68 | |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 69 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
| 70 | enum i915_cache_level level) |
| 71 | { |
| 72 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
| 73 | } |
| 74 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 75 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
| 76 | { |
| 77 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
| 78 | return true; |
| 79 | |
| 80 | return obj->pin_display; |
| 81 | } |
| 82 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 83 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 84 | { |
| 85 | if (obj->tiling_mode) |
| 86 | i915_gem_release_mmap(obj); |
| 87 | |
| 88 | /* As we do not have an associated fence register, we will force |
| 89 | * a tiling change if we ever need to acquire one. |
| 90 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 91 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 92 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 93 | } |
| 94 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 95 | /* some bookkeeping */ |
| 96 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 97 | size_t size) |
| 98 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 99 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 100 | dev_priv->mm.object_count++; |
| 101 | dev_priv->mm.object_memory += size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 102 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 106 | size_t size) |
| 107 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 108 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 109 | dev_priv->mm.object_count--; |
| 110 | dev_priv->mm.object_memory -= size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 111 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 112 | } |
| 113 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 114 | static int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 115 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 116 | { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 117 | int ret; |
| 118 | |
Daniel Vetter | 7abb690 | 2013-05-24 21:29:32 +0200 | [diff] [blame] | 119 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
| 120 | i915_terminally_wedged(error)) |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 121 | if (EXIT_COND) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 122 | return 0; |
| 123 | |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 124 | /* |
| 125 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 126 | * userspace. If it takes that long something really bad is going on and |
| 127 | * we should simply try to bail out and fail as gracefully as possible. |
| 128 | */ |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 129 | ret = wait_event_interruptible_timeout(error->reset_queue, |
| 130 | EXIT_COND, |
| 131 | 10*HZ); |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 132 | if (ret == 0) { |
| 133 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 134 | return -EIO; |
| 135 | } else if (ret < 0) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 136 | return ret; |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 137 | } |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 138 | #undef EXIT_COND |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 139 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 140 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 141 | } |
| 142 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 143 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 144 | { |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 145 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 146 | int ret; |
| 147 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 148 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 149 | if (ret) |
| 150 | return ret; |
| 151 | |
| 152 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 153 | if (ret) |
| 154 | return ret; |
| 155 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 156 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 157 | return 0; |
| 158 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 159 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 160 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 161 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 162 | { |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 163 | return i915_gem_obj_bound_any(obj) && !obj->active; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 164 | } |
| 165 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 166 | int |
| 167 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 168 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 169 | { |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 170 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 171 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 172 | |
Daniel Vetter | 7bb6fb8 | 2012-04-24 08:22:52 +0200 | [diff] [blame] | 173 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 174 | return -ENODEV; |
| 175 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 176 | if (args->gtt_start >= args->gtt_end || |
| 177 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 178 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 179 | |
Daniel Vetter | f534bc0 | 2012-03-26 22:37:04 +0200 | [diff] [blame] | 180 | /* GEM with user mode setting was never supported on ilk and later. */ |
| 181 | if (INTEL_INFO(dev)->gen >= 5) |
| 182 | return -ENODEV; |
| 183 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 184 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 185 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
| 186 | args->gtt_end); |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 187 | dev_priv->gtt.mappable_end = args->gtt_end; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 188 | mutex_unlock(&dev->struct_mutex); |
| 189 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 190 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 191 | } |
| 192 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 193 | int |
| 194 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 195 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 196 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 197 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 198 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 199 | struct drm_i915_gem_object *obj; |
| 200 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 201 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 202 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 203 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 204 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 205 | if (obj->pin_count) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 206 | pinned += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 207 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 208 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 209 | args->aper_size = dev_priv->gtt.base.total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 210 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 211 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 212 | return 0; |
| 213 | } |
| 214 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 215 | void *i915_gem_object_alloc(struct drm_device *dev) |
| 216 | { |
| 217 | struct drm_i915_private *dev_priv = dev->dev_private; |
Joe Perches | fac15c1 | 2013-08-29 13:11:07 -0700 | [diff] [blame] | 218 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 219 | } |
| 220 | |
| 221 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
| 222 | { |
| 223 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 224 | kmem_cache_free(dev_priv->slab, obj); |
| 225 | } |
| 226 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 227 | static int |
| 228 | i915_gem_create(struct drm_file *file, |
| 229 | struct drm_device *dev, |
| 230 | uint64_t size, |
| 231 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 232 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 233 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 234 | int ret; |
| 235 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 236 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 237 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 238 | if (size == 0) |
| 239 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 240 | |
| 241 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 242 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 243 | if (obj == NULL) |
| 244 | return -ENOMEM; |
| 245 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 246 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 247 | /* drop reference from allocate - handle holds it now */ |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 248 | drm_gem_object_unreference_unlocked(&obj->base); |
| 249 | if (ret) |
| 250 | return ret; |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 251 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 252 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 253 | return 0; |
| 254 | } |
| 255 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 256 | int |
| 257 | i915_gem_dumb_create(struct drm_file *file, |
| 258 | struct drm_device *dev, |
| 259 | struct drm_mode_create_dumb *args) |
| 260 | { |
| 261 | /* have to work out size/pitch and return them */ |
Chris Wilson | ed0291f | 2011-03-19 08:21:45 +0000 | [diff] [blame] | 262 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 263 | args->size = args->pitch * args->height; |
| 264 | return i915_gem_create(file, dev, |
| 265 | args->size, &args->handle); |
| 266 | } |
| 267 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 268 | /** |
| 269 | * Creates a new mm object and returns a handle to it. |
| 270 | */ |
| 271 | int |
| 272 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 273 | struct drm_file *file) |
| 274 | { |
| 275 | struct drm_i915_gem_create *args = data; |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 276 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 277 | return i915_gem_create(file, dev, |
| 278 | args->size, &args->handle); |
| 279 | } |
| 280 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 281 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 282 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 283 | const char *gpu_vaddr, int gpu_offset, |
| 284 | int length) |
| 285 | { |
| 286 | int ret, cpu_offset = 0; |
| 287 | |
| 288 | while (length > 0) { |
| 289 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 290 | int this_length = min(cacheline_end - gpu_offset, length); |
| 291 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 292 | |
| 293 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 294 | gpu_vaddr + swizzled_gpu_offset, |
| 295 | this_length); |
| 296 | if (ret) |
| 297 | return ret + length; |
| 298 | |
| 299 | cpu_offset += this_length; |
| 300 | gpu_offset += this_length; |
| 301 | length -= this_length; |
| 302 | } |
| 303 | |
| 304 | return 0; |
| 305 | } |
| 306 | |
| 307 | static inline int |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 308 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 309 | const char __user *cpu_vaddr, |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 310 | int length) |
| 311 | { |
| 312 | int ret, cpu_offset = 0; |
| 313 | |
| 314 | while (length > 0) { |
| 315 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 316 | int this_length = min(cacheline_end - gpu_offset, length); |
| 317 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 318 | |
| 319 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 320 | cpu_vaddr + cpu_offset, |
| 321 | this_length); |
| 322 | if (ret) |
| 323 | return ret + length; |
| 324 | |
| 325 | cpu_offset += this_length; |
| 326 | gpu_offset += this_length; |
| 327 | length -= this_length; |
| 328 | } |
| 329 | |
| 330 | return 0; |
| 331 | } |
| 332 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 333 | /* Per-page copy function for the shmem pread fastpath. |
| 334 | * Flushes invalid cachelines before reading the target if |
| 335 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 336 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 337 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 338 | char __user *user_data, |
| 339 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 340 | { |
| 341 | char *vaddr; |
| 342 | int ret; |
| 343 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 344 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 345 | return -EINVAL; |
| 346 | |
| 347 | vaddr = kmap_atomic(page); |
| 348 | if (needs_clflush) |
| 349 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 350 | page_length); |
| 351 | ret = __copy_to_user_inatomic(user_data, |
| 352 | vaddr + shmem_page_offset, |
| 353 | page_length); |
| 354 | kunmap_atomic(vaddr); |
| 355 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 356 | return ret ? -EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 357 | } |
| 358 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 359 | static void |
| 360 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 361 | bool swizzled) |
| 362 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 363 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 364 | unsigned long start = (unsigned long) addr; |
| 365 | unsigned long end = (unsigned long) addr + length; |
| 366 | |
| 367 | /* For swizzling simply ensure that we always flush both |
| 368 | * channels. Lame, but simple and it works. Swizzled |
| 369 | * pwrite/pread is far from a hotpath - current userspace |
| 370 | * doesn't use it at all. */ |
| 371 | start = round_down(start, 128); |
| 372 | end = round_up(end, 128); |
| 373 | |
| 374 | drm_clflush_virt_range((void *)start, end - start); |
| 375 | } else { |
| 376 | drm_clflush_virt_range(addr, length); |
| 377 | } |
| 378 | |
| 379 | } |
| 380 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 381 | /* Only difference to the fast-path function is that this can handle bit17 |
| 382 | * and uses non-atomic copy and kmap functions. */ |
| 383 | static int |
| 384 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 385 | char __user *user_data, |
| 386 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 387 | { |
| 388 | char *vaddr; |
| 389 | int ret; |
| 390 | |
| 391 | vaddr = kmap(page); |
| 392 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 393 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 394 | page_length, |
| 395 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 396 | |
| 397 | if (page_do_bit17_swizzling) |
| 398 | ret = __copy_to_user_swizzled(user_data, |
| 399 | vaddr, shmem_page_offset, |
| 400 | page_length); |
| 401 | else |
| 402 | ret = __copy_to_user(user_data, |
| 403 | vaddr + shmem_page_offset, |
| 404 | page_length); |
| 405 | kunmap(page); |
| 406 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 407 | return ret ? - EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 408 | } |
| 409 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 410 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 411 | i915_gem_shmem_pread(struct drm_device *dev, |
| 412 | struct drm_i915_gem_object *obj, |
| 413 | struct drm_i915_gem_pread *args, |
| 414 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 415 | { |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 416 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 417 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 418 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 419 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 420 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 421 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 422 | int needs_clflush = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 423 | struct sg_page_iter sg_iter; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 424 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 425 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 426 | remain = args->size; |
| 427 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 428 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 429 | |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 430 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 431 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 432 | * read domain and manually flush cachelines (if required). This |
| 433 | * optimizes for the case when the gpu will dirty the data |
| 434 | * anyway again before the next pread happens. */ |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 435 | needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level); |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 436 | ret = i915_gem_object_wait_rendering(obj, true); |
| 437 | if (ret) |
| 438 | return ret; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 439 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 440 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 441 | ret = i915_gem_object_get_pages(obj); |
| 442 | if (ret) |
| 443 | return ret; |
| 444 | |
| 445 | i915_gem_object_pin_pages(obj); |
| 446 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 447 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 448 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 449 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 450 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 451 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 452 | |
| 453 | if (remain <= 0) |
| 454 | break; |
| 455 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 456 | /* Operation in this page |
| 457 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 458 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 459 | * page_length = bytes to copy for this page |
| 460 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 461 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 462 | page_length = remain; |
| 463 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 464 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 465 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 466 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 467 | (page_to_phys(page) & (1 << 17)) != 0; |
| 468 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 469 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 470 | user_data, page_do_bit17_swizzling, |
| 471 | needs_clflush); |
| 472 | if (ret == 0) |
| 473 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 474 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 475 | mutex_unlock(&dev->struct_mutex); |
| 476 | |
Xiong Zhang | 0b74b50 | 2013-07-19 13:51:24 +0800 | [diff] [blame] | 477 | if (likely(!i915_prefault_disable) && !prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 478 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 479 | /* Userspace is tricking us, but we've already clobbered |
| 480 | * its pages with the prefault and promised to write the |
| 481 | * data up to the first fault. Hence ignore any errors |
| 482 | * and just continue. */ |
| 483 | (void)ret; |
| 484 | prefaulted = 1; |
| 485 | } |
| 486 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 487 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 488 | user_data, page_do_bit17_swizzling, |
| 489 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 490 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 491 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 492 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 493 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 494 | mark_page_accessed(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 495 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 496 | if (ret) |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 497 | goto out; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 498 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 499 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 500 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 501 | offset += page_length; |
| 502 | } |
| 503 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 504 | out: |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 505 | i915_gem_object_unpin_pages(obj); |
| 506 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 507 | return ret; |
| 508 | } |
| 509 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 510 | /** |
| 511 | * Reads data from the object referenced by handle. |
| 512 | * |
| 513 | * On error, the contents of *data are undefined. |
| 514 | */ |
| 515 | int |
| 516 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 517 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 518 | { |
| 519 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 520 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 521 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 522 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 523 | if (args->size == 0) |
| 524 | return 0; |
| 525 | |
| 526 | if (!access_ok(VERIFY_WRITE, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 527 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 528 | args->size)) |
| 529 | return -EFAULT; |
| 530 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 531 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 532 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 533 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 534 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 535 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 536 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 537 | ret = -ENOENT; |
| 538 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 539 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 540 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 541 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 542 | if (args->offset > obj->base.size || |
| 543 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 544 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 545 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 546 | } |
| 547 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 548 | /* prime objects have no backing filp to GEM pread/pwrite |
| 549 | * pages from. |
| 550 | */ |
| 551 | if (!obj->base.filp) { |
| 552 | ret = -EINVAL; |
| 553 | goto out; |
| 554 | } |
| 555 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 556 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 557 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 558 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 559 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 560 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 561 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 562 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 563 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 564 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 565 | } |
| 566 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 567 | /* This is the fast write path which cannot handle |
| 568 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 569 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 570 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 571 | static inline int |
| 572 | fast_user_write(struct io_mapping *mapping, |
| 573 | loff_t page_base, int page_offset, |
| 574 | char __user *user_data, |
| 575 | int length) |
| 576 | { |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 577 | void __iomem *vaddr_atomic; |
| 578 | void *vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 579 | unsigned long unwritten; |
| 580 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 581 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 582 | /* We can use the cpu mem copy function because this is X86. */ |
| 583 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 584 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 585 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 586 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 587 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 588 | } |
| 589 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 590 | /** |
| 591 | * This is the fast pwrite path, where we copy the data directly from the |
| 592 | * user into the GTT, uncached. |
| 593 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 594 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 595 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 596 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 597 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 598 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 599 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 600 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 601 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 602 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 603 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 604 | int page_offset, page_length, ret; |
| 605 | |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 606 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 607 | if (ret) |
| 608 | goto out; |
| 609 | |
| 610 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 611 | if (ret) |
| 612 | goto out_unpin; |
| 613 | |
| 614 | ret = i915_gem_object_put_fence(obj); |
| 615 | if (ret) |
| 616 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 617 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 618 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 619 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 620 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 621 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 622 | |
| 623 | while (remain > 0) { |
| 624 | /* Operation in this page |
| 625 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 626 | * page_base = page offset within aperture |
| 627 | * page_offset = offset within page |
| 628 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 629 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 630 | page_base = offset & PAGE_MASK; |
| 631 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 632 | page_length = remain; |
| 633 | if ((page_offset + remain) > PAGE_SIZE) |
| 634 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 635 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 636 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 637 | * source page isn't available. Return the error and we'll |
| 638 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 639 | */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 640 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 641 | page_offset, user_data, page_length)) { |
| 642 | ret = -EFAULT; |
| 643 | goto out_unpin; |
| 644 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 645 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 646 | remain -= page_length; |
| 647 | user_data += page_length; |
| 648 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 649 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 650 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 651 | out_unpin: |
| 652 | i915_gem_object_unpin(obj); |
| 653 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 654 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 655 | } |
| 656 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 657 | /* Per-page copy function for the shmem pwrite fastpath. |
| 658 | * Flushes invalid cachelines before writing to the target if |
| 659 | * needs_clflush_before is set and flushes out any written cachelines after |
| 660 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 661 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 662 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 663 | char __user *user_data, |
| 664 | bool page_do_bit17_swizzling, |
| 665 | bool needs_clflush_before, |
| 666 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 667 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 668 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 669 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 670 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 671 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 672 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 673 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 674 | vaddr = kmap_atomic(page); |
| 675 | if (needs_clflush_before) |
| 676 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 677 | page_length); |
| 678 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, |
| 679 | user_data, |
| 680 | page_length); |
| 681 | if (needs_clflush_after) |
| 682 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 683 | page_length); |
| 684 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 685 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 686 | return ret ? -EFAULT : 0; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 687 | } |
| 688 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 689 | /* Only difference to the fast-path function is that this can handle bit17 |
| 690 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 691 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 692 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 693 | char __user *user_data, |
| 694 | bool page_do_bit17_swizzling, |
| 695 | bool needs_clflush_before, |
| 696 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 697 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 698 | char *vaddr; |
| 699 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 700 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 701 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 702 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 703 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 704 | page_length, |
| 705 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 706 | if (page_do_bit17_swizzling) |
| 707 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 708 | user_data, |
| 709 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 710 | else |
| 711 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 712 | user_data, |
| 713 | page_length); |
| 714 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 715 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 716 | page_length, |
| 717 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 718 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 719 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 720 | return ret ? -EFAULT : 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 721 | } |
| 722 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 723 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 724 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 725 | struct drm_i915_gem_object *obj, |
| 726 | struct drm_i915_gem_pwrite *args, |
| 727 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 728 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 729 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 730 | loff_t offset; |
| 731 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 732 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 733 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 734 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 735 | int needs_clflush_after = 0; |
| 736 | int needs_clflush_before = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 737 | struct sg_page_iter sg_iter; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 738 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 739 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 740 | remain = args->size; |
| 741 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 742 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 743 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 744 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 745 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 746 | * write domain and manually flush cachelines (if required). This |
| 747 | * optimizes for the case when the gpu will use the data |
| 748 | * right away and we therefore have to clflush anyway. */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 749 | needs_clflush_after = cpu_write_needs_clflush(obj); |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 750 | ret = i915_gem_object_wait_rendering(obj, false); |
| 751 | if (ret) |
| 752 | return ret; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 753 | } |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 754 | /* Same trick applies to invalidate partially written cachelines read |
| 755 | * before writing. */ |
| 756 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 757 | needs_clflush_before = |
| 758 | !cpu_cache_is_coherent(dev, obj->cache_level); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 759 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 760 | ret = i915_gem_object_get_pages(obj); |
| 761 | if (ret) |
| 762 | return ret; |
| 763 | |
| 764 | i915_gem_object_pin_pages(obj); |
| 765 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 766 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 767 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 768 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 769 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 770 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 771 | struct page *page = sg_page_iter_page(&sg_iter); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 772 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 773 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 774 | if (remain <= 0) |
| 775 | break; |
| 776 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 777 | /* Operation in this page |
| 778 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 779 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 780 | * page_length = bytes to copy for this page |
| 781 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 782 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 783 | |
| 784 | page_length = remain; |
| 785 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 786 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 787 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 788 | /* If we don't overwrite a cacheline completely we need to be |
| 789 | * careful to have up-to-date data by first clflushing. Don't |
| 790 | * overcomplicate things and flush the entire patch. */ |
| 791 | partial_cacheline_write = needs_clflush_before && |
| 792 | ((shmem_page_offset | page_length) |
| 793 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 794 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 795 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 796 | (page_to_phys(page) & (1 << 17)) != 0; |
| 797 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 798 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 799 | user_data, page_do_bit17_swizzling, |
| 800 | partial_cacheline_write, |
| 801 | needs_clflush_after); |
| 802 | if (ret == 0) |
| 803 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 804 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 805 | hit_slowpath = 1; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 806 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 807 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 808 | user_data, page_do_bit17_swizzling, |
| 809 | partial_cacheline_write, |
| 810 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 811 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 812 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 813 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 814 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 815 | set_page_dirty(page); |
| 816 | mark_page_accessed(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 817 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 818 | if (ret) |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 819 | goto out; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 820 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 821 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 822 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 823 | offset += page_length; |
| 824 | } |
| 825 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 826 | out: |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 827 | i915_gem_object_unpin_pages(obj); |
| 828 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 829 | if (hit_slowpath) { |
Daniel Vetter | 8dcf015 | 2012-11-15 16:53:58 +0100 | [diff] [blame] | 830 | /* |
| 831 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
| 832 | * cachelines in-line while writing and the object moved |
| 833 | * out of the cpu write domain while we've dropped the lock. |
| 834 | */ |
| 835 | if (!needs_clflush_after && |
| 836 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 837 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
| 838 | i915_gem_chipset_flush(dev); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 839 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 840 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 841 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 842 | if (needs_clflush_after) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 843 | i915_gem_chipset_flush(dev); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 844 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 845 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 846 | } |
| 847 | |
| 848 | /** |
| 849 | * Writes data to the object referenced by handle. |
| 850 | * |
| 851 | * On error, the contents of the buffer that were to be modified are undefined. |
| 852 | */ |
| 853 | int |
| 854 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 855 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 856 | { |
| 857 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 858 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 859 | int ret; |
| 860 | |
| 861 | if (args->size == 0) |
| 862 | return 0; |
| 863 | |
| 864 | if (!access_ok(VERIFY_READ, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 865 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 866 | args->size)) |
| 867 | return -EFAULT; |
| 868 | |
Xiong Zhang | 0b74b50 | 2013-07-19 13:51:24 +0800 | [diff] [blame] | 869 | if (likely(!i915_prefault_disable)) { |
| 870 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
| 871 | args->size); |
| 872 | if (ret) |
| 873 | return -EFAULT; |
| 874 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 875 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 876 | ret = i915_mutex_lock_interruptible(dev); |
| 877 | if (ret) |
| 878 | return ret; |
| 879 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 880 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 881 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 882 | ret = -ENOENT; |
| 883 | goto unlock; |
| 884 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 885 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 886 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 887 | if (args->offset > obj->base.size || |
| 888 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 889 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 890 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 891 | } |
| 892 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 893 | /* prime objects have no backing filp to GEM pread/pwrite |
| 894 | * pages from. |
| 895 | */ |
| 896 | if (!obj->base.filp) { |
| 897 | ret = -EINVAL; |
| 898 | goto out; |
| 899 | } |
| 900 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 901 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 902 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 903 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 904 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 905 | * it would end up going through the fenced access, and we'll get |
| 906 | * different detiling behavior between reading and writing. |
| 907 | * pread/pwrite currently are reading and writing from the CPU |
| 908 | * perspective, requiring manual detiling by the client. |
| 909 | */ |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 910 | if (obj->phys_obj) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 911 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 912 | goto out; |
| 913 | } |
| 914 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 915 | if (obj->tiling_mode == I915_TILING_NONE && |
| 916 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 917 | cpu_write_needs_clflush(obj)) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 918 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 919 | /* Note that the gtt paths might fail with non-page-backed user |
| 920 | * pointers (e.g. gtt mappings when moving data between |
| 921 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 922 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 923 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 924 | if (ret == -EFAULT || ret == -ENOSPC) |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 925 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 926 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 927 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 928 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 929 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 930 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 931 | return ret; |
| 932 | } |
| 933 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 934 | int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 935 | i915_gem_check_wedge(struct i915_gpu_error *error, |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 936 | bool interruptible) |
| 937 | { |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 938 | if (i915_reset_in_progress(error)) { |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 939 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 940 | * -EIO unconditionally for these. */ |
| 941 | if (!interruptible) |
| 942 | return -EIO; |
| 943 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 944 | /* Recovery complete, but the reset failed ... */ |
| 945 | if (i915_terminally_wedged(error)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 946 | return -EIO; |
| 947 | |
| 948 | return -EAGAIN; |
| 949 | } |
| 950 | |
| 951 | return 0; |
| 952 | } |
| 953 | |
| 954 | /* |
| 955 | * Compare seqno against outstanding lazy request. Emit a request if they are |
| 956 | * equal. |
| 957 | */ |
| 958 | static int |
| 959 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) |
| 960 | { |
| 961 | int ret; |
| 962 | |
| 963 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
| 964 | |
| 965 | ret = 0; |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 966 | if (seqno == ring->outstanding_lazy_seqno) |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 967 | ret = i915_add_request(ring, NULL); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 968 | |
| 969 | return ret; |
| 970 | } |
| 971 | |
| 972 | /** |
| 973 | * __wait_seqno - wait until execution of seqno has finished |
| 974 | * @ring: the ring expected to report seqno |
| 975 | * @seqno: duh! |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 976 | * @reset_counter: reset sequence associated with the given seqno |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 977 | * @interruptible: do an interruptible wait (normally yes) |
| 978 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 979 | * |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 980 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
| 981 | * values have been read by the caller in an smp safe manner. Where read-side |
| 982 | * locks are involved, it is sufficient to read the reset_counter before |
| 983 | * unlocking the lock that protects the seqno. For lockless tricks, the |
| 984 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
| 985 | * inserted. |
| 986 | * |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 987 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
| 988 | * errno with remaining time filled in timeout argument. |
| 989 | */ |
| 990 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 991 | unsigned reset_counter, |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 992 | bool interruptible, struct timespec *timeout) |
| 993 | { |
| 994 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 995 | struct timespec before, now, wait_time={1,0}; |
| 996 | unsigned long timeout_jiffies; |
| 997 | long end; |
| 998 | bool wait_forever = true; |
| 999 | int ret; |
| 1000 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1001 | WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n"); |
| 1002 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1003 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
| 1004 | return 0; |
| 1005 | |
| 1006 | trace_i915_gem_request_wait_begin(ring, seqno); |
| 1007 | |
| 1008 | if (timeout != NULL) { |
| 1009 | wait_time = *timeout; |
| 1010 | wait_forever = false; |
| 1011 | } |
| 1012 | |
Imre Deak | e054cc3 | 2013-05-21 20:03:19 +0300 | [diff] [blame] | 1013 | timeout_jiffies = timespec_to_jiffies_timeout(&wait_time); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1014 | |
| 1015 | if (WARN_ON(!ring->irq_get(ring))) |
| 1016 | return -ENODEV; |
| 1017 | |
| 1018 | /* Record current time in case interrupted by signal, or wedged * */ |
| 1019 | getrawmonotonic(&before); |
| 1020 | |
| 1021 | #define EXIT_COND \ |
| 1022 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1023 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
| 1024 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1025 | do { |
| 1026 | if (interruptible) |
| 1027 | end = wait_event_interruptible_timeout(ring->irq_queue, |
| 1028 | EXIT_COND, |
| 1029 | timeout_jiffies); |
| 1030 | else |
| 1031 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, |
| 1032 | timeout_jiffies); |
| 1033 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1034 | /* We need to check whether any gpu reset happened in between |
| 1035 | * the caller grabbing the seqno and now ... */ |
| 1036 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
| 1037 | end = -EAGAIN; |
| 1038 | |
| 1039 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely |
| 1040 | * gone. */ |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1041 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1042 | if (ret) |
| 1043 | end = ret; |
| 1044 | } while (end == 0 && wait_forever); |
| 1045 | |
| 1046 | getrawmonotonic(&now); |
| 1047 | |
| 1048 | ring->irq_put(ring); |
| 1049 | trace_i915_gem_request_wait_end(ring, seqno); |
| 1050 | #undef EXIT_COND |
| 1051 | |
| 1052 | if (timeout) { |
| 1053 | struct timespec sleep_time = timespec_sub(now, before); |
| 1054 | *timeout = timespec_sub(*timeout, sleep_time); |
Chris Wilson | 4f42f4e | 2013-04-26 16:22:46 +0300 | [diff] [blame] | 1055 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
| 1056 | set_normalized_timespec(timeout, 0, 0); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1057 | } |
| 1058 | |
| 1059 | switch (end) { |
| 1060 | case -EIO: |
| 1061 | case -EAGAIN: /* Wedged */ |
| 1062 | case -ERESTARTSYS: /* Signal */ |
| 1063 | return (int)end; |
| 1064 | case 0: /* Timeout */ |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1065 | return -ETIME; |
| 1066 | default: /* Completed */ |
| 1067 | WARN_ON(end < 0); /* We're not aware of other errors */ |
| 1068 | return 0; |
| 1069 | } |
| 1070 | } |
| 1071 | |
| 1072 | /** |
| 1073 | * Waits for a sequence number to be signaled, and cleans up the |
| 1074 | * request and object lists appropriately for that event. |
| 1075 | */ |
| 1076 | int |
| 1077 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
| 1078 | { |
| 1079 | struct drm_device *dev = ring->dev; |
| 1080 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1081 | bool interruptible = dev_priv->mm.interruptible; |
| 1082 | int ret; |
| 1083 | |
| 1084 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1085 | BUG_ON(seqno == 0); |
| 1086 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1087 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1088 | if (ret) |
| 1089 | return ret; |
| 1090 | |
| 1091 | ret = i915_gem_check_olr(ring, seqno); |
| 1092 | if (ret) |
| 1093 | return ret; |
| 1094 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1095 | return __wait_seqno(ring, seqno, |
| 1096 | atomic_read(&dev_priv->gpu_error.reset_counter), |
| 1097 | interruptible, NULL); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1098 | } |
| 1099 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1100 | static int |
| 1101 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, |
| 1102 | struct intel_ring_buffer *ring) |
| 1103 | { |
| 1104 | i915_gem_retire_requests_ring(ring); |
| 1105 | |
| 1106 | /* Manually manage the write flush as we may have not yet |
| 1107 | * retired the buffer. |
| 1108 | * |
| 1109 | * Note that the last_write_seqno is always the earlier of |
| 1110 | * the two (read/write) seqno, so if we haved successfully waited, |
| 1111 | * we know we have passed the last write. |
| 1112 | */ |
| 1113 | obj->last_write_seqno = 0; |
| 1114 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 1115 | |
| 1116 | return 0; |
| 1117 | } |
| 1118 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1119 | /** |
| 1120 | * Ensures that all rendering to the object has completed and the object is |
| 1121 | * safe to unbind from the GTT or access from the CPU. |
| 1122 | */ |
| 1123 | static __must_check int |
| 1124 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1125 | bool readonly) |
| 1126 | { |
| 1127 | struct intel_ring_buffer *ring = obj->ring; |
| 1128 | u32 seqno; |
| 1129 | int ret; |
| 1130 | |
| 1131 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1132 | if (seqno == 0) |
| 1133 | return 0; |
| 1134 | |
| 1135 | ret = i915_wait_seqno(ring, seqno); |
| 1136 | if (ret) |
| 1137 | return ret; |
| 1138 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1139 | return i915_gem_object_wait_rendering__tail(obj, ring); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1140 | } |
| 1141 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1142 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1143 | * as the object state may change during this call. |
| 1144 | */ |
| 1145 | static __must_check int |
| 1146 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
| 1147 | bool readonly) |
| 1148 | { |
| 1149 | struct drm_device *dev = obj->base.dev; |
| 1150 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1151 | struct intel_ring_buffer *ring = obj->ring; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1152 | unsigned reset_counter; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1153 | u32 seqno; |
| 1154 | int ret; |
| 1155 | |
| 1156 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1157 | BUG_ON(!dev_priv->mm.interruptible); |
| 1158 | |
| 1159 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1160 | if (seqno == 0) |
| 1161 | return 0; |
| 1162 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1163 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1164 | if (ret) |
| 1165 | return ret; |
| 1166 | |
| 1167 | ret = i915_gem_check_olr(ring, seqno); |
| 1168 | if (ret) |
| 1169 | return ret; |
| 1170 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1171 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1172 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1173 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1174 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1175 | if (ret) |
| 1176 | return ret; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1177 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1178 | return i915_gem_object_wait_rendering__tail(obj, ring); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1179 | } |
| 1180 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1181 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1182 | * Called when user space prepares to use an object with the CPU, either |
| 1183 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1184 | */ |
| 1185 | int |
| 1186 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1187 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1188 | { |
| 1189 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1190 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1191 | uint32_t read_domains = args->read_domains; |
| 1192 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1193 | int ret; |
| 1194 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1195 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1196 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1197 | return -EINVAL; |
| 1198 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1199 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1200 | return -EINVAL; |
| 1201 | |
| 1202 | /* Having something in the write domain implies it's in the read |
| 1203 | * domain, and only that read domain. Enforce that in the request. |
| 1204 | */ |
| 1205 | if (write_domain != 0 && read_domains != write_domain) |
| 1206 | return -EINVAL; |
| 1207 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1208 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1209 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1210 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1211 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1212 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1213 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1214 | ret = -ENOENT; |
| 1215 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1216 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1217 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1218 | /* Try to flush the object off the GPU without holding the lock. |
| 1219 | * We will repeat the flush holding the lock in the normal manner |
| 1220 | * to catch cases where we are gazumped. |
| 1221 | */ |
| 1222 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); |
| 1223 | if (ret) |
| 1224 | goto unref; |
| 1225 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1226 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1227 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1228 | |
| 1229 | /* Silently promote "you're not bound, there was nothing to do" |
| 1230 | * to success, since the client was just asking us to |
| 1231 | * make sure everything was done. |
| 1232 | */ |
| 1233 | if (ret == -EINVAL) |
| 1234 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1235 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1236 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1237 | } |
| 1238 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1239 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1240 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1241 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1242 | mutex_unlock(&dev->struct_mutex); |
| 1243 | return ret; |
| 1244 | } |
| 1245 | |
| 1246 | /** |
| 1247 | * Called when user space has done writes to this buffer |
| 1248 | */ |
| 1249 | int |
| 1250 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1251 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1252 | { |
| 1253 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1254 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1255 | int ret = 0; |
| 1256 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1257 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1258 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1259 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1260 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1261 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1262 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1263 | ret = -ENOENT; |
| 1264 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1265 | } |
| 1266 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1267 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1268 | if (obj->pin_display) |
| 1269 | i915_gem_object_flush_cpu_write_domain(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1270 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1271 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1272 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1273 | mutex_unlock(&dev->struct_mutex); |
| 1274 | return ret; |
| 1275 | } |
| 1276 | |
| 1277 | /** |
| 1278 | * Maps the contents of an object, returning the address it is mapped |
| 1279 | * into. |
| 1280 | * |
| 1281 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1282 | * imply a ref on the object itself. |
| 1283 | */ |
| 1284 | int |
| 1285 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1286 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1287 | { |
| 1288 | struct drm_i915_gem_mmap *args = data; |
| 1289 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1290 | unsigned long addr; |
| 1291 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1292 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1293 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1294 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1295 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1296 | /* prime objects have no backing filp to GEM mmap |
| 1297 | * pages from. |
| 1298 | */ |
| 1299 | if (!obj->filp) { |
| 1300 | drm_gem_object_unreference_unlocked(obj); |
| 1301 | return -EINVAL; |
| 1302 | } |
| 1303 | |
Linus Torvalds | 6be5ceb | 2012-04-20 17:13:58 -0700 | [diff] [blame] | 1304 | addr = vm_mmap(obj->filp, 0, args->size, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1305 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1306 | args->offset); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1307 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1308 | if (IS_ERR((void *)addr)) |
| 1309 | return addr; |
| 1310 | |
| 1311 | args->addr_ptr = (uint64_t) addr; |
| 1312 | |
| 1313 | return 0; |
| 1314 | } |
| 1315 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1316 | /** |
| 1317 | * i915_gem_fault - fault a page into the GTT |
| 1318 | * vma: VMA in question |
| 1319 | * vmf: fault info |
| 1320 | * |
| 1321 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1322 | * from userspace. The fault handler takes care of binding the object to |
| 1323 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1324 | * only if needed based on whether the old reg is still valid or the object |
| 1325 | * is tiled) and inserting a new PTE into the faulting process. |
| 1326 | * |
| 1327 | * Note that the faulting process may involve evicting existing objects |
| 1328 | * from the GTT and/or fence registers to make room. So performance may |
| 1329 | * suffer if the GTT working set is large or there are few fence registers |
| 1330 | * left. |
| 1331 | */ |
| 1332 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1333 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1334 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1335 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1336 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1337 | pgoff_t page_offset; |
| 1338 | unsigned long pfn; |
| 1339 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1340 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1341 | |
| 1342 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1343 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1344 | PAGE_SHIFT; |
| 1345 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1346 | ret = i915_mutex_lock_interruptible(dev); |
| 1347 | if (ret) |
| 1348 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1349 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1350 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1351 | |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1352 | /* Access to snoopable pages through the GTT is incoherent. */ |
| 1353 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { |
| 1354 | ret = -EINVAL; |
| 1355 | goto unlock; |
| 1356 | } |
| 1357 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1358 | /* Now bind it into the GTT if needed */ |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 1359 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1360 | if (ret) |
| 1361 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1362 | |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1363 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1364 | if (ret) |
| 1365 | goto unpin; |
| 1366 | |
| 1367 | ret = i915_gem_object_get_fence(obj); |
| 1368 | if (ret) |
| 1369 | goto unpin; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1370 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1371 | obj->fault_mappable = true; |
| 1372 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1373 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
| 1374 | pfn >>= PAGE_SHIFT; |
| 1375 | pfn += page_offset; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1376 | |
| 1377 | /* Finally, remap it using the new GTT offset */ |
| 1378 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1379 | unpin: |
| 1380 | i915_gem_object_unpin(obj); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1381 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1382 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1383 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1384 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1385 | case -EIO: |
Daniel Vetter | a9340cc | 2012-07-04 22:18:42 +0200 | [diff] [blame] | 1386 | /* If this -EIO is due to a gpu hang, give the reset code a |
| 1387 | * chance to clean up the mess. Otherwise return the proper |
| 1388 | * SIGBUS. */ |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1389 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
Daniel Vetter | a9340cc | 2012-07-04 22:18:42 +0200 | [diff] [blame] | 1390 | return VM_FAULT_SIGBUS; |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1391 | case -EAGAIN: |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1392 | /* Give the error handler a chance to run and move the |
| 1393 | * objects off the GPU active list. Next time we service the |
| 1394 | * fault, we should be able to transition the page into the |
| 1395 | * GTT without touching the GPU (and so avoid further |
| 1396 | * EIO/EGAIN). If the GPU is wedged, then there is no issue |
| 1397 | * with coherency, just lost writes. |
| 1398 | */ |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1399 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1400 | case 0: |
| 1401 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1402 | case -EINTR: |
Dmitry Rogozhkin | e79e0fe | 2012-10-03 17:15:26 +0300 | [diff] [blame] | 1403 | case -EBUSY: |
| 1404 | /* |
| 1405 | * EBUSY is ok: this just means that another thread |
| 1406 | * already did the job. |
| 1407 | */ |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1408 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1409 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1410 | return VM_FAULT_OOM; |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1411 | case -ENOSPC: |
| 1412 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1413 | default: |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1414 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1415 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1416 | } |
| 1417 | } |
| 1418 | |
| 1419 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1420 | * i915_gem_release_mmap - remove physical page mappings |
| 1421 | * @obj: obj in question |
| 1422 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1423 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1424 | * relinquish ownership of the pages back to the system. |
| 1425 | * |
| 1426 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1427 | * object through the GTT and then lose the fence register due to |
| 1428 | * resource pressure. Similarly if the object has been moved out of the |
| 1429 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1430 | * mapping will then trigger a page fault on the next user access, allowing |
| 1431 | * fixup by i915_gem_fault(). |
| 1432 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1433 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1434 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1435 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1436 | if (!obj->fault_mappable) |
| 1437 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1438 | |
David Herrmann | 51335df | 2013-07-24 21:10:03 +0200 | [diff] [blame] | 1439 | drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1440 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1441 | } |
| 1442 | |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 1443 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1444 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1445 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1446 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1447 | |
| 1448 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1449 | tiling_mode == I915_TILING_NONE) |
| 1450 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1451 | |
| 1452 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1453 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1454 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1455 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1456 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1457 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1458 | while (gtt_size < size) |
| 1459 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1460 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1461 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1462 | } |
| 1463 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1464 | /** |
| 1465 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1466 | * @obj: object to check |
| 1467 | * |
| 1468 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1469 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1470 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1471 | uint32_t |
| 1472 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 1473 | int tiling_mode, bool fenced) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1474 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1475 | /* |
| 1476 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1477 | * if a fence register is needed for the object. |
| 1478 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1479 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1480 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1481 | return 4096; |
| 1482 | |
| 1483 | /* |
| 1484 | * Previous chips need to be aligned to the size of the smallest |
| 1485 | * fence register that can contain the object. |
| 1486 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1487 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1488 | } |
| 1489 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1490 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 1491 | { |
| 1492 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1493 | int ret; |
| 1494 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 1495 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1496 | return 0; |
| 1497 | |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1498 | dev_priv->mm.shrinker_no_lock_stealing = true; |
| 1499 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1500 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1501 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1502 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1503 | |
| 1504 | /* Badly fragmented mmap space? The only way we can recover |
| 1505 | * space is by destroying unwanted objects. We can't randomly release |
| 1506 | * mmap_offsets as userspace expects them to be persistent for the |
| 1507 | * lifetime of the objects. The closest we can is to release the |
| 1508 | * offsets on purgeable objects by truncating it and marking it purged, |
| 1509 | * which prevents userspace from ever using that object again. |
| 1510 | */ |
| 1511 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); |
| 1512 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1513 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1514 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1515 | |
| 1516 | i915_gem_shrink_all(dev_priv); |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1517 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1518 | out: |
| 1519 | dev_priv->mm.shrinker_no_lock_stealing = false; |
| 1520 | |
| 1521 | return ret; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1522 | } |
| 1523 | |
| 1524 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 1525 | { |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1526 | drm_gem_free_mmap_offset(&obj->base); |
| 1527 | } |
| 1528 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1529 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1530 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1531 | struct drm_device *dev, |
| 1532 | uint32_t handle, |
| 1533 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1534 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1535 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1536 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1537 | int ret; |
| 1538 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1539 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1540 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1541 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1542 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1543 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1544 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1545 | ret = -ENOENT; |
| 1546 | goto unlock; |
| 1547 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1548 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1549 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1550 | ret = -E2BIG; |
Eric Anholt | ff56b0b | 2011-10-31 23:16:21 -0700 | [diff] [blame] | 1551 | goto out; |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1552 | } |
| 1553 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1554 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1555 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1556 | ret = -EINVAL; |
| 1557 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1558 | } |
| 1559 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1560 | ret = i915_gem_object_create_mmap_offset(obj); |
| 1561 | if (ret) |
| 1562 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1563 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 1564 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1565 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1566 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1567 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1568 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1569 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1570 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1571 | } |
| 1572 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1573 | /** |
| 1574 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1575 | * @dev: DRM device |
| 1576 | * @data: GTT mapping ioctl data |
| 1577 | * @file: GEM object info |
| 1578 | * |
| 1579 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1580 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1581 | * up so we can get faults in the handler above. |
| 1582 | * |
| 1583 | * The fault handler will take care of binding the object into the GTT |
| 1584 | * (since it may have been evicted to make room for something), allocating |
| 1585 | * a fence register, and mapping the appropriate aperture address into |
| 1586 | * userspace. |
| 1587 | */ |
| 1588 | int |
| 1589 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1590 | struct drm_file *file) |
| 1591 | { |
| 1592 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1593 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1594 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1595 | } |
| 1596 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1597 | /* Immediately discard the backing storage */ |
| 1598 | static void |
| 1599 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1600 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1601 | struct inode *inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1602 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1603 | i915_gem_object_free_mmap_offset(obj); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1604 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1605 | if (obj->base.filp == NULL) |
| 1606 | return; |
| 1607 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1608 | /* Our goal here is to return as much of the memory as |
| 1609 | * is possible back to the system as we are called from OOM. |
| 1610 | * To do this we must instruct the shmfs to drop all of its |
| 1611 | * backing pages, *now*. |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1612 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 1613 | inode = file_inode(obj->base.filp); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1614 | shmem_truncate_range(inode, 0, (loff_t)-1); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1615 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1616 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1617 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1618 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1619 | static inline int |
| 1620 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
| 1621 | { |
| 1622 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1623 | } |
| 1624 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1625 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1626 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1627 | { |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1628 | struct sg_page_iter sg_iter; |
| 1629 | int ret; |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1630 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1631 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1632 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1633 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 1634 | if (ret) { |
| 1635 | /* In the event of a disaster, abandon all caches and |
| 1636 | * hope for the best. |
| 1637 | */ |
| 1638 | WARN_ON(ret != -EIO); |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1639 | i915_gem_clflush_object(obj, true); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1640 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 1641 | } |
| 1642 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1643 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1644 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1645 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1646 | if (obj->madv == I915_MADV_DONTNEED) |
| 1647 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1648 | |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1649 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1650 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1651 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1652 | if (obj->dirty) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1653 | set_page_dirty(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1654 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1655 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1656 | mark_page_accessed(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1657 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1658 | page_cache_release(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1659 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1660 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1661 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1662 | sg_free_table(obj->pages); |
| 1663 | kfree(obj->pages); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1664 | } |
| 1665 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1666 | int |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1667 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 1668 | { |
| 1669 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1670 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 1671 | if (obj->pages == NULL) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1672 | return 0; |
| 1673 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1674 | if (obj->pages_pin_count) |
| 1675 | return -EBUSY; |
| 1676 | |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 1677 | BUG_ON(i915_gem_obj_bound_any(obj)); |
Ben Widawsky | 3e12302 | 2013-07-31 17:00:04 -0700 | [diff] [blame] | 1678 | |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 1679 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
| 1680 | * array, hence protect them from being reaped by removing them from gtt |
| 1681 | * lists early. */ |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1682 | list_del(&obj->global_list); |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 1683 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1684 | ops->put_pages(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1685 | obj->pages = NULL; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1686 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1687 | if (i915_gem_object_is_purgeable(obj)) |
| 1688 | i915_gem_object_truncate(obj); |
| 1689 | |
| 1690 | return 0; |
| 1691 | } |
| 1692 | |
| 1693 | static long |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1694 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
| 1695 | bool purgeable_only) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1696 | { |
| 1697 | struct drm_i915_gem_object *obj, *next; |
| 1698 | long count = 0; |
| 1699 | |
| 1700 | list_for_each_entry_safe(obj, next, |
| 1701 | &dev_priv->mm.unbound_list, |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1702 | global_list) { |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1703 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1704 | i915_gem_object_put_pages(obj) == 0) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1705 | count += obj->base.size >> PAGE_SHIFT; |
| 1706 | if (count >= target) |
| 1707 | return count; |
| 1708 | } |
| 1709 | } |
| 1710 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 1711 | list_for_each_entry_safe(obj, next, &dev_priv->mm.bound_list, |
| 1712 | global_list) { |
| 1713 | struct i915_vma *vma, *v; |
Ben Widawsky | 80dcfdb | 2013-07-31 17:00:01 -0700 | [diff] [blame] | 1714 | |
| 1715 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
| 1716 | continue; |
| 1717 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 1718 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
| 1719 | if (i915_vma_unbind(vma)) |
| 1720 | break; |
Ben Widawsky | 80dcfdb | 2013-07-31 17:00:01 -0700 | [diff] [blame] | 1721 | |
| 1722 | if (!i915_gem_object_put_pages(obj)) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1723 | count += obj->base.size >> PAGE_SHIFT; |
| 1724 | if (count >= target) |
| 1725 | return count; |
| 1726 | } |
| 1727 | } |
| 1728 | |
| 1729 | return count; |
| 1730 | } |
| 1731 | |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1732 | static long |
| 1733 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
| 1734 | { |
| 1735 | return __i915_gem_shrink(dev_priv, target, true); |
| 1736 | } |
| 1737 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1738 | static void |
| 1739 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
| 1740 | { |
| 1741 | struct drm_i915_gem_object *obj, *next; |
| 1742 | |
| 1743 | i915_gem_evict_everything(dev_priv->dev); |
| 1744 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1745 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
| 1746 | global_list) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1747 | i915_gem_object_put_pages(obj); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1748 | } |
| 1749 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1750 | static int |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1751 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1752 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1753 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1754 | int page_count, i; |
| 1755 | struct address_space *mapping; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1756 | struct sg_table *st; |
| 1757 | struct scatterlist *sg; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1758 | struct sg_page_iter sg_iter; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1759 | struct page *page; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1760 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1761 | gfp_t gfp; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1762 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1763 | /* Assert that the object is not currently in any GPU domain. As it |
| 1764 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 1765 | * a GPU cache |
| 1766 | */ |
| 1767 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 1768 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 1769 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1770 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 1771 | if (st == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1772 | return -ENOMEM; |
| 1773 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1774 | page_count = obj->base.size / PAGE_SIZE; |
| 1775 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1776 | kfree(st); |
| 1777 | return -ENOMEM; |
| 1778 | } |
| 1779 | |
| 1780 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1781 | * at this point until we release them. |
| 1782 | * |
| 1783 | * Fail silently without starting the shrinker |
| 1784 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 1785 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1786 | gfp = mapping_gfp_mask(mapping); |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 1787 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1788 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1789 | sg = st->sgl; |
| 1790 | st->nents = 0; |
| 1791 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1792 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1793 | if (IS_ERR(page)) { |
| 1794 | i915_gem_purge(dev_priv, page_count); |
| 1795 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1796 | } |
| 1797 | if (IS_ERR(page)) { |
| 1798 | /* We've tried hard to allocate the memory by reaping |
| 1799 | * our own buffer, now let the real VM do its job and |
| 1800 | * go down in flames if truly OOM. |
| 1801 | */ |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 1802 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1803 | gfp |= __GFP_IO | __GFP_WAIT; |
| 1804 | |
| 1805 | i915_gem_shrink_all(dev_priv); |
| 1806 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1807 | if (IS_ERR(page)) |
| 1808 | goto err_pages; |
| 1809 | |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 1810 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1811 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
| 1812 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 1813 | #ifdef CONFIG_SWIOTLB |
| 1814 | if (swiotlb_nr_tbl()) { |
| 1815 | st->nents++; |
| 1816 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 1817 | sg = sg_next(sg); |
| 1818 | continue; |
| 1819 | } |
| 1820 | #endif |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1821 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
| 1822 | if (i) |
| 1823 | sg = sg_next(sg); |
| 1824 | st->nents++; |
| 1825 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 1826 | } else { |
| 1827 | sg->length += PAGE_SIZE; |
| 1828 | } |
| 1829 | last_pfn = page_to_pfn(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1830 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 1831 | #ifdef CONFIG_SWIOTLB |
| 1832 | if (!swiotlb_nr_tbl()) |
| 1833 | #endif |
| 1834 | sg_mark_end(sg); |
Chris Wilson | 74ce6b6 | 2012-10-19 15:51:06 +0100 | [diff] [blame] | 1835 | obj->pages = st; |
| 1836 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1837 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 1838 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1839 | |
| 1840 | return 0; |
| 1841 | |
| 1842 | err_pages: |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1843 | sg_mark_end(sg); |
| 1844 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1845 | page_cache_release(sg_page_iter_page(&sg_iter)); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1846 | sg_free_table(st); |
| 1847 | kfree(st); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1848 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1849 | } |
| 1850 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1851 | /* Ensure that the associated pages are gathered from the backing storage |
| 1852 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 1853 | * multiple times before they are released by a single call to |
| 1854 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 1855 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 1856 | * or as the object is itself released. |
| 1857 | */ |
| 1858 | int |
| 1859 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 1860 | { |
| 1861 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1862 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1863 | int ret; |
| 1864 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 1865 | if (obj->pages) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1866 | return 0; |
| 1867 | |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 1868 | if (obj->madv != I915_MADV_WILLNEED) { |
| 1869 | DRM_ERROR("Attempting to obtain a purgeable object\n"); |
| 1870 | return -EINVAL; |
| 1871 | } |
| 1872 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1873 | BUG_ON(obj->pages_pin_count); |
| 1874 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1875 | ret = ops->get_pages(obj); |
| 1876 | if (ret) |
| 1877 | return ret; |
| 1878 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1879 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1880 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1881 | } |
| 1882 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1883 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1884 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1885 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1886 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1887 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1888 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1889 | u32 seqno = intel_ring_get_seqno(ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1890 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1891 | BUG_ON(ring == NULL); |
Chris Wilson | 02978ff | 2013-07-09 09:22:39 +0100 | [diff] [blame] | 1892 | if (obj->ring != ring && obj->last_write_seqno) { |
| 1893 | /* Keep the seqno relative to the current ring */ |
| 1894 | obj->last_write_seqno = seqno; |
| 1895 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1896 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1897 | |
| 1898 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1899 | if (!obj->active) { |
| 1900 | drm_gem_object_reference(&obj->base); |
| 1901 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1902 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1903 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1904 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1905 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 1906 | obj->last_read_seqno = seqno; |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1907 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1908 | if (obj->fenced_gpu_access) { |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1909 | obj->last_fenced_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1910 | |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1911 | /* Bump MRU to take account of the delayed flush */ |
| 1912 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 1913 | struct drm_i915_fence_reg *reg; |
| 1914 | |
| 1915 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1916 | list_move_tail(®->lru_list, |
| 1917 | &dev_priv->mm.fence_list); |
| 1918 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1919 | } |
| 1920 | } |
| 1921 | |
| 1922 | static void |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1923 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1924 | { |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 1925 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1926 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; |
| 1927 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1928 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1929 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1930 | BUG_ON(!obj->active); |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1931 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 1932 | list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1933 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1934 | list_del_init(&obj->ring_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1935 | obj->ring = NULL; |
| 1936 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1937 | obj->last_read_seqno = 0; |
| 1938 | obj->last_write_seqno = 0; |
| 1939 | obj->base.write_domain = 0; |
| 1940 | |
| 1941 | obj->last_fenced_seqno = 0; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1942 | obj->fenced_gpu_access = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1943 | |
| 1944 | obj->active = 0; |
| 1945 | drm_gem_object_unreference(&obj->base); |
| 1946 | |
| 1947 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1948 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1949 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1950 | static int |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 1951 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1952 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1953 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1954 | struct intel_ring_buffer *ring; |
| 1955 | int ret, i, j; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1956 | |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 1957 | /* Carefully retire all requests without writing to the rings */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1958 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 1959 | ret = intel_ring_idle(ring); |
| 1960 | if (ret) |
| 1961 | return ret; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1962 | } |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1963 | i915_gem_retire_requests(dev); |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 1964 | |
| 1965 | /* Finally reset hw state */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1966 | for_each_ring(ring, dev_priv, i) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 1967 | intel_ring_init_seqno(ring, seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1968 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1969 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
| 1970 | ring->sync_seqno[j] = 0; |
| 1971 | } |
| 1972 | |
| 1973 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1974 | } |
| 1975 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 1976 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
| 1977 | { |
| 1978 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1979 | int ret; |
| 1980 | |
| 1981 | if (seqno == 0) |
| 1982 | return -EINVAL; |
| 1983 | |
| 1984 | /* HWS page needs to be set less than what we |
| 1985 | * will inject to ring |
| 1986 | */ |
| 1987 | ret = i915_gem_init_seqno(dev, seqno - 1); |
| 1988 | if (ret) |
| 1989 | return ret; |
| 1990 | |
| 1991 | /* Carefully set the last_seqno value so that wrap |
| 1992 | * detection still works |
| 1993 | */ |
| 1994 | dev_priv->next_seqno = seqno; |
| 1995 | dev_priv->last_seqno = seqno - 1; |
| 1996 | if (dev_priv->last_seqno == 0) |
| 1997 | dev_priv->last_seqno--; |
| 1998 | |
| 1999 | return 0; |
| 2000 | } |
| 2001 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2002 | int |
| 2003 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2004 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2005 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2006 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2007 | /* reserve 0 for non-seqno */ |
| 2008 | if (dev_priv->next_seqno == 0) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2009 | int ret = i915_gem_init_seqno(dev, 0); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2010 | if (ret) |
| 2011 | return ret; |
| 2012 | |
| 2013 | dev_priv->next_seqno = 1; |
| 2014 | } |
| 2015 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 2016 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2017 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2018 | } |
| 2019 | |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2020 | int __i915_add_request(struct intel_ring_buffer *ring, |
| 2021 | struct drm_file *file, |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2022 | struct drm_i915_gem_object *obj, |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2023 | u32 *out_seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2024 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2025 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2026 | struct drm_i915_gem_request *request; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2027 | u32 request_ring_position, request_start; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2028 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2029 | int ret; |
| 2030 | |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2031 | request_start = intel_ring_get_tail(ring); |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2032 | /* |
| 2033 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 2034 | * after having emitted the batchbuffer command. Hence we need to fix |
| 2035 | * things up similar to emitting the lazy request. The difference here |
| 2036 | * is that the flush _must_ happen before the next request, no matter |
| 2037 | * what. |
| 2038 | */ |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2039 | ret = intel_ring_flush_all_caches(ring); |
| 2040 | if (ret) |
| 2041 | return ret; |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2042 | |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 2043 | request = ring->preallocated_lazy_request; |
| 2044 | if (WARN_ON(request == NULL)) |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2045 | return -ENOMEM; |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2046 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2047 | /* Record the position of the start of the request so that |
| 2048 | * should we detect the updated seqno part-way through the |
| 2049 | * GPU processing the request, we never over-estimate the |
| 2050 | * position of the head. |
| 2051 | */ |
| 2052 | request_ring_position = intel_ring_get_tail(ring); |
| 2053 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2054 | ret = ring->add_request(ring); |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 2055 | if (ret) |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2056 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2057 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2058 | request->seqno = intel_ring_get_seqno(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2059 | request->ring = ring; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2060 | request->head = request_start; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2061 | request->tail = request_ring_position; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2062 | |
| 2063 | /* Whilst this request exists, batch_obj will be on the |
| 2064 | * active_list, and so will hold the active reference. Only when this |
| 2065 | * request is retired will the the batch_obj be moved onto the |
| 2066 | * inactive_list and lose its active reference. Hence we do not need |
| 2067 | * to explicitly hold another reference here. |
| 2068 | */ |
Chris Wilson | 9a7e0c2 | 2013-08-26 19:50:54 -0300 | [diff] [blame] | 2069 | request->batch_obj = obj; |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2070 | |
Chris Wilson | 9a7e0c2 | 2013-08-26 19:50:54 -0300 | [diff] [blame] | 2071 | /* Hold a reference to the current context so that we can inspect |
| 2072 | * it later in case a hangcheck error event fires. |
| 2073 | */ |
| 2074 | request->ctx = ring->last_context; |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2075 | if (request->ctx) |
| 2076 | i915_gem_context_reference(request->ctx); |
| 2077 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2078 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2079 | was_empty = list_empty(&ring->request_list); |
| 2080 | list_add_tail(&request->list, &ring->request_list); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2081 | request->file_priv = NULL; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2082 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2083 | if (file) { |
| 2084 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 2085 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2086 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2087 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2088 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2089 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2090 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2091 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2092 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2093 | trace_i915_gem_request_add(ring, request->seqno); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 2094 | ring->outstanding_lazy_seqno = 0; |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 2095 | ring->preallocated_lazy_request = NULL; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2096 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 2097 | if (!dev_priv->ums.mm_suspended) { |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 2098 | i915_queue_hangcheck(ring->dev); |
| 2099 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2100 | if (was_empty) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 2101 | queue_delayed_work(dev_priv->wq, |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2102 | &dev_priv->mm.retire_work, |
| 2103 | round_jiffies_up_relative(HZ)); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2104 | intel_mark_busy(dev_priv->dev); |
| 2105 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2106 | } |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2107 | |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2108 | if (out_seqno) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2109 | *out_seqno = request->seqno; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2110 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2111 | } |
| 2112 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2113 | static inline void |
| 2114 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2115 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2116 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2117 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2118 | if (!file_priv) |
| 2119 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2120 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2121 | spin_lock(&file_priv->mm.lock); |
Herton Ronaldo Krzesinski | 09bfa51 | 2011-03-17 13:45:12 +0000 | [diff] [blame] | 2122 | if (request->file_priv) { |
| 2123 | list_del(&request->client_list); |
| 2124 | request->file_priv = NULL; |
| 2125 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2126 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2127 | } |
| 2128 | |
Ben Widawsky | d1ccbb5 | 2013-07-31 17:00:05 -0700 | [diff] [blame] | 2129 | static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj, |
| 2130 | struct i915_address_space *vm) |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2131 | { |
Ben Widawsky | d1ccbb5 | 2013-07-31 17:00:05 -0700 | [diff] [blame] | 2132 | if (acthd >= i915_gem_obj_offset(obj, vm) && |
| 2133 | acthd < i915_gem_obj_offset(obj, vm) + obj->base.size) |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2134 | return true; |
| 2135 | |
| 2136 | return false; |
| 2137 | } |
| 2138 | |
| 2139 | static bool i915_head_inside_request(const u32 acthd_unmasked, |
| 2140 | const u32 request_start, |
| 2141 | const u32 request_end) |
| 2142 | { |
| 2143 | const u32 acthd = acthd_unmasked & HEAD_ADDR; |
| 2144 | |
| 2145 | if (request_start < request_end) { |
| 2146 | if (acthd >= request_start && acthd < request_end) |
| 2147 | return true; |
| 2148 | } else if (request_start > request_end) { |
| 2149 | if (acthd >= request_start || acthd < request_end) |
| 2150 | return true; |
| 2151 | } |
| 2152 | |
| 2153 | return false; |
| 2154 | } |
| 2155 | |
Ben Widawsky | d1ccbb5 | 2013-07-31 17:00:05 -0700 | [diff] [blame] | 2156 | static struct i915_address_space * |
| 2157 | request_to_vm(struct drm_i915_gem_request *request) |
| 2158 | { |
| 2159 | struct drm_i915_private *dev_priv = request->ring->dev->dev_private; |
| 2160 | struct i915_address_space *vm; |
| 2161 | |
| 2162 | vm = &dev_priv->gtt.base; |
| 2163 | |
| 2164 | return vm; |
| 2165 | } |
| 2166 | |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2167 | static bool i915_request_guilty(struct drm_i915_gem_request *request, |
| 2168 | const u32 acthd, bool *inside) |
| 2169 | { |
| 2170 | /* There is a possibility that unmasked head address |
| 2171 | * pointing inside the ring, matches the batch_obj address range. |
| 2172 | * However this is extremely unlikely. |
| 2173 | */ |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2174 | if (request->batch_obj) { |
Ben Widawsky | d1ccbb5 | 2013-07-31 17:00:05 -0700 | [diff] [blame] | 2175 | if (i915_head_inside_object(acthd, request->batch_obj, |
| 2176 | request_to_vm(request))) { |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2177 | *inside = true; |
| 2178 | return true; |
| 2179 | } |
| 2180 | } |
| 2181 | |
| 2182 | if (i915_head_inside_request(acthd, request->head, request->tail)) { |
| 2183 | *inside = false; |
| 2184 | return true; |
| 2185 | } |
| 2186 | |
| 2187 | return false; |
| 2188 | } |
| 2189 | |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2190 | static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs) |
| 2191 | { |
| 2192 | const unsigned long elapsed = get_seconds() - hs->guilty_ts; |
| 2193 | |
| 2194 | if (hs->banned) |
| 2195 | return true; |
| 2196 | |
| 2197 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { |
| 2198 | DRM_ERROR("context hanging too fast, declaring banned!\n"); |
| 2199 | return true; |
| 2200 | } |
| 2201 | |
| 2202 | return false; |
| 2203 | } |
| 2204 | |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2205 | static void i915_set_reset_status(struct intel_ring_buffer *ring, |
| 2206 | struct drm_i915_gem_request *request, |
| 2207 | u32 acthd) |
| 2208 | { |
| 2209 | struct i915_ctx_hang_stats *hs = NULL; |
| 2210 | bool inside, guilty; |
Ben Widawsky | d1ccbb5 | 2013-07-31 17:00:05 -0700 | [diff] [blame] | 2211 | unsigned long offset = 0; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2212 | |
| 2213 | /* Innocent until proven guilty */ |
| 2214 | guilty = false; |
| 2215 | |
Ben Widawsky | d1ccbb5 | 2013-07-31 17:00:05 -0700 | [diff] [blame] | 2216 | if (request->batch_obj) |
| 2217 | offset = i915_gem_obj_offset(request->batch_obj, |
| 2218 | request_to_vm(request)); |
| 2219 | |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2220 | if (ring->hangcheck.action != HANGCHECK_WAIT && |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2221 | i915_request_guilty(request, acthd, &inside)) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2222 | DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n", |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2223 | ring->name, |
| 2224 | inside ? "inside" : "flushing", |
Ben Widawsky | d1ccbb5 | 2013-07-31 17:00:05 -0700 | [diff] [blame] | 2225 | offset, |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2226 | request->ctx ? request->ctx->id : 0, |
| 2227 | acthd); |
| 2228 | |
| 2229 | guilty = true; |
| 2230 | } |
| 2231 | |
| 2232 | /* If contexts are disabled or this is the default context, use |
| 2233 | * file_priv->reset_state |
| 2234 | */ |
| 2235 | if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID) |
| 2236 | hs = &request->ctx->hang_stats; |
| 2237 | else if (request->file_priv) |
| 2238 | hs = &request->file_priv->hang_stats; |
| 2239 | |
| 2240 | if (hs) { |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2241 | if (guilty) { |
| 2242 | hs->banned = i915_context_is_banned(hs); |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2243 | hs->batch_active++; |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2244 | hs->guilty_ts = get_seconds(); |
| 2245 | } else { |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2246 | hs->batch_pending++; |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2247 | } |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2248 | } |
| 2249 | } |
| 2250 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2251 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
| 2252 | { |
| 2253 | list_del(&request->list); |
| 2254 | i915_gem_request_remove_from_client(request); |
| 2255 | |
| 2256 | if (request->ctx) |
| 2257 | i915_gem_context_unreference(request->ctx); |
| 2258 | |
| 2259 | kfree(request); |
| 2260 | } |
| 2261 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2262 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 2263 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2264 | { |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2265 | u32 completed_seqno; |
| 2266 | u32 acthd; |
| 2267 | |
| 2268 | acthd = intel_ring_get_active_head(ring); |
| 2269 | completed_seqno = ring->get_seqno(ring, false); |
| 2270 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2271 | while (!list_empty(&ring->request_list)) { |
| 2272 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2273 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2274 | request = list_first_entry(&ring->request_list, |
| 2275 | struct drm_i915_gem_request, |
| 2276 | list); |
| 2277 | |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2278 | if (request->seqno > completed_seqno) |
| 2279 | i915_set_reset_status(ring, request, acthd); |
| 2280 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2281 | i915_gem_free_request(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2282 | } |
| 2283 | |
| 2284 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2285 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2286 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2287 | obj = list_first_entry(&ring->active_list, |
| 2288 | struct drm_i915_gem_object, |
| 2289 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2290 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2291 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2292 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2293 | } |
| 2294 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2295 | void i915_gem_restore_fences(struct drm_device *dev) |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2296 | { |
| 2297 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2298 | int i; |
| 2299 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 2300 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2301 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 2302 | |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 2303 | /* |
| 2304 | * Commit delayed tiling changes if we have an object still |
| 2305 | * attached to the fence, otherwise just clear the fence. |
| 2306 | */ |
| 2307 | if (reg->obj) { |
| 2308 | i915_gem_object_update_fence(reg->obj, reg, |
| 2309 | reg->obj->tiling_mode); |
| 2310 | } else { |
| 2311 | i915_gem_write_fence(dev, i, NULL); |
| 2312 | } |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2313 | } |
| 2314 | } |
| 2315 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2316 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2317 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2318 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2319 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2320 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2321 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2322 | for_each_ring(ring, dev_priv, i) |
| 2323 | i915_gem_reset_ring_lists(dev_priv, ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2324 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2325 | i915_gem_restore_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2326 | } |
| 2327 | |
| 2328 | /** |
| 2329 | * This function clears the request list as sequence numbers are passed. |
| 2330 | */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2331 | void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2332 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2333 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2334 | uint32_t seqno; |
| 2335 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2336 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 2337 | return; |
| 2338 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2339 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2340 | |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 2341 | seqno = ring->get_seqno(ring, true); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2342 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2343 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2344 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2345 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2346 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2347 | struct drm_i915_gem_request, |
| 2348 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2349 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2350 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2351 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2352 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2353 | trace_i915_gem_request_retire(ring, request->seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2354 | /* We know the GPU must have read the request to have |
| 2355 | * sent us the seqno + interrupt, so use the position |
| 2356 | * of tail of the request to update the last known position |
| 2357 | * of the GPU head. |
| 2358 | */ |
| 2359 | ring->last_retired_head = request->tail; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2360 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2361 | i915_gem_free_request(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2362 | } |
| 2363 | |
| 2364 | /* Move any buffers on the active list that are no longer referenced |
| 2365 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 2366 | */ |
| 2367 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2368 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2369 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2370 | obj = list_first_entry(&ring->active_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2371 | struct drm_i915_gem_object, |
| 2372 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2373 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2374 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2375 | break; |
| 2376 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2377 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2378 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2379 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2380 | if (unlikely(ring->trace_irq_seqno && |
| 2381 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2382 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2383 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2384 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2385 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2386 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2387 | } |
| 2388 | |
| 2389 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2390 | i915_gem_retire_requests(struct drm_device *dev) |
| 2391 | { |
| 2392 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2393 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2394 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2395 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2396 | for_each_ring(ring, dev_priv, i) |
| 2397 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2398 | } |
| 2399 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2400 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2401 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2402 | { |
| 2403 | drm_i915_private_t *dev_priv; |
| 2404 | struct drm_device *dev; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2405 | struct intel_ring_buffer *ring; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2406 | bool idle; |
| 2407 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2408 | |
| 2409 | dev_priv = container_of(work, drm_i915_private_t, |
| 2410 | mm.retire_work.work); |
| 2411 | dev = dev_priv->dev; |
| 2412 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2413 | /* Come back later if the device is busy... */ |
| 2414 | if (!mutex_trylock(&dev->struct_mutex)) { |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2415 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 2416 | round_jiffies_up_relative(HZ)); |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2417 | return; |
| 2418 | } |
| 2419 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2420 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2421 | |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2422 | /* Send a periodic flush down the ring so we don't hold onto GEM |
| 2423 | * objects indefinitely. |
| 2424 | */ |
| 2425 | idle = true; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2426 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2427 | if (ring->gpu_caches_dirty) |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2428 | i915_add_request(ring, NULL); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2429 | |
| 2430 | idle &= list_empty(&ring->request_list); |
| 2431 | } |
| 2432 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 2433 | if (!dev_priv->ums.mm_suspended && !idle) |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2434 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 2435 | round_jiffies_up_relative(HZ)); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2436 | if (idle) |
| 2437 | intel_mark_idle(dev); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2438 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2439 | mutex_unlock(&dev->struct_mutex); |
| 2440 | } |
| 2441 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2442 | /** |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2443 | * Ensures that an object will eventually get non-busy by flushing any required |
| 2444 | * write domains, emitting any outstanding lazy request and retiring and |
| 2445 | * completed requests. |
| 2446 | */ |
| 2447 | static int |
| 2448 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 2449 | { |
| 2450 | int ret; |
| 2451 | |
| 2452 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2453 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2454 | if (ret) |
| 2455 | return ret; |
| 2456 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2457 | i915_gem_retire_requests_ring(obj->ring); |
| 2458 | } |
| 2459 | |
| 2460 | return 0; |
| 2461 | } |
| 2462 | |
| 2463 | /** |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2464 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 2465 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 2466 | * |
| 2467 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 2468 | * the timeout parameter. |
| 2469 | * -ETIME: object is still busy after timeout |
| 2470 | * -ERESTARTSYS: signal interrupted the wait |
| 2471 | * -ENONENT: object doesn't exist |
| 2472 | * Also possible, but rare: |
| 2473 | * -EAGAIN: GPU wedged |
| 2474 | * -ENOMEM: damn |
| 2475 | * -ENODEV: Internal IRQ fail |
| 2476 | * -E?: The add request failed |
| 2477 | * |
| 2478 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 2479 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 2480 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 2481 | * without holding struct_mutex the object may become re-busied before this |
| 2482 | * function completes. A similar but shorter * race condition exists in the busy |
| 2483 | * ioctl |
| 2484 | */ |
| 2485 | int |
| 2486 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 2487 | { |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2488 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2489 | struct drm_i915_gem_wait *args = data; |
| 2490 | struct drm_i915_gem_object *obj; |
| 2491 | struct intel_ring_buffer *ring = NULL; |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2492 | struct timespec timeout_stack, *timeout = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2493 | unsigned reset_counter; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2494 | u32 seqno = 0; |
| 2495 | int ret = 0; |
| 2496 | |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2497 | if (args->timeout_ns >= 0) { |
| 2498 | timeout_stack = ns_to_timespec(args->timeout_ns); |
| 2499 | timeout = &timeout_stack; |
| 2500 | } |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2501 | |
| 2502 | ret = i915_mutex_lock_interruptible(dev); |
| 2503 | if (ret) |
| 2504 | return ret; |
| 2505 | |
| 2506 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 2507 | if (&obj->base == NULL) { |
| 2508 | mutex_unlock(&dev->struct_mutex); |
| 2509 | return -ENOENT; |
| 2510 | } |
| 2511 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2512 | /* Need to make sure the object gets inactive eventually. */ |
| 2513 | ret = i915_gem_object_flush_active(obj); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2514 | if (ret) |
| 2515 | goto out; |
| 2516 | |
| 2517 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2518 | seqno = obj->last_read_seqno; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2519 | ring = obj->ring; |
| 2520 | } |
| 2521 | |
| 2522 | if (seqno == 0) |
| 2523 | goto out; |
| 2524 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2525 | /* Do this after OLR check to make sure we make forward progress polling |
| 2526 | * on this IOCTL with a 0 timeout (like busy ioctl) |
| 2527 | */ |
| 2528 | if (!args->timeout_ns) { |
| 2529 | ret = -ETIME; |
| 2530 | goto out; |
| 2531 | } |
| 2532 | |
| 2533 | drm_gem_object_unreference(&obj->base); |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2534 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2535 | mutex_unlock(&dev->struct_mutex); |
| 2536 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2537 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout); |
Chris Wilson | 4f42f4e | 2013-04-26 16:22:46 +0300 | [diff] [blame] | 2538 | if (timeout) |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2539 | args->timeout_ns = timespec_to_ns(timeout); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2540 | return ret; |
| 2541 | |
| 2542 | out: |
| 2543 | drm_gem_object_unreference(&obj->base); |
| 2544 | mutex_unlock(&dev->struct_mutex); |
| 2545 | return ret; |
| 2546 | } |
| 2547 | |
| 2548 | /** |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2549 | * i915_gem_object_sync - sync an object to a ring. |
| 2550 | * |
| 2551 | * @obj: object which may be in use on another ring. |
| 2552 | * @to: ring we wish to use the object on. May be NULL. |
| 2553 | * |
| 2554 | * This code is meant to abstract object synchronization with the GPU. |
| 2555 | * Calling with NULL implies synchronizing the object with the CPU |
| 2556 | * rather than a particular GPU ring. |
| 2557 | * |
| 2558 | * Returns 0 if successful, else propagates up the lower layer error. |
| 2559 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2560 | int |
| 2561 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 2562 | struct intel_ring_buffer *to) |
| 2563 | { |
| 2564 | struct intel_ring_buffer *from = obj->ring; |
| 2565 | u32 seqno; |
| 2566 | int ret, idx; |
| 2567 | |
| 2568 | if (from == NULL || to == from) |
| 2569 | return 0; |
| 2570 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2571 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2572 | return i915_gem_object_wait_rendering(obj, false); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2573 | |
| 2574 | idx = intel_ring_sync_index(from, to); |
| 2575 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2576 | seqno = obj->last_read_seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2577 | if (seqno <= from->sync_seqno[idx]) |
| 2578 | return 0; |
| 2579 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 2580 | ret = i915_gem_check_olr(obj->ring, seqno); |
| 2581 | if (ret) |
| 2582 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2583 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 2584 | ret = to->sync_to(to, from, seqno); |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2585 | if (!ret) |
Mika Kuoppala | 7b01e26 | 2012-11-28 17:18:45 +0200 | [diff] [blame] | 2586 | /* We use last_read_seqno because sync_to() |
| 2587 | * might have just caused seqno wrap under |
| 2588 | * the radar. |
| 2589 | */ |
| 2590 | from->sync_seqno[idx] = obj->last_read_seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2591 | |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2592 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2593 | } |
| 2594 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2595 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 2596 | { |
| 2597 | u32 old_write_domain, old_read_domains; |
| 2598 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2599 | /* Force a pagefault for domain tracking on next user access */ |
| 2600 | i915_gem_release_mmap(obj); |
| 2601 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 2602 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 2603 | return; |
| 2604 | |
Chris Wilson | 97c809fd | 2012-10-09 19:24:38 +0100 | [diff] [blame] | 2605 | /* Wait for any direct GTT access to complete */ |
| 2606 | mb(); |
| 2607 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2608 | old_read_domains = obj->base.read_domains; |
| 2609 | old_write_domain = obj->base.write_domain; |
| 2610 | |
| 2611 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 2612 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 2613 | |
| 2614 | trace_i915_gem_object_change_domain(obj, |
| 2615 | old_read_domains, |
| 2616 | old_write_domain); |
| 2617 | } |
| 2618 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2619 | int i915_vma_unbind(struct i915_vma *vma) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2620 | { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2621 | struct drm_i915_gem_object *obj = vma->obj; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2622 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2623 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2624 | |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 2625 | /* For now we only ever use 1 vma per object */ |
| 2626 | WARN_ON(!list_is_singular(&obj->vma_list)); |
| 2627 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2628 | if (list_empty(&vma->vma_link)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2629 | return 0; |
| 2630 | |
Daniel Vetter | 0ff501c | 2013-08-29 19:50:31 +0200 | [diff] [blame] | 2631 | if (!drm_mm_node_allocated(&vma->node)) { |
| 2632 | i915_gem_vma_destroy(vma); |
| 2633 | |
| 2634 | return 0; |
| 2635 | } |
Ben Widawsky | 433544b | 2013-08-13 18:09:06 -0700 | [diff] [blame] | 2636 | |
Chris Wilson | 31d8d65 | 2012-05-24 19:11:20 +0100 | [diff] [blame] | 2637 | if (obj->pin_count) |
| 2638 | return -EBUSY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2639 | |
Chris Wilson | c4670ad | 2012-08-20 10:23:27 +0100 | [diff] [blame] | 2640 | BUG_ON(obj->pages == NULL); |
| 2641 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2642 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2643 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2644 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2645 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2646 | * should be safe and we need to cleanup or else we might |
| 2647 | * cause memory corruption through use-after-free. |
| 2648 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2649 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2650 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2651 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2652 | /* release the fence reg _after_ flushing */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2653 | ret = i915_gem_object_put_fence(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2654 | if (ret) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2655 | return ret; |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2656 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2657 | trace_i915_vma_unbind(vma); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2658 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 2659 | if (obj->has_global_gtt_mapping) |
| 2660 | i915_gem_gtt_unbind_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2661 | if (obj->has_aliasing_ppgtt_mapping) { |
| 2662 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); |
| 2663 | obj->has_aliasing_ppgtt_mapping = 0; |
| 2664 | } |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2665 | i915_gem_gtt_finish_object(obj); |
Ben Widawsky | 401c29f | 2013-05-31 11:28:47 -0700 | [diff] [blame] | 2666 | i915_gem_object_unpin_pages(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2667 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 2668 | list_del(&vma->mm_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2669 | /* Avoid an unnecessary call to unbind on rebind. */ |
Ben Widawsky | 5cacaac | 2013-07-31 17:00:13 -0700 | [diff] [blame] | 2670 | if (i915_is_ggtt(vma->vm)) |
| 2671 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2672 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 2673 | drm_mm_remove_node(&vma->node); |
Ben Widawsky | 433544b | 2013-08-13 18:09:06 -0700 | [diff] [blame] | 2674 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 2675 | i915_gem_vma_destroy(vma); |
| 2676 | |
| 2677 | /* Since the unbound list is global, only move to that list if |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 2678 | * no more VMAs exist. */ |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 2679 | if (list_empty(&obj->vma_list)) |
| 2680 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2681 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2682 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2683 | } |
| 2684 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2685 | /** |
| 2686 | * Unbinds an object from the global GTT aperture. |
| 2687 | */ |
| 2688 | int |
| 2689 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) |
| 2690 | { |
| 2691 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2692 | struct i915_address_space *ggtt = &dev_priv->gtt.base; |
| 2693 | |
Dan Carpenter | 58e73e1 | 2013-08-09 12:44:11 +0300 | [diff] [blame] | 2694 | if (!i915_gem_obj_ggtt_bound(obj)) |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2695 | return 0; |
| 2696 | |
| 2697 | if (obj->pin_count) |
| 2698 | return -EBUSY; |
| 2699 | |
| 2700 | BUG_ON(obj->pages == NULL); |
| 2701 | |
| 2702 | return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt)); |
| 2703 | } |
| 2704 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2705 | int i915_gpu_idle(struct drm_device *dev) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2706 | { |
| 2707 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2708 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2709 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2710 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2711 | /* Flush everything onto the inactive list. */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2712 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | b6c7488 | 2012-08-14 14:35:14 -0700 | [diff] [blame] | 2713 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
| 2714 | if (ret) |
| 2715 | return ret; |
| 2716 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2717 | ret = intel_ring_idle(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2718 | if (ret) |
| 2719 | return ret; |
| 2720 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2721 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2722 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2723 | } |
| 2724 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2725 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 2726 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2727 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2728 | drm_i915_private_t *dev_priv = dev->dev_private; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2729 | int fence_reg; |
| 2730 | int fence_pitch_shift; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2731 | |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2732 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2733 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
| 2734 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2735 | } else { |
| 2736 | fence_reg = FENCE_REG_965_0; |
| 2737 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
| 2738 | } |
| 2739 | |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 2740 | fence_reg += reg * 8; |
| 2741 | |
| 2742 | /* To w/a incoherency with non-atomic 64-bit register updates, |
| 2743 | * we split the 64-bit update into two 32-bit writes. In order |
| 2744 | * for a partial fence not to be evaluated between writes, we |
| 2745 | * precede the update with write to turn off the fence register, |
| 2746 | * and only enable the fence as the last step. |
| 2747 | * |
| 2748 | * For extra levels of paranoia, we make sure each step lands |
| 2749 | * before applying the next step. |
| 2750 | */ |
| 2751 | I915_WRITE(fence_reg, 0); |
| 2752 | POSTING_READ(fence_reg); |
| 2753 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2754 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2755 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 2756 | uint64_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2757 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2758 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2759 | 0xfffff000) << 32; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2760 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2761 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2762 | if (obj->tiling_mode == I915_TILING_Y) |
| 2763 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2764 | val |= I965_FENCE_REG_VALID; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2765 | |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 2766 | I915_WRITE(fence_reg + 4, val >> 32); |
| 2767 | POSTING_READ(fence_reg + 4); |
| 2768 | |
| 2769 | I915_WRITE(fence_reg + 0, val); |
| 2770 | POSTING_READ(fence_reg); |
| 2771 | } else { |
| 2772 | I915_WRITE(fence_reg + 4, 0); |
| 2773 | POSTING_READ(fence_reg + 4); |
| 2774 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2775 | } |
| 2776 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2777 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 2778 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2779 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2780 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2781 | u32 val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2782 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2783 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2784 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2785 | int pitch_val; |
| 2786 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2787 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2788 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2789 | (size & -size) != size || |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2790 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 2791 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2792 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2793 | |
| 2794 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 2795 | tile_width = 128; |
| 2796 | else |
| 2797 | tile_width = 512; |
| 2798 | |
| 2799 | /* Note: pitch better be a power of two tile widths */ |
| 2800 | pitch_val = obj->stride / tile_width; |
| 2801 | pitch_val = ffs(pitch_val) - 1; |
| 2802 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2803 | val = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2804 | if (obj->tiling_mode == I915_TILING_Y) |
| 2805 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2806 | val |= I915_FENCE_SIZE_BITS(size); |
| 2807 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2808 | val |= I830_FENCE_REG_VALID; |
| 2809 | } else |
| 2810 | val = 0; |
| 2811 | |
| 2812 | if (reg < 8) |
| 2813 | reg = FENCE_REG_830_0 + reg * 4; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2814 | else |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2815 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2816 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2817 | I915_WRITE(reg, val); |
| 2818 | POSTING_READ(reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2819 | } |
| 2820 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2821 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 2822 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2823 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2824 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2825 | uint32_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2826 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2827 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2828 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2829 | uint32_t pitch_val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2830 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2831 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2832 | (size & -size) != size || |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2833 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 2834 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", |
| 2835 | i915_gem_obj_ggtt_offset(obj), size); |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2836 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2837 | pitch_val = obj->stride / 128; |
| 2838 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2839 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2840 | val = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2841 | if (obj->tiling_mode == I915_TILING_Y) |
| 2842 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2843 | val |= I830_FENCE_SIZE_BITS(size); |
| 2844 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2845 | val |= I830_FENCE_REG_VALID; |
| 2846 | } else |
| 2847 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2848 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2849 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 2850 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 2851 | } |
| 2852 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2853 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
| 2854 | { |
| 2855 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
| 2856 | } |
| 2857 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2858 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 2859 | struct drm_i915_gem_object *obj) |
| 2860 | { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2861 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2862 | |
| 2863 | /* Ensure that all CPU reads are completed before installing a fence |
| 2864 | * and all writes before removing the fence. |
| 2865 | */ |
| 2866 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
| 2867 | mb(); |
| 2868 | |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 2869 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
| 2870 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", |
| 2871 | obj->stride, obj->tiling_mode); |
| 2872 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2873 | switch (INTEL_INFO(dev)->gen) { |
| 2874 | case 7: |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2875 | case 6: |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2876 | case 5: |
| 2877 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
| 2878 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
| 2879 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
Ben Widawsky | 7dbf9d6 | 2012-12-18 10:31:22 -0800 | [diff] [blame] | 2880 | default: BUG(); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2881 | } |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2882 | |
| 2883 | /* And similarly be paranoid that no direct access to this region |
| 2884 | * is reordered to before the fence is installed. |
| 2885 | */ |
| 2886 | if (i915_gem_object_needs_mb(obj)) |
| 2887 | mb(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2888 | } |
| 2889 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2890 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 2891 | struct drm_i915_fence_reg *fence) |
| 2892 | { |
| 2893 | return fence - dev_priv->fence_regs; |
| 2894 | } |
| 2895 | |
| 2896 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 2897 | struct drm_i915_fence_reg *fence, |
| 2898 | bool enable) |
| 2899 | { |
Chris Wilson | 2dc8aae | 2013-05-22 17:08:06 +0100 | [diff] [blame] | 2900 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 2901 | int reg = fence_number(dev_priv, fence); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2902 | |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 2903 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2904 | |
| 2905 | if (enable) { |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 2906 | obj->fence_reg = reg; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2907 | fence->obj = obj; |
| 2908 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 2909 | } else { |
| 2910 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 2911 | fence->obj = NULL; |
| 2912 | list_del_init(&fence->lru_list); |
| 2913 | } |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 2914 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2915 | } |
| 2916 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2917 | static int |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2918 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2919 | { |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 2920 | if (obj->last_fenced_seqno) { |
Chris Wilson | 86d5bc3 | 2012-07-20 12:41:04 +0100 | [diff] [blame] | 2921 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
Chris Wilson | 1899184 | 2012-04-17 15:31:29 +0100 | [diff] [blame] | 2922 | if (ret) |
| 2923 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2924 | |
| 2925 | obj->last_fenced_seqno = 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2926 | } |
| 2927 | |
Chris Wilson | 86d5bc3 | 2012-07-20 12:41:04 +0100 | [diff] [blame] | 2928 | obj->fenced_gpu_access = false; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2929 | return 0; |
| 2930 | } |
| 2931 | |
| 2932 | int |
| 2933 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 2934 | { |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2935 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 2936 | struct drm_i915_fence_reg *fence; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2937 | int ret; |
| 2938 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2939 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2940 | if (ret) |
| 2941 | return ret; |
| 2942 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2943 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 2944 | return 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2945 | |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 2946 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
| 2947 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2948 | i915_gem_object_fence_lost(obj); |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 2949 | i915_gem_object_update_fence(obj, fence, false); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2950 | |
| 2951 | return 0; |
| 2952 | } |
| 2953 | |
| 2954 | static struct drm_i915_fence_reg * |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2955 | i915_find_fence_reg(struct drm_device *dev) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2956 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2957 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2958 | struct drm_i915_fence_reg *reg, *avail; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2959 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2960 | |
| 2961 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2962 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2963 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2964 | reg = &dev_priv->fence_regs[i]; |
| 2965 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2966 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2967 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2968 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2969 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2970 | } |
| 2971 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2972 | if (avail == NULL) |
| 2973 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2974 | |
| 2975 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2976 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2977 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2978 | continue; |
| 2979 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2980 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2981 | } |
| 2982 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2983 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2984 | } |
| 2985 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2986 | /** |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2987 | * i915_gem_object_get_fence - set up fencing for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2988 | * @obj: object to map through a fence reg |
| 2989 | * |
| 2990 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2991 | * to them without having to worry about swizzling if the object is tiled. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2992 | * This function walks the fence regs looking for a free one for @obj, |
| 2993 | * stealing one if it can't find any. |
| 2994 | * |
| 2995 | * It then sets up the reg based on the object's properties: address, pitch |
| 2996 | * and tiling format. |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2997 | * |
| 2998 | * For an untiled surface, this removes any existing fence. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2999 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 3000 | int |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 3001 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3002 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3003 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3004 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3005 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3006 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3007 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3008 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3009 | /* Have we updated the tiling parameters upon the object and so |
| 3010 | * will need to serialise the write to the associated fence register? |
| 3011 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 3012 | if (obj->fence_dirty) { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3013 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3014 | if (ret) |
| 3015 | return ret; |
| 3016 | } |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3017 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3018 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3019 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 3020 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 3021 | if (!obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3022 | list_move_tail(®->lru_list, |
| 3023 | &dev_priv->mm.fence_list); |
| 3024 | return 0; |
| 3025 | } |
| 3026 | } else if (enable) { |
| 3027 | reg = i915_find_fence_reg(dev); |
| 3028 | if (reg == NULL) |
| 3029 | return -EDEADLK; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3030 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3031 | if (reg->obj) { |
| 3032 | struct drm_i915_gem_object *old = reg->obj; |
| 3033 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3034 | ret = i915_gem_object_wait_fence(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 3035 | if (ret) |
| 3036 | return ret; |
| 3037 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3038 | i915_gem_object_fence_lost(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 3039 | } |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3040 | } else |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3041 | return 0; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3042 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3043 | i915_gem_object_update_fence(obj, reg, enable); |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3044 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3045 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3046 | } |
| 3047 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3048 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
| 3049 | struct drm_mm_node *gtt_space, |
| 3050 | unsigned long cache_level) |
| 3051 | { |
| 3052 | struct drm_mm_node *other; |
| 3053 | |
| 3054 | /* On non-LLC machines we have to be careful when putting differing |
| 3055 | * types of snoopable memory together to avoid the prefetcher |
Damien Lespiau | 4239ca7 | 2012-12-03 16:26:16 +0000 | [diff] [blame] | 3056 | * crossing memory domains and dying. |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3057 | */ |
| 3058 | if (HAS_LLC(dev)) |
| 3059 | return true; |
| 3060 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3061 | if (!drm_mm_node_allocated(gtt_space)) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3062 | return true; |
| 3063 | |
| 3064 | if (list_empty(>t_space->node_list)) |
| 3065 | return true; |
| 3066 | |
| 3067 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 3068 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 3069 | return false; |
| 3070 | |
| 3071 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 3072 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 3073 | return false; |
| 3074 | |
| 3075 | return true; |
| 3076 | } |
| 3077 | |
| 3078 | static void i915_gem_verify_gtt(struct drm_device *dev) |
| 3079 | { |
| 3080 | #if WATCH_GTT |
| 3081 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3082 | struct drm_i915_gem_object *obj; |
| 3083 | int err = 0; |
| 3084 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3085 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3086 | if (obj->gtt_space == NULL) { |
| 3087 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); |
| 3088 | err++; |
| 3089 | continue; |
| 3090 | } |
| 3091 | |
| 3092 | if (obj->cache_level != obj->gtt_space->color) { |
| 3093 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3094 | i915_gem_obj_ggtt_offset(obj), |
| 3095 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3096 | obj->cache_level, |
| 3097 | obj->gtt_space->color); |
| 3098 | err++; |
| 3099 | continue; |
| 3100 | } |
| 3101 | |
| 3102 | if (!i915_gem_valid_gtt_space(dev, |
| 3103 | obj->gtt_space, |
| 3104 | obj->cache_level)) { |
| 3105 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3106 | i915_gem_obj_ggtt_offset(obj), |
| 3107 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3108 | obj->cache_level); |
| 3109 | err++; |
| 3110 | continue; |
| 3111 | } |
| 3112 | } |
| 3113 | |
| 3114 | WARN_ON(err); |
| 3115 | #endif |
| 3116 | } |
| 3117 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3118 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3119 | * Finds free space in the GTT aperture and binds the object there. |
| 3120 | */ |
| 3121 | static int |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3122 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| 3123 | struct i915_address_space *vm, |
| 3124 | unsigned alignment, |
| 3125 | bool map_and_fenceable, |
| 3126 | bool nonblocking) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3127 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3128 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3129 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3130 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3131 | size_t gtt_max = |
| 3132 | map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3133 | struct i915_vma *vma; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3134 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3135 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3136 | fence_size = i915_gem_get_gtt_size(dev, |
| 3137 | obj->base.size, |
| 3138 | obj->tiling_mode); |
| 3139 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3140 | obj->base.size, |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3141 | obj->tiling_mode, true); |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3142 | unfenced_alignment = |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3143 | i915_gem_get_gtt_alignment(dev, |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3144 | obj->base.size, |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3145 | obj->tiling_mode, false); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3146 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3147 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3148 | alignment = map_and_fenceable ? fence_alignment : |
| 3149 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3150 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3151 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 3152 | return -EINVAL; |
| 3153 | } |
| 3154 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3155 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3156 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3157 | /* If the object is bigger than the entire aperture, reject it early |
| 3158 | * before evicting everything in a vain attempt to find space. |
| 3159 | */ |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3160 | if (obj->base.size > gtt_max) { |
Jani Nikula | 3765f30 | 2013-06-07 16:03:50 +0300 | [diff] [blame] | 3161 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
Chris Wilson | a36689c | 2013-05-21 16:58:49 +0100 | [diff] [blame] | 3162 | obj->base.size, |
| 3163 | map_and_fenceable ? "mappable" : "total", |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3164 | gtt_max); |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3165 | return -E2BIG; |
| 3166 | } |
| 3167 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3168 | ret = i915_gem_object_get_pages(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3169 | if (ret) |
| 3170 | return ret; |
| 3171 | |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 3172 | i915_gem_object_pin_pages(obj); |
| 3173 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3174 | BUG_ON(!i915_is_ggtt(vm)); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3175 | |
Ben Widawsky | accfef2 | 2013-08-14 11:38:35 +0200 | [diff] [blame] | 3176 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
Dan Carpenter | db473b3 | 2013-07-19 08:45:46 +0300 | [diff] [blame] | 3177 | if (IS_ERR(vma)) { |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3178 | ret = PTR_ERR(vma); |
| 3179 | goto err_unpin; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3180 | } |
| 3181 | |
Ben Widawsky | accfef2 | 2013-08-14 11:38:35 +0200 | [diff] [blame] | 3182 | /* For now we only ever use 1 vma per object */ |
| 3183 | WARN_ON(!list_is_singular(&obj->vma_list)); |
| 3184 | |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3185 | search_free: |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3186 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3187 | size, alignment, |
David Herrmann | 31e5d7c | 2013-07-27 13:36:27 +0200 | [diff] [blame] | 3188 | obj->cache_level, 0, gtt_max, |
| 3189 | DRM_MM_SEARCH_DEFAULT); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3190 | if (ret) { |
Ben Widawsky | f6cd1f1 | 2013-07-31 17:00:11 -0700 | [diff] [blame] | 3191 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3192 | obj->cache_level, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3193 | map_and_fenceable, |
| 3194 | nonblocking); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3195 | if (ret == 0) |
| 3196 | goto search_free; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3197 | |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3198 | goto err_free_vma; |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3199 | } |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3200 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3201 | obj->cache_level))) { |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3202 | ret = -EINVAL; |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3203 | goto err_remove_node; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3204 | } |
| 3205 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 3206 | ret = i915_gem_gtt_prepare_object(obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3207 | if (ret) |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3208 | goto err_remove_node; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3209 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3210 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 3211 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 3212 | |
Ben Widawsky | 4bd561b | 2013-08-13 18:09:07 -0700 | [diff] [blame] | 3213 | if (i915_is_ggtt(vm)) { |
| 3214 | bool mappable, fenceable; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3215 | |
Daniel Vetter | 4998709 | 2013-08-14 10:21:23 +0200 | [diff] [blame] | 3216 | fenceable = (vma->node.size == fence_size && |
| 3217 | (vma->node.start & (fence_alignment - 1)) == 0); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3218 | |
Daniel Vetter | 4998709 | 2013-08-14 10:21:23 +0200 | [diff] [blame] | 3219 | mappable = (vma->node.start + obj->base.size <= |
| 3220 | dev_priv->gtt.mappable_end); |
Ben Widawsky | 4bd561b | 2013-08-13 18:09:07 -0700 | [diff] [blame] | 3221 | |
Ben Widawsky | 5cacaac | 2013-07-31 17:00:13 -0700 | [diff] [blame] | 3222 | obj->map_and_fenceable = mappable && fenceable; |
Ben Widawsky | 4bd561b | 2013-08-13 18:09:07 -0700 | [diff] [blame] | 3223 | } |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3224 | |
Ben Widawsky | 7ace7ef | 2013-08-09 22:12:12 -0700 | [diff] [blame] | 3225 | WARN_ON(map_and_fenceable && !obj->map_and_fenceable); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3226 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3227 | trace_i915_vma_bind(vma, map_and_fenceable); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3228 | i915_gem_verify_gtt(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3229 | return 0; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3230 | |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3231 | err_remove_node: |
Dan Carpenter | 6286ef9 | 2013-07-19 08:46:27 +0300 | [diff] [blame] | 3232 | drm_mm_remove_node(&vma->node); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3233 | err_free_vma: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3234 | i915_gem_vma_destroy(vma); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3235 | err_unpin: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3236 | i915_gem_object_unpin_pages(obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3237 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3238 | } |
| 3239 | |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3240 | bool |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3241 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
| 3242 | bool force) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3243 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3244 | /* If we don't have a page list set up, then we're not pinned |
| 3245 | * to GPU, and we can ignore the cache flush because it'll happen |
| 3246 | * again at bind time. |
| 3247 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3248 | if (obj->pages == NULL) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3249 | return false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3250 | |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3251 | /* |
| 3252 | * Stolen memory is always coherent with the GPU as it is explicitly |
| 3253 | * marked as wc by the system, or the system is cache-coherent. |
| 3254 | */ |
| 3255 | if (obj->stolen) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3256 | return false; |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3257 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3258 | /* If the GPU is snooping the contents of the CPU cache, |
| 3259 | * we do not need to manually clear the CPU cache lines. However, |
| 3260 | * the caches are only snooped when the render cache is |
| 3261 | * flushed/invalidated. As we always have to emit invalidations |
| 3262 | * and flushes when moving into and out of the RENDER domain, correct |
| 3263 | * snooping behaviour occurs naturally as the result of our domain |
| 3264 | * tracking. |
| 3265 | */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3266 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3267 | return false; |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3268 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3269 | trace_i915_gem_object_clflush(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3270 | drm_clflush_sg(obj->pages); |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3271 | |
| 3272 | return true; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3273 | } |
| 3274 | |
| 3275 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3276 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3277 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3278 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3279 | uint32_t old_write_domain; |
| 3280 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3281 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3282 | return; |
| 3283 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3284 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3285 | * to it immediately go to main memory as far as we know, so there's |
| 3286 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3287 | * |
| 3288 | * However, we do have to enforce the order so that all writes through |
| 3289 | * the GTT land before any writes to the device, such as updates to |
| 3290 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3291 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3292 | wmb(); |
| 3293 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3294 | old_write_domain = obj->base.write_domain; |
| 3295 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3296 | |
| 3297 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3298 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3299 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3300 | } |
| 3301 | |
| 3302 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3303 | static void |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3304 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
| 3305 | bool force) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3306 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3307 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3308 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3309 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3310 | return; |
| 3311 | |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3312 | if (i915_gem_clflush_object(obj, force)) |
| 3313 | i915_gem_chipset_flush(obj->base.dev); |
| 3314 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3315 | old_write_domain = obj->base.write_domain; |
| 3316 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3317 | |
| 3318 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3319 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3320 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3321 | } |
| 3322 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3323 | /** |
| 3324 | * Moves a single object to the GTT read, and possibly write domain. |
| 3325 | * |
| 3326 | * This function returns when the move is complete, including waiting on |
| 3327 | * flushes to occur. |
| 3328 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3329 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3330 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3331 | { |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3332 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3333 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3334 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3335 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3336 | /* Not valid to be called on unbound objects. */ |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 3337 | if (!i915_gem_obj_bound_any(obj)) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3338 | return -EINVAL; |
| 3339 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3340 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3341 | return 0; |
| 3342 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3343 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3344 | if (ret) |
| 3345 | return ret; |
| 3346 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3347 | i915_gem_object_flush_cpu_write_domain(obj, false); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3348 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3349 | /* Serialise direct access to this object with the barriers for |
| 3350 | * coherent writes from the GPU, by effectively invalidating the |
| 3351 | * GTT domain upon first access. |
| 3352 | */ |
| 3353 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3354 | mb(); |
| 3355 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3356 | old_write_domain = obj->base.write_domain; |
| 3357 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3358 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3359 | /* It should now be out of any other write domains, and we can update |
| 3360 | * the domain values for our changes. |
| 3361 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3362 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 3363 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3364 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3365 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 3366 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 3367 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3368 | } |
| 3369 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3370 | trace_i915_gem_object_change_domain(obj, |
| 3371 | old_read_domains, |
| 3372 | old_write_domain); |
| 3373 | |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3374 | /* And bump the LRU for this access */ |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 3375 | if (i915_gem_object_is_inactive(obj)) { |
| 3376 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
| 3377 | &dev_priv->gtt.base); |
| 3378 | if (vma) |
| 3379 | list_move_tail(&vma->mm_list, |
| 3380 | &dev_priv->gtt.base.inactive_list); |
| 3381 | |
| 3382 | } |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3383 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3384 | return 0; |
| 3385 | } |
| 3386 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3387 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 3388 | enum i915_cache_level cache_level) |
| 3389 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3390 | struct drm_device *dev = obj->base.dev; |
| 3391 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3392 | struct i915_vma *vma; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3393 | int ret; |
| 3394 | |
| 3395 | if (obj->cache_level == cache_level) |
| 3396 | return 0; |
| 3397 | |
| 3398 | if (obj->pin_count) { |
| 3399 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 3400 | return -EBUSY; |
| 3401 | } |
| 3402 | |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3403 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 3404 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3405 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3406 | if (ret) |
| 3407 | return ret; |
| 3408 | |
| 3409 | break; |
| 3410 | } |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3411 | } |
| 3412 | |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3413 | if (i915_gem_obj_bound_any(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3414 | ret = i915_gem_object_finish_gpu(obj); |
| 3415 | if (ret) |
| 3416 | return ret; |
| 3417 | |
| 3418 | i915_gem_object_finish_gtt(obj); |
| 3419 | |
| 3420 | /* Before SandyBridge, you could not use tiling or fence |
| 3421 | * registers with snooped memory, so relinquish any fences |
| 3422 | * currently pointing to our region in the aperture. |
| 3423 | */ |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3424 | if (INTEL_INFO(dev)->gen < 6) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3425 | ret = i915_gem_object_put_fence(obj); |
| 3426 | if (ret) |
| 3427 | return ret; |
| 3428 | } |
| 3429 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3430 | if (obj->has_global_gtt_mapping) |
| 3431 | i915_gem_gtt_bind_object(obj, cache_level); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3432 | if (obj->has_aliasing_ppgtt_mapping) |
| 3433 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
| 3434 | obj, cache_level); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3435 | } |
| 3436 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3437 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 3438 | vma->node.color = cache_level; |
| 3439 | obj->cache_level = cache_level; |
| 3440 | |
| 3441 | if (cpu_write_needs_clflush(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3442 | u32 old_read_domains, old_write_domain; |
| 3443 | |
| 3444 | /* If we're coming from LLC cached, then we haven't |
| 3445 | * actually been tracking whether the data is in the |
| 3446 | * CPU cache or not, since we only allow one bit set |
| 3447 | * in obj->write_domain and have been skipping the clflushes. |
| 3448 | * Just set it to the CPU cache for now. |
| 3449 | */ |
| 3450 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3451 | |
| 3452 | old_read_domains = obj->base.read_domains; |
| 3453 | old_write_domain = obj->base.write_domain; |
| 3454 | |
| 3455 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3456 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3457 | |
| 3458 | trace_i915_gem_object_change_domain(obj, |
| 3459 | old_read_domains, |
| 3460 | old_write_domain); |
| 3461 | } |
| 3462 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3463 | i915_gem_verify_gtt(dev); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3464 | return 0; |
| 3465 | } |
| 3466 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3467 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 3468 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3469 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3470 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3471 | struct drm_i915_gem_object *obj; |
| 3472 | int ret; |
| 3473 | |
| 3474 | ret = i915_mutex_lock_interruptible(dev); |
| 3475 | if (ret) |
| 3476 | return ret; |
| 3477 | |
| 3478 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3479 | if (&obj->base == NULL) { |
| 3480 | ret = -ENOENT; |
| 3481 | goto unlock; |
| 3482 | } |
| 3483 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3484 | switch (obj->cache_level) { |
| 3485 | case I915_CACHE_LLC: |
| 3486 | case I915_CACHE_L3_LLC: |
| 3487 | args->caching = I915_CACHING_CACHED; |
| 3488 | break; |
| 3489 | |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 3490 | case I915_CACHE_WT: |
| 3491 | args->caching = I915_CACHING_DISPLAY; |
| 3492 | break; |
| 3493 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3494 | default: |
| 3495 | args->caching = I915_CACHING_NONE; |
| 3496 | break; |
| 3497 | } |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3498 | |
| 3499 | drm_gem_object_unreference(&obj->base); |
| 3500 | unlock: |
| 3501 | mutex_unlock(&dev->struct_mutex); |
| 3502 | return ret; |
| 3503 | } |
| 3504 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3505 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 3506 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3507 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3508 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3509 | struct drm_i915_gem_object *obj; |
| 3510 | enum i915_cache_level level; |
| 3511 | int ret; |
| 3512 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3513 | switch (args->caching) { |
| 3514 | case I915_CACHING_NONE: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3515 | level = I915_CACHE_NONE; |
| 3516 | break; |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3517 | case I915_CACHING_CACHED: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3518 | level = I915_CACHE_LLC; |
| 3519 | break; |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 3520 | case I915_CACHING_DISPLAY: |
| 3521 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
| 3522 | break; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3523 | default: |
| 3524 | return -EINVAL; |
| 3525 | } |
| 3526 | |
Ben Widawsky | 3bc2913 | 2012-09-26 16:15:20 -0700 | [diff] [blame] | 3527 | ret = i915_mutex_lock_interruptible(dev); |
| 3528 | if (ret) |
| 3529 | return ret; |
| 3530 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3531 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3532 | if (&obj->base == NULL) { |
| 3533 | ret = -ENOENT; |
| 3534 | goto unlock; |
| 3535 | } |
| 3536 | |
| 3537 | ret = i915_gem_object_set_cache_level(obj, level); |
| 3538 | |
| 3539 | drm_gem_object_unreference(&obj->base); |
| 3540 | unlock: |
| 3541 | mutex_unlock(&dev->struct_mutex); |
| 3542 | return ret; |
| 3543 | } |
| 3544 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3545 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
| 3546 | { |
| 3547 | /* There are 3 sources that pin objects: |
| 3548 | * 1. The display engine (scanouts, sprites, cursors); |
| 3549 | * 2. Reservations for execbuffer; |
| 3550 | * 3. The user. |
| 3551 | * |
| 3552 | * We can ignore reservations as we hold the struct_mutex and |
| 3553 | * are only called outside of the reservation path. The user |
| 3554 | * can only increment pin_count once, and so if after |
| 3555 | * subtracting the potential reference by the user, any pin_count |
| 3556 | * remains, it must be due to another use by the display engine. |
| 3557 | */ |
| 3558 | return obj->pin_count - !!obj->user_pin_count; |
| 3559 | } |
| 3560 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3561 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3562 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 3563 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 3564 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3565 | */ |
| 3566 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3567 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 3568 | u32 alignment, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3569 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3570 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3571 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3572 | int ret; |
| 3573 | |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 3574 | if (pipelined != obj->ring) { |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3575 | ret = i915_gem_object_sync(obj, pipelined); |
| 3576 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3577 | return ret; |
| 3578 | } |
| 3579 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3580 | /* Mark the pin_display early so that we account for the |
| 3581 | * display coherency whilst setting up the cache domains. |
| 3582 | */ |
| 3583 | obj->pin_display = true; |
| 3584 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3585 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 3586 | * a result, we make sure that the pinning that is about to occur is |
| 3587 | * done with uncached PTEs. This is lowest common denominator for all |
| 3588 | * chipsets. |
| 3589 | * |
| 3590 | * However for gen6+, we could do better by using the GFDT bit instead |
| 3591 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 3592 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 3593 | */ |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3594 | ret = i915_gem_object_set_cache_level(obj, |
| 3595 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3596 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3597 | goto err_unpin_display; |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3598 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3599 | /* As the user may map the buffer once pinned in the display plane |
| 3600 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 3601 | * always use map_and_fenceable for all scanout buffers. |
| 3602 | */ |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 3603 | ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3604 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3605 | goto err_unpin_display; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3606 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3607 | i915_gem_object_flush_cpu_write_domain(obj, true); |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3608 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3609 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3610 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3611 | |
| 3612 | /* It should now be out of any other write domains, and we can update |
| 3613 | * the domain values for our changes. |
| 3614 | */ |
Chris Wilson | e5f1d96 | 2012-07-20 12:41:00 +0100 | [diff] [blame] | 3615 | obj->base.write_domain = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3616 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3617 | |
| 3618 | trace_i915_gem_object_change_domain(obj, |
| 3619 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3620 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3621 | |
| 3622 | return 0; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3623 | |
| 3624 | err_unpin_display: |
| 3625 | obj->pin_display = is_pin_display(obj); |
| 3626 | return ret; |
| 3627 | } |
| 3628 | |
| 3629 | void |
| 3630 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) |
| 3631 | { |
| 3632 | i915_gem_object_unpin(obj); |
| 3633 | obj->pin_display = is_pin_display(obj); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3634 | } |
| 3635 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3636 | int |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3637 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3638 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3639 | int ret; |
| 3640 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3641 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3642 | return 0; |
| 3643 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3644 | ret = i915_gem_object_wait_rendering(obj, false); |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3645 | if (ret) |
| 3646 | return ret; |
| 3647 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3648 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 3649 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3650 | return 0; |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3651 | } |
| 3652 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3653 | /** |
| 3654 | * Moves a single object to the CPU read, and possibly write domain. |
| 3655 | * |
| 3656 | * This function returns when the move is complete, including waiting on |
| 3657 | * flushes to occur. |
| 3658 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 3659 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3660 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3661 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3662 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3663 | int ret; |
| 3664 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3665 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 3666 | return 0; |
| 3667 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3668 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3669 | if (ret) |
| 3670 | return ret; |
| 3671 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3672 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3673 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3674 | old_write_domain = obj->base.write_domain; |
| 3675 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3676 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3677 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3678 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3679 | i915_gem_clflush_object(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3680 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3681 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3682 | } |
| 3683 | |
| 3684 | /* It should now be out of any other write domains, and we can update |
| 3685 | * the domain values for our changes. |
| 3686 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3687 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3688 | |
| 3689 | /* If we're writing through the CPU, then the GPU read domains will |
| 3690 | * need to be invalidated at next use. |
| 3691 | */ |
| 3692 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3693 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3694 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3695 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3696 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3697 | trace_i915_gem_object_change_domain(obj, |
| 3698 | old_read_domains, |
| 3699 | old_write_domain); |
| 3700 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3701 | return 0; |
| 3702 | } |
| 3703 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3704 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3705 | * emitted over 20 msec ago. |
| 3706 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3707 | * Note that if we were to use the current jiffies each time around the loop, |
| 3708 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3709 | * render a frame was over 20ms. |
| 3710 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3711 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3712 | * relatively low latency when blocking on a particular request to finish. |
| 3713 | */ |
| 3714 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3715 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3716 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3717 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3718 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3719 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3720 | struct drm_i915_gem_request *request; |
| 3721 | struct intel_ring_buffer *ring = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3722 | unsigned reset_counter; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3723 | u32 seqno = 0; |
| 3724 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3725 | |
Daniel Vetter | 308887a | 2012-11-14 17:14:06 +0100 | [diff] [blame] | 3726 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 3727 | if (ret) |
| 3728 | return ret; |
| 3729 | |
| 3730 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
| 3731 | if (ret) |
| 3732 | return ret; |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 3733 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3734 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3735 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3736 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3737 | break; |
| 3738 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3739 | ring = request->ring; |
| 3740 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3741 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3742 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3743 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3744 | |
| 3745 | if (seqno == 0) |
| 3746 | return 0; |
| 3747 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3748 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3749 | if (ret == 0) |
| 3750 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3751 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3752 | return ret; |
| 3753 | } |
| 3754 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3755 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3756 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 3757 | struct i915_address_space *vm, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3758 | uint32_t alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3759 | bool map_and_fenceable, |
| 3760 | bool nonblocking) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3761 | { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3762 | struct i915_vma *vma; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3763 | int ret; |
| 3764 | |
Chris Wilson | 7e81a42 | 2012-09-15 09:41:57 +0100 | [diff] [blame] | 3765 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 3766 | return -EBUSY; |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3767 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3768 | WARN_ON(map_and_fenceable && !i915_is_ggtt(vm)); |
| 3769 | |
| 3770 | vma = i915_gem_obj_to_vma(obj, vm); |
| 3771 | |
| 3772 | if (vma) { |
| 3773 | if ((alignment && |
| 3774 | vma->node.start & (alignment - 1)) || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3775 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 3776 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 3777 | "bo is already pinned with incorrect alignment:" |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3778 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3779 | " obj->map_and_fenceable=%d\n", |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3780 | i915_gem_obj_offset(obj, vm), alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3781 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3782 | obj->map_and_fenceable); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3783 | ret = i915_vma_unbind(vma); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3784 | if (ret) |
| 3785 | return ret; |
| 3786 | } |
| 3787 | } |
| 3788 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3789 | if (!i915_gem_obj_bound(obj, vm)) { |
Chris Wilson | 8742267 | 2012-11-21 13:04:03 +0000 | [diff] [blame] | 3790 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 3791 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3792 | ret = i915_gem_object_bind_to_vm(obj, vm, alignment, |
| 3793 | map_and_fenceable, |
| 3794 | nonblocking); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3795 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3796 | return ret; |
Chris Wilson | 8742267 | 2012-11-21 13:04:03 +0000 | [diff] [blame] | 3797 | |
| 3798 | if (!dev_priv->mm.aliasing_ppgtt) |
| 3799 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3800 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3801 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3802 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
| 3803 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 3804 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3805 | obj->pin_count++; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3806 | obj->pin_mappable |= map_and_fenceable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3807 | |
| 3808 | return 0; |
| 3809 | } |
| 3810 | |
| 3811 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3812 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3813 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3814 | BUG_ON(obj->pin_count == 0); |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 3815 | BUG_ON(!i915_gem_obj_bound_any(obj)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3816 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3817 | if (--obj->pin_count == 0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3818 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3819 | } |
| 3820 | |
| 3821 | int |
| 3822 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3823 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3824 | { |
| 3825 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3826 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3827 | int ret; |
| 3828 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3829 | ret = i915_mutex_lock_interruptible(dev); |
| 3830 | if (ret) |
| 3831 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3832 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3833 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3834 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3835 | ret = -ENOENT; |
| 3836 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3837 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3838 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3839 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3840 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3841 | ret = -EINVAL; |
| 3842 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3843 | } |
| 3844 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3845 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3846 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3847 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3848 | ret = -EINVAL; |
| 3849 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3850 | } |
| 3851 | |
Chris Wilson | 93be878 | 2013-01-02 10:31:22 +0000 | [diff] [blame] | 3852 | if (obj->user_pin_count == 0) { |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 3853 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3854 | if (ret) |
| 3855 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3856 | } |
| 3857 | |
Chris Wilson | 93be878 | 2013-01-02 10:31:22 +0000 | [diff] [blame] | 3858 | obj->user_pin_count++; |
| 3859 | obj->pin_filp = file; |
| 3860 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3861 | args->offset = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3862 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3863 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3864 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3865 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3866 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3867 | } |
| 3868 | |
| 3869 | int |
| 3870 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3871 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3872 | { |
| 3873 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3874 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3875 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3876 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3877 | ret = i915_mutex_lock_interruptible(dev); |
| 3878 | if (ret) |
| 3879 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3880 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3881 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3882 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3883 | ret = -ENOENT; |
| 3884 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3885 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3886 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3887 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3888 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 3889 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3890 | ret = -EINVAL; |
| 3891 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3892 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3893 | obj->user_pin_count--; |
| 3894 | if (obj->user_pin_count == 0) { |
| 3895 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3896 | i915_gem_object_unpin(obj); |
| 3897 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3898 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3899 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3900 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3901 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3902 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3903 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3904 | } |
| 3905 | |
| 3906 | int |
| 3907 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3908 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3909 | { |
| 3910 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3911 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3912 | int ret; |
| 3913 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3914 | ret = i915_mutex_lock_interruptible(dev); |
| 3915 | if (ret) |
| 3916 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3917 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3918 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3919 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3920 | ret = -ENOENT; |
| 3921 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3922 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3923 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3924 | /* Count all active objects as busy, even if they are currently not used |
| 3925 | * by the gpu. Users of this interface expect objects to eventually |
| 3926 | * become non-busy without any further actions, therefore emit any |
| 3927 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 3928 | */ |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3929 | ret = i915_gem_object_flush_active(obj); |
| 3930 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3931 | args->busy = obj->active; |
Chris Wilson | e9808ed | 2012-07-04 12:25:08 +0100 | [diff] [blame] | 3932 | if (obj->ring) { |
| 3933 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
| 3934 | args->busy |= intel_ring_flag(obj->ring) << 16; |
| 3935 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3936 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3937 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3938 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3939 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3940 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3941 | } |
| 3942 | |
| 3943 | int |
| 3944 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 3945 | struct drm_file *file_priv) |
| 3946 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3947 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3948 | } |
| 3949 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3950 | int |
| 3951 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 3952 | struct drm_file *file_priv) |
| 3953 | { |
| 3954 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3955 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3956 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3957 | |
| 3958 | switch (args->madv) { |
| 3959 | case I915_MADV_DONTNEED: |
| 3960 | case I915_MADV_WILLNEED: |
| 3961 | break; |
| 3962 | default: |
| 3963 | return -EINVAL; |
| 3964 | } |
| 3965 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3966 | ret = i915_mutex_lock_interruptible(dev); |
| 3967 | if (ret) |
| 3968 | return ret; |
| 3969 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3970 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3971 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3972 | ret = -ENOENT; |
| 3973 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3974 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3975 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3976 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3977 | ret = -EINVAL; |
| 3978 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3979 | } |
| 3980 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3981 | if (obj->madv != __I915_MADV_PURGED) |
| 3982 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3983 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3984 | /* if the object is no longer attached, discard its backing storage */ |
| 3985 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3986 | i915_gem_object_truncate(obj); |
| 3987 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3988 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3989 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3990 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3991 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3992 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3993 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3994 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3995 | } |
| 3996 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3997 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 3998 | const struct drm_i915_gem_object_ops *ops) |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 3999 | { |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 4000 | INIT_LIST_HEAD(&obj->global_list); |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4001 | INIT_LIST_HEAD(&obj->ring_list); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 4002 | INIT_LIST_HEAD(&obj->obj_exec_link); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4003 | INIT_LIST_HEAD(&obj->vma_list); |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4004 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4005 | obj->ops = ops; |
| 4006 | |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4007 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4008 | obj->madv = I915_MADV_WILLNEED; |
| 4009 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 4010 | obj->map_and_fenceable = true; |
| 4011 | |
| 4012 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 4013 | } |
| 4014 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4015 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
| 4016 | .get_pages = i915_gem_object_get_pages_gtt, |
| 4017 | .put_pages = i915_gem_object_put_pages_gtt, |
| 4018 | }; |
| 4019 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4020 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 4021 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4022 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4023 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4024 | struct address_space *mapping; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 4025 | gfp_t mask; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4026 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4027 | obj = i915_gem_object_alloc(dev); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4028 | if (obj == NULL) |
| 4029 | return NULL; |
| 4030 | |
| 4031 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4032 | i915_gem_object_free(obj); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4033 | return NULL; |
| 4034 | } |
| 4035 | |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4036 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 4037 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 4038 | /* 965gm cannot relocate objects above 4GiB. */ |
| 4039 | mask &= ~__GFP_HIGHMEM; |
| 4040 | mask |= __GFP_DMA32; |
| 4041 | } |
| 4042 | |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4043 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4044 | mapping_set_gfp_mask(mapping, mask); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4045 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4046 | i915_gem_object_init(obj, &i915_gem_object_ops); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4047 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4048 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4049 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4050 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 4051 | if (HAS_LLC(dev)) { |
| 4052 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 4053 | * cache) for about a 10% performance improvement |
| 4054 | * compared to uncached. Graphics requests other than |
| 4055 | * display scanout are coherent with the CPU in |
| 4056 | * accessing this cache. This means in this mode we |
| 4057 | * don't need to clflush on the CPU side, and on the |
| 4058 | * GPU side we only need to flush internal caches to |
| 4059 | * get data visible to the CPU. |
| 4060 | * |
| 4061 | * However, we maintain the display planes as UC, and so |
| 4062 | * need to rebind when first used as such. |
| 4063 | */ |
| 4064 | obj->cache_level = I915_CACHE_LLC; |
| 4065 | } else |
| 4066 | obj->cache_level = I915_CACHE_NONE; |
| 4067 | |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 4068 | trace_i915_gem_object_create(obj); |
| 4069 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4070 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4071 | } |
| 4072 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4073 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4074 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4075 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4076 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4077 | return 0; |
| 4078 | } |
| 4079 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4080 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4081 | { |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4082 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4083 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4084 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4085 | struct i915_vma *vma, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4086 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 4087 | trace_i915_gem_object_destroy(obj); |
| 4088 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4089 | if (obj->phys_obj) |
| 4090 | i915_gem_detach_phys_object(dev, obj); |
| 4091 | |
| 4092 | obj->pin_count = 0; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4093 | /* NB: 0 or 1 elements */ |
| 4094 | WARN_ON(!list_empty(&obj->vma_list) && |
| 4095 | !list_is_singular(&obj->vma_list)); |
| 4096 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
| 4097 | int ret = i915_vma_unbind(vma); |
| 4098 | if (WARN_ON(ret == -ERESTARTSYS)) { |
| 4099 | bool was_interruptible; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4100 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4101 | was_interruptible = dev_priv->mm.interruptible; |
| 4102 | dev_priv->mm.interruptible = false; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4103 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4104 | WARN_ON(i915_vma_unbind(vma)); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4105 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4106 | dev_priv->mm.interruptible = was_interruptible; |
| 4107 | } |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4108 | } |
| 4109 | |
Ben Widawsky | 1d64ae7 | 2013-05-31 14:46:20 -0700 | [diff] [blame] | 4110 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
| 4111 | * before progressing. */ |
| 4112 | if (obj->stolen) |
| 4113 | i915_gem_object_unpin_pages(obj); |
| 4114 | |
Ben Widawsky | 401c29f | 2013-05-31 11:28:47 -0700 | [diff] [blame] | 4115 | if (WARN_ON(obj->pages_pin_count)) |
| 4116 | obj->pages_pin_count = 0; |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4117 | i915_gem_object_put_pages(obj); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 4118 | i915_gem_object_free_mmap_offset(obj); |
Chris Wilson | 0104fdb | 2012-11-15 11:32:26 +0000 | [diff] [blame] | 4119 | i915_gem_object_release_stolen(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4120 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 4121 | BUG_ON(obj->pages); |
| 4122 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 4123 | if (obj->base.import_attach) |
| 4124 | drm_prime_gem_destroy(&obj->base, NULL); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4125 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4126 | drm_gem_object_release(&obj->base); |
| 4127 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4128 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4129 | kfree(obj->bit_17); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4130 | i915_gem_object_free(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4131 | } |
| 4132 | |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4133 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4134 | struct i915_address_space *vm) |
| 4135 | { |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4136 | struct i915_vma *vma; |
| 4137 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 4138 | if (vma->vm == vm) |
| 4139 | return vma; |
| 4140 | |
| 4141 | return NULL; |
| 4142 | } |
| 4143 | |
| 4144 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, |
| 4145 | struct i915_address_space *vm) |
| 4146 | { |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4147 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); |
| 4148 | if (vma == NULL) |
| 4149 | return ERR_PTR(-ENOMEM); |
| 4150 | |
| 4151 | INIT_LIST_HEAD(&vma->vma_link); |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 4152 | INIT_LIST_HEAD(&vma->mm_list); |
Ben Widawsky | 82a55ad | 2013-08-14 11:38:34 +0200 | [diff] [blame] | 4153 | INIT_LIST_HEAD(&vma->exec_list); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4154 | vma->vm = vm; |
| 4155 | vma->obj = obj; |
| 4156 | |
Ben Widawsky | 8b9c2b9 | 2013-07-31 17:00:16 -0700 | [diff] [blame] | 4157 | /* Keep GGTT vmas first to make debug easier */ |
| 4158 | if (i915_is_ggtt(vm)) |
| 4159 | list_add(&vma->vma_link, &obj->vma_list); |
| 4160 | else |
| 4161 | list_add_tail(&vma->vma_link, &obj->vma_list); |
| 4162 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4163 | return vma; |
| 4164 | } |
| 4165 | |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4166 | struct i915_vma * |
| 4167 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
| 4168 | struct i915_address_space *vm) |
| 4169 | { |
| 4170 | struct i915_vma *vma; |
| 4171 | |
| 4172 | vma = i915_gem_obj_to_vma(obj, vm); |
| 4173 | if (!vma) |
| 4174 | vma = __i915_gem_vma_create(obj, vm); |
| 4175 | |
| 4176 | return vma; |
| 4177 | } |
| 4178 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4179 | void i915_gem_vma_destroy(struct i915_vma *vma) |
| 4180 | { |
| 4181 | WARN_ON(vma->node.allocated); |
Chris Wilson | aaa0566 | 2013-08-20 12:56:40 +0100 | [diff] [blame] | 4182 | |
| 4183 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ |
| 4184 | if (!list_empty(&vma->exec_list)) |
| 4185 | return; |
| 4186 | |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 4187 | list_del(&vma->vma_link); |
| 4188 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4189 | kfree(vma); |
| 4190 | } |
| 4191 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4192 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4193 | i915_gem_idle(struct drm_device *dev) |
| 4194 | { |
| 4195 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4196 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4197 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4198 | if (dev_priv->ums.mm_suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4199 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4200 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4201 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4202 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4203 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4204 | if (ret) { |
| 4205 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4206 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4207 | } |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4208 | i915_gem_retire_requests(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4209 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4210 | /* Under UMS, be paranoid and evict. */ |
Chris Wilson | a39d7ef | 2012-04-24 18:22:52 +0100 | [diff] [blame] | 4211 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4212 | i915_gem_evict_everything(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4213 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 4214 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4215 | |
| 4216 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4217 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4218 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4219 | /* Cancel the retire work handler, which should be idle now. */ |
| 4220 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4221 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4222 | return 0; |
| 4223 | } |
| 4224 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame^] | 4225 | void i915_gem_l3_remap(struct drm_device *dev, int slice) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4226 | { |
| 4227 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame^] | 4228 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
| 4229 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4230 | u32 misccpctl; |
| 4231 | int i; |
| 4232 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame^] | 4233 | if (!HAS_L3_GPU_CACHE(dev) || !remap_info) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4234 | return; |
| 4235 | |
| 4236 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 4237 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 4238 | POSTING_READ(GEN7_MISCCPCTL); |
| 4239 | |
| 4240 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame^] | 4241 | u32 remap = I915_READ(reg_base + i); |
| 4242 | if (remap && remap != remap_info[i/4]) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4243 | DRM_DEBUG("0x%x was already programmed to %x\n", |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame^] | 4244 | reg_base + i, remap); |
| 4245 | if (remap && !remap_info[i/4]) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4246 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame^] | 4247 | I915_WRITE(reg_base + i, remap_info[i/4]); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4248 | } |
| 4249 | |
| 4250 | /* Make sure all the writes land before disabling dop clock gating */ |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame^] | 4251 | POSTING_READ(reg_base); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4252 | |
| 4253 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 4254 | } |
| 4255 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4256 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 4257 | { |
| 4258 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4259 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4260 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4261 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 4262 | return; |
| 4263 | |
| 4264 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 4265 | DISP_TILE_SURFACE_SWIZZLING); |
| 4266 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4267 | if (IS_GEN5(dev)) |
| 4268 | return; |
| 4269 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4270 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 4271 | if (IS_GEN6(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4272 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4273 | else if (IS_GEN7(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4274 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4275 | else |
| 4276 | BUG(); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4277 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4278 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 4279 | static bool |
| 4280 | intel_enable_blt(struct drm_device *dev) |
| 4281 | { |
| 4282 | if (!HAS_BLT(dev)) |
| 4283 | return false; |
| 4284 | |
| 4285 | /* The blitter was dysfunctional on early prototypes */ |
| 4286 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
| 4287 | DRM_INFO("BLT not supported on this pre-production hardware;" |
| 4288 | " graphics performance will be degraded.\n"); |
| 4289 | return false; |
| 4290 | } |
| 4291 | |
| 4292 | return true; |
| 4293 | } |
| 4294 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4295 | static int i915_gem_init_rings(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4296 | { |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4297 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4298 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4299 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4300 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4301 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 4302 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4303 | |
| 4304 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4305 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4306 | if (ret) |
| 4307 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4308 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4309 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 4310 | if (intel_enable_blt(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4311 | ret = intel_init_blt_ring_buffer(dev); |
| 4312 | if (ret) |
| 4313 | goto cleanup_bsd_ring; |
| 4314 | } |
| 4315 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4316 | if (HAS_VEBOX(dev)) { |
| 4317 | ret = intel_init_vebox_ring_buffer(dev); |
| 4318 | if (ret) |
| 4319 | goto cleanup_blt_ring; |
| 4320 | } |
| 4321 | |
| 4322 | |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4323 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
| 4324 | if (ret) |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4325 | goto cleanup_vebox_ring; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4326 | |
| 4327 | return 0; |
| 4328 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4329 | cleanup_vebox_ring: |
| 4330 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4331 | cleanup_blt_ring: |
| 4332 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
| 4333 | cleanup_bsd_ring: |
| 4334 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
| 4335 | cleanup_render_ring: |
| 4336 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
| 4337 | |
| 4338 | return ret; |
| 4339 | } |
| 4340 | |
| 4341 | int |
| 4342 | i915_gem_init_hw(struct drm_device *dev) |
| 4343 | { |
| 4344 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame^] | 4345 | int ret, i; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4346 | |
| 4347 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
| 4348 | return -EIO; |
| 4349 | |
Ben Widawsky | 5912450 | 2013-07-04 11:02:05 -0700 | [diff] [blame] | 4350 | if (dev_priv->ellc_size) |
Ben Widawsky | 05e21cc | 2013-07-04 11:02:04 -0700 | [diff] [blame] | 4351 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4352 | |
Rodrigo Vivi | 9435373 | 2013-08-28 16:45:46 -0300 | [diff] [blame] | 4353 | if (IS_HSW_GT3(dev)) |
| 4354 | I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); |
| 4355 | else |
| 4356 | I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); |
| 4357 | |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 4358 | if (HAS_PCH_NOP(dev)) { |
| 4359 | u32 temp = I915_READ(GEN7_MSG_CTL); |
| 4360 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
| 4361 | I915_WRITE(GEN7_MSG_CTL, temp); |
| 4362 | } |
| 4363 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame^] | 4364 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
| 4365 | i915_gem_l3_remap(dev, i); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4366 | |
| 4367 | i915_gem_init_swizzling(dev); |
| 4368 | |
| 4369 | ret = i915_gem_init_rings(dev); |
| 4370 | if (ret) |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4371 | return ret; |
| 4372 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 4373 | /* |
| 4374 | * XXX: There was some w/a described somewhere suggesting loading |
| 4375 | * contexts before PPGTT. |
| 4376 | */ |
| 4377 | i915_gem_context_init(dev); |
Ben Widawsky | b7c36d2 | 2013-04-08 18:43:56 -0700 | [diff] [blame] | 4378 | if (dev_priv->mm.aliasing_ppgtt) { |
| 4379 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); |
| 4380 | if (ret) { |
| 4381 | i915_gem_cleanup_aliasing_ppgtt(dev); |
| 4382 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); |
| 4383 | } |
| 4384 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4385 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4386 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4387 | } |
| 4388 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4389 | int i915_gem_init(struct drm_device *dev) |
| 4390 | { |
| 4391 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4392 | int ret; |
| 4393 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4394 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4395 | |
| 4396 | if (IS_VALLEYVIEW(dev)) { |
| 4397 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
| 4398 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); |
| 4399 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) |
| 4400 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
| 4401 | } |
| 4402 | |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 4403 | i915_gem_init_global_gtt(dev); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4404 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4405 | ret = i915_gem_init_hw(dev); |
| 4406 | mutex_unlock(&dev->struct_mutex); |
| 4407 | if (ret) { |
| 4408 | i915_gem_cleanup_aliasing_ppgtt(dev); |
| 4409 | return ret; |
| 4410 | } |
| 4411 | |
Daniel Vetter | 53ca26c | 2012-04-26 23:28:03 +0200 | [diff] [blame] | 4412 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
| 4413 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4414 | dev_priv->dri1.allow_batchbuffer = 1; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4415 | return 0; |
| 4416 | } |
| 4417 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4418 | void |
| 4419 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4420 | { |
| 4421 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4422 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4423 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4424 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4425 | for_each_ring(ring, dev_priv, i) |
| 4426 | intel_cleanup_ring_buffer(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4427 | } |
| 4428 | |
| 4429 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4430 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4431 | struct drm_file *file_priv) |
| 4432 | { |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4433 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4434 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4435 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4436 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4437 | return 0; |
| 4438 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4439 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4440 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4441 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4442 | } |
| 4443 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4444 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4445 | dev_priv->ums.mm_suspended = 0; |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4446 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4447 | ret = i915_gem_init_hw(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4448 | if (ret != 0) { |
| 4449 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4450 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4451 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4452 | |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 4453 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4454 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4455 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4456 | ret = drm_irq_install(dev); |
| 4457 | if (ret) |
| 4458 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4459 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4460 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4461 | |
| 4462 | cleanup_ringbuffer: |
| 4463 | mutex_lock(&dev->struct_mutex); |
| 4464 | i915_gem_cleanup_ringbuffer(dev); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4465 | dev_priv->ums.mm_suspended = 1; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4466 | mutex_unlock(&dev->struct_mutex); |
| 4467 | |
| 4468 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4469 | } |
| 4470 | |
| 4471 | int |
| 4472 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4473 | struct drm_file *file_priv) |
| 4474 | { |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4475 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4476 | int ret; |
| 4477 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4478 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4479 | return 0; |
| 4480 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4481 | drm_irq_uninstall(dev); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4482 | |
| 4483 | mutex_lock(&dev->struct_mutex); |
| 4484 | ret = i915_gem_idle(dev); |
| 4485 | |
| 4486 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4487 | * We need to replace this with a semaphore, or something. |
| 4488 | * And not confound ums.mm_suspended! |
| 4489 | */ |
| 4490 | if (ret != 0) |
| 4491 | dev_priv->ums.mm_suspended = 1; |
| 4492 | mutex_unlock(&dev->struct_mutex); |
| 4493 | |
| 4494 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4495 | } |
| 4496 | |
| 4497 | void |
| 4498 | i915_gem_lastclose(struct drm_device *dev) |
| 4499 | { |
| 4500 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4501 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4502 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4503 | return; |
| 4504 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4505 | mutex_lock(&dev->struct_mutex); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4506 | ret = i915_gem_idle(dev); |
| 4507 | if (ret) |
| 4508 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4509 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4510 | } |
| 4511 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4512 | static void |
| 4513 | init_ring_lists(struct intel_ring_buffer *ring) |
| 4514 | { |
| 4515 | INIT_LIST_HEAD(&ring->active_list); |
| 4516 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4517 | } |
| 4518 | |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4519 | static void i915_init_vm(struct drm_i915_private *dev_priv, |
| 4520 | struct i915_address_space *vm) |
| 4521 | { |
| 4522 | vm->dev = dev_priv->dev; |
| 4523 | INIT_LIST_HEAD(&vm->active_list); |
| 4524 | INIT_LIST_HEAD(&vm->inactive_list); |
| 4525 | INIT_LIST_HEAD(&vm->global_link); |
| 4526 | list_add(&vm->global_link, &dev_priv->vm_list); |
| 4527 | } |
| 4528 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4529 | void |
| 4530 | i915_gem_load(struct drm_device *dev) |
| 4531 | { |
| 4532 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4533 | int i; |
| 4534 | |
| 4535 | dev_priv->slab = |
| 4536 | kmem_cache_create("i915_gem_object", |
| 4537 | sizeof(struct drm_i915_gem_object), 0, |
| 4538 | SLAB_HWCACHE_ALIGN, |
| 4539 | NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4540 | |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4541 | INIT_LIST_HEAD(&dev_priv->vm_list); |
| 4542 | i915_init_vm(dev_priv, &dev_priv->gtt.base); |
| 4543 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4544 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 4545 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4546 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4547 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 4548 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 4549 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4550 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4551 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4552 | i915_gem_retire_work_handler); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4553 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4554 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4555 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4556 | if (IS_GEN3(dev)) { |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 4557 | I915_WRITE(MI_ARB_STATE, |
| 4558 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4559 | } |
| 4560 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 4561 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 4562 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4563 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4564 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4565 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4566 | |
Ville Syrjälä | 42b5aea | 2013-04-09 13:02:47 +0300 | [diff] [blame] | 4567 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
| 4568 | dev_priv->num_fence_regs = 32; |
| 4569 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4570 | dev_priv->num_fence_regs = 16; |
| 4571 | else |
| 4572 | dev_priv->num_fence_regs = 8; |
| 4573 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4574 | /* Initialize fence registers to zero */ |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 4575 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
| 4576 | i915_gem_restore_fences(dev); |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 4577 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4578 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4579 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4580 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 4581 | dev_priv->mm.interruptible = true; |
| 4582 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4583 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 4584 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 4585 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4586 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4587 | |
| 4588 | /* |
| 4589 | * Create a physically contiguous memory object for this object |
| 4590 | * e.g. for cursor + overlay regs |
| 4591 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4592 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 4593 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4594 | { |
| 4595 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4596 | struct drm_i915_gem_phys_object *phys_obj; |
| 4597 | int ret; |
| 4598 | |
| 4599 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4600 | return 0; |
| 4601 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4602 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4603 | if (!phys_obj) |
| 4604 | return -ENOMEM; |
| 4605 | |
| 4606 | phys_obj->id = id; |
| 4607 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4608 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4609 | if (!phys_obj->handle) { |
| 4610 | ret = -ENOMEM; |
| 4611 | goto kfree_obj; |
| 4612 | } |
| 4613 | #ifdef CONFIG_X86 |
| 4614 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4615 | #endif |
| 4616 | |
| 4617 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4618 | |
| 4619 | return 0; |
| 4620 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4621 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4622 | return ret; |
| 4623 | } |
| 4624 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4625 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4626 | { |
| 4627 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4628 | struct drm_i915_gem_phys_object *phys_obj; |
| 4629 | |
| 4630 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4631 | return; |
| 4632 | |
| 4633 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4634 | if (phys_obj->cur_obj) { |
| 4635 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4636 | } |
| 4637 | |
| 4638 | #ifdef CONFIG_X86 |
| 4639 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4640 | #endif |
| 4641 | drm_pci_free(dev, phys_obj->handle); |
| 4642 | kfree(phys_obj); |
| 4643 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4644 | } |
| 4645 | |
| 4646 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4647 | { |
| 4648 | int i; |
| 4649 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4650 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4651 | i915_gem_free_phys_object(dev, i); |
| 4652 | } |
| 4653 | |
| 4654 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4655 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4656 | { |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4657 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4658 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4659 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4660 | int page_count; |
| 4661 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4662 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4663 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4664 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4665 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4666 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4667 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4668 | struct page *page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4669 | if (!IS_ERR(page)) { |
| 4670 | char *dst = kmap_atomic(page); |
| 4671 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 4672 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4673 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4674 | drm_clflush_pages(&page, 1); |
| 4675 | |
| 4676 | set_page_dirty(page); |
| 4677 | mark_page_accessed(page); |
| 4678 | page_cache_release(page); |
| 4679 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4680 | } |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 4681 | i915_gem_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4682 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4683 | obj->phys_obj->cur_obj = NULL; |
| 4684 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4685 | } |
| 4686 | |
| 4687 | int |
| 4688 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4689 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4690 | int id, |
| 4691 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4692 | { |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4693 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4694 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4695 | int ret = 0; |
| 4696 | int page_count; |
| 4697 | int i; |
| 4698 | |
| 4699 | if (id > I915_MAX_PHYS_OBJECT) |
| 4700 | return -EINVAL; |
| 4701 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4702 | if (obj->phys_obj) { |
| 4703 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4704 | return 0; |
| 4705 | i915_gem_detach_phys_object(dev, obj); |
| 4706 | } |
| 4707 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4708 | /* create a new object */ |
| 4709 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4710 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4711 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4712 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4713 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 4714 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4715 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4716 | } |
| 4717 | } |
| 4718 | |
| 4719 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4720 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4721 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4722 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4723 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4724 | |
| 4725 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4726 | struct page *page; |
| 4727 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4728 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4729 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4730 | if (IS_ERR(page)) |
| 4731 | return PTR_ERR(page); |
| 4732 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 4733 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4734 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4735 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4736 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4737 | |
| 4738 | mark_page_accessed(page); |
| 4739 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4740 | } |
| 4741 | |
| 4742 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4743 | } |
| 4744 | |
| 4745 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4746 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 4747 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4748 | struct drm_i915_gem_pwrite *args, |
| 4749 | struct drm_file *file_priv) |
| 4750 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4751 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 4752 | char __user *user_data = to_user_ptr(args->data_ptr); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4753 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 4754 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 4755 | unsigned long unwritten; |
| 4756 | |
| 4757 | /* The physical object once assigned is fixed for the lifetime |
| 4758 | * of the obj, so we can safely drop the lock and continue |
| 4759 | * to access vaddr. |
| 4760 | */ |
| 4761 | mutex_unlock(&dev->struct_mutex); |
| 4762 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 4763 | mutex_lock(&dev->struct_mutex); |
| 4764 | if (unwritten) |
| 4765 | return -EFAULT; |
| 4766 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4767 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 4768 | i915_gem_chipset_flush(dev); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4769 | return 0; |
| 4770 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4771 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4772 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4773 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4774 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4775 | |
| 4776 | /* Clean up our request list when the client is going away, so that |
| 4777 | * later retire_requests won't dereference our soon-to-be-gone |
| 4778 | * file_priv. |
| 4779 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4780 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4781 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4782 | struct drm_i915_gem_request *request; |
| 4783 | |
| 4784 | request = list_first_entry(&file_priv->mm.request_list, |
| 4785 | struct drm_i915_gem_request, |
| 4786 | client_list); |
| 4787 | list_del(&request->client_list); |
| 4788 | request->file_priv = NULL; |
| 4789 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4790 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4791 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4792 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4793 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
| 4794 | { |
| 4795 | if (!mutex_is_locked(mutex)) |
| 4796 | return false; |
| 4797 | |
| 4798 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) |
| 4799 | return mutex->owner == task; |
| 4800 | #else |
| 4801 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ |
| 4802 | return false; |
| 4803 | #endif |
| 4804 | } |
| 4805 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4806 | static int |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4807 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4808 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4809 | struct drm_i915_private *dev_priv = |
| 4810 | container_of(shrinker, |
| 4811 | struct drm_i915_private, |
| 4812 | mm.inactive_shrinker); |
| 4813 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4814 | struct drm_i915_gem_object *obj; |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4815 | int nr_to_scan = sc->nr_to_scan; |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4816 | bool unlock = true; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4817 | int cnt; |
| 4818 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4819 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 4820 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) |
| 4821 | return 0; |
| 4822 | |
Daniel Vetter | 677feac | 2012-12-19 14:33:45 +0100 | [diff] [blame] | 4823 | if (dev_priv->mm.shrinker_no_lock_stealing) |
| 4824 | return 0; |
| 4825 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4826 | unlock = false; |
| 4827 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4828 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4829 | if (nr_to_scan) { |
| 4830 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); |
| 4831 | if (nr_to_scan > 0) |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 4832 | nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan, |
| 4833 | false); |
| 4834 | if (nr_to_scan > 0) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4835 | i915_gem_shrink_all(dev_priv); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4836 | } |
| 4837 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4838 | cnt = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 4839 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 4840 | if (obj->pages_pin_count == 0) |
| 4841 | cnt += obj->base.size >> PAGE_SHIFT; |
Ben Widawsky | fcb4a57 | 2013-07-31 16:59:57 -0700 | [diff] [blame] | 4842 | |
| 4843 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 4844 | if (obj->active) |
| 4845 | continue; |
| 4846 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 4847 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4848 | cnt += obj->base.size >> PAGE_SHIFT; |
Ben Widawsky | fcb4a57 | 2013-07-31 16:59:57 -0700 | [diff] [blame] | 4849 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4850 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4851 | if (unlock) |
| 4852 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4853 | return cnt; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4854 | } |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 4855 | |
| 4856 | /* All the new VM stuff */ |
| 4857 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 4858 | struct i915_address_space *vm) |
| 4859 | { |
| 4860 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 4861 | struct i915_vma *vma; |
| 4862 | |
| 4863 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) |
| 4864 | vm = &dev_priv->gtt.base; |
| 4865 | |
| 4866 | BUG_ON(list_empty(&o->vma_list)); |
| 4867 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
| 4868 | if (vma->vm == vm) |
| 4869 | return vma->node.start; |
| 4870 | |
| 4871 | } |
| 4872 | return -1; |
| 4873 | } |
| 4874 | |
| 4875 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 4876 | struct i915_address_space *vm) |
| 4877 | { |
| 4878 | struct i915_vma *vma; |
| 4879 | |
| 4880 | list_for_each_entry(vma, &o->vma_list, vma_link) |
Ben Widawsky | 8b9c2b9 | 2013-07-31 17:00:16 -0700 | [diff] [blame] | 4881 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 4882 | return true; |
| 4883 | |
| 4884 | return false; |
| 4885 | } |
| 4886 | |
| 4887 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
| 4888 | { |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 4889 | struct i915_vma *vma; |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 4890 | |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 4891 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 4892 | if (drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 4893 | return true; |
| 4894 | |
| 4895 | return false; |
| 4896 | } |
| 4897 | |
| 4898 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
| 4899 | struct i915_address_space *vm) |
| 4900 | { |
| 4901 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 4902 | struct i915_vma *vma; |
| 4903 | |
| 4904 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) |
| 4905 | vm = &dev_priv->gtt.base; |
| 4906 | |
| 4907 | BUG_ON(list_empty(&o->vma_list)); |
| 4908 | |
| 4909 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 4910 | if (vma->vm == vm) |
| 4911 | return vma->node.size; |
| 4912 | |
| 4913 | return 0; |
| 4914 | } |