Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
| 29 | #include <drm/i915_drm.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 30 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 31 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 32 | #include "intel_drv.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 33 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 35 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include <linux/pci.h> |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 37 | #include <linux/dma-buf.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 41 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
| 42 | unsigned alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 43 | bool map_and_fenceable, |
| 44 | bool nonblocking); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 46 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 47 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 48 | struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 49 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 51 | struct drm_i915_gem_object *obj); |
| 52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 53 | struct drm_i915_fence_reg *fence, |
| 54 | bool enable); |
| 55 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 57 | struct shrink_control *sc); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 58 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
| 59 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 60 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 61 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 62 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 63 | { |
| 64 | if (obj->tiling_mode) |
| 65 | i915_gem_release_mmap(obj); |
| 66 | |
| 67 | /* As we do not have an associated fence register, we will force |
| 68 | * a tiling change if we ever need to acquire one. |
| 69 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 70 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 71 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 72 | } |
| 73 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 74 | /* some bookkeeping */ |
| 75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 76 | size_t size) |
| 77 | { |
| 78 | dev_priv->mm.object_count++; |
| 79 | dev_priv->mm.object_memory += size; |
| 80 | } |
| 81 | |
| 82 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 83 | size_t size) |
| 84 | { |
| 85 | dev_priv->mm.object_count--; |
| 86 | dev_priv->mm.object_memory -= size; |
| 87 | } |
| 88 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 89 | static int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 90 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 91 | { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 92 | int ret; |
| 93 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 94 | #define EXIT_COND (!i915_reset_in_progress(error)) |
| 95 | if (EXIT_COND) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 96 | return 0; |
| 97 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 98 | /* GPU is already declared terminally dead, give up. */ |
| 99 | if (i915_terminally_wedged(error)) |
| 100 | return -EIO; |
| 101 | |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 102 | /* |
| 103 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 104 | * userspace. If it takes that long something really bad is going on and |
| 105 | * we should simply try to bail out and fail as gracefully as possible. |
| 106 | */ |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 107 | ret = wait_event_interruptible_timeout(error->reset_queue, |
| 108 | EXIT_COND, |
| 109 | 10*HZ); |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 110 | if (ret == 0) { |
| 111 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 112 | return -EIO; |
| 113 | } else if (ret < 0) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 114 | return ret; |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 115 | } |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 116 | #undef EXIT_COND |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 117 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 118 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 119 | } |
| 120 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 121 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 122 | { |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 123 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 124 | int ret; |
| 125 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 126 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 127 | if (ret) |
| 128 | return ret; |
| 129 | |
| 130 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 131 | if (ret) |
| 132 | return ret; |
| 133 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 134 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 135 | return 0; |
| 136 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 137 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 138 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 139 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 140 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 141 | return obj->gtt_space && !obj->active; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 142 | } |
| 143 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 144 | int |
| 145 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 146 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 147 | { |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 148 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 149 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 150 | |
Daniel Vetter | 7bb6fb8 | 2012-04-24 08:22:52 +0200 | [diff] [blame] | 151 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 152 | return -ENODEV; |
| 153 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 154 | if (args->gtt_start >= args->gtt_end || |
| 155 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 156 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 157 | |
Daniel Vetter | f534bc0 | 2012-03-26 22:37:04 +0200 | [diff] [blame] | 158 | /* GEM with user mode setting was never supported on ilk and later. */ |
| 159 | if (INTEL_INFO(dev)->gen >= 5) |
| 160 | return -ENODEV; |
| 161 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 162 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 163 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
| 164 | args->gtt_end); |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 165 | dev_priv->gtt.mappable_end = args->gtt_end; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 166 | mutex_unlock(&dev->struct_mutex); |
| 167 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 168 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 169 | } |
| 170 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 171 | int |
| 172 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 173 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 174 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 175 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 176 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 177 | struct drm_i915_gem_object *obj; |
| 178 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 179 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 180 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 181 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 182 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 183 | if (obj->pin_count) |
| 184 | pinned += obj->gtt_space->size; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 185 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 186 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 187 | args->aper_size = dev_priv->gtt.total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 188 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 189 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 190 | return 0; |
| 191 | } |
| 192 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 193 | void *i915_gem_object_alloc(struct drm_device *dev) |
| 194 | { |
| 195 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 196 | return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO); |
| 197 | } |
| 198 | |
| 199 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
| 200 | { |
| 201 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 202 | kmem_cache_free(dev_priv->slab, obj); |
| 203 | } |
| 204 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 205 | static int |
| 206 | i915_gem_create(struct drm_file *file, |
| 207 | struct drm_device *dev, |
| 208 | uint64_t size, |
| 209 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 210 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 211 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 212 | int ret; |
| 213 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 214 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 215 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 216 | if (size == 0) |
| 217 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 218 | |
| 219 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 220 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 221 | if (obj == NULL) |
| 222 | return -ENOMEM; |
| 223 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 224 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 225 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 226 | drm_gem_object_release(&obj->base); |
| 227 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 228 | i915_gem_object_free(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 229 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 230 | } |
| 231 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 232 | /* drop reference from allocate - handle holds it now */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 233 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 234 | trace_i915_gem_object_create(obj); |
| 235 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 236 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 237 | return 0; |
| 238 | } |
| 239 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 240 | int |
| 241 | i915_gem_dumb_create(struct drm_file *file, |
| 242 | struct drm_device *dev, |
| 243 | struct drm_mode_create_dumb *args) |
| 244 | { |
| 245 | /* have to work out size/pitch and return them */ |
Chris Wilson | ed0291f | 2011-03-19 08:21:45 +0000 | [diff] [blame] | 246 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 247 | args->size = args->pitch * args->height; |
| 248 | return i915_gem_create(file, dev, |
| 249 | args->size, &args->handle); |
| 250 | } |
| 251 | |
| 252 | int i915_gem_dumb_destroy(struct drm_file *file, |
| 253 | struct drm_device *dev, |
| 254 | uint32_t handle) |
| 255 | { |
| 256 | return drm_gem_handle_delete(file, handle); |
| 257 | } |
| 258 | |
| 259 | /** |
| 260 | * Creates a new mm object and returns a handle to it. |
| 261 | */ |
| 262 | int |
| 263 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 264 | struct drm_file *file) |
| 265 | { |
| 266 | struct drm_i915_gem_create *args = data; |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 267 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 268 | return i915_gem_create(file, dev, |
| 269 | args->size, &args->handle); |
| 270 | } |
| 271 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 272 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 273 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 274 | const char *gpu_vaddr, int gpu_offset, |
| 275 | int length) |
| 276 | { |
| 277 | int ret, cpu_offset = 0; |
| 278 | |
| 279 | while (length > 0) { |
| 280 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 281 | int this_length = min(cacheline_end - gpu_offset, length); |
| 282 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 283 | |
| 284 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 285 | gpu_vaddr + swizzled_gpu_offset, |
| 286 | this_length); |
| 287 | if (ret) |
| 288 | return ret + length; |
| 289 | |
| 290 | cpu_offset += this_length; |
| 291 | gpu_offset += this_length; |
| 292 | length -= this_length; |
| 293 | } |
| 294 | |
| 295 | return 0; |
| 296 | } |
| 297 | |
| 298 | static inline int |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 299 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 300 | const char __user *cpu_vaddr, |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 301 | int length) |
| 302 | { |
| 303 | int ret, cpu_offset = 0; |
| 304 | |
| 305 | while (length > 0) { |
| 306 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 307 | int this_length = min(cacheline_end - gpu_offset, length); |
| 308 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 309 | |
| 310 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 311 | cpu_vaddr + cpu_offset, |
| 312 | this_length); |
| 313 | if (ret) |
| 314 | return ret + length; |
| 315 | |
| 316 | cpu_offset += this_length; |
| 317 | gpu_offset += this_length; |
| 318 | length -= this_length; |
| 319 | } |
| 320 | |
| 321 | return 0; |
| 322 | } |
| 323 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 324 | /* Per-page copy function for the shmem pread fastpath. |
| 325 | * Flushes invalid cachelines before reading the target if |
| 326 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 327 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 328 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 329 | char __user *user_data, |
| 330 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 331 | { |
| 332 | char *vaddr; |
| 333 | int ret; |
| 334 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 335 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 336 | return -EINVAL; |
| 337 | |
| 338 | vaddr = kmap_atomic(page); |
| 339 | if (needs_clflush) |
| 340 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 341 | page_length); |
| 342 | ret = __copy_to_user_inatomic(user_data, |
| 343 | vaddr + shmem_page_offset, |
| 344 | page_length); |
| 345 | kunmap_atomic(vaddr); |
| 346 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 347 | return ret ? -EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 348 | } |
| 349 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 350 | static void |
| 351 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 352 | bool swizzled) |
| 353 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 354 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 355 | unsigned long start = (unsigned long) addr; |
| 356 | unsigned long end = (unsigned long) addr + length; |
| 357 | |
| 358 | /* For swizzling simply ensure that we always flush both |
| 359 | * channels. Lame, but simple and it works. Swizzled |
| 360 | * pwrite/pread is far from a hotpath - current userspace |
| 361 | * doesn't use it at all. */ |
| 362 | start = round_down(start, 128); |
| 363 | end = round_up(end, 128); |
| 364 | |
| 365 | drm_clflush_virt_range((void *)start, end - start); |
| 366 | } else { |
| 367 | drm_clflush_virt_range(addr, length); |
| 368 | } |
| 369 | |
| 370 | } |
| 371 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 372 | /* Only difference to the fast-path function is that this can handle bit17 |
| 373 | * and uses non-atomic copy and kmap functions. */ |
| 374 | static int |
| 375 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 376 | char __user *user_data, |
| 377 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 378 | { |
| 379 | char *vaddr; |
| 380 | int ret; |
| 381 | |
| 382 | vaddr = kmap(page); |
| 383 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 384 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 385 | page_length, |
| 386 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 387 | |
| 388 | if (page_do_bit17_swizzling) |
| 389 | ret = __copy_to_user_swizzled(user_data, |
| 390 | vaddr, shmem_page_offset, |
| 391 | page_length); |
| 392 | else |
| 393 | ret = __copy_to_user(user_data, |
| 394 | vaddr + shmem_page_offset, |
| 395 | page_length); |
| 396 | kunmap(page); |
| 397 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 398 | return ret ? - EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 399 | } |
| 400 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 401 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 402 | i915_gem_shmem_pread(struct drm_device *dev, |
| 403 | struct drm_i915_gem_object *obj, |
| 404 | struct drm_i915_gem_pread *args, |
| 405 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 406 | { |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 407 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 408 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 409 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 410 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 411 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 412 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 413 | int needs_clflush = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 414 | struct sg_page_iter sg_iter; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 415 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 416 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 417 | remain = args->size; |
| 418 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 419 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 420 | |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 421 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 422 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 423 | * read domain and manually flush cachelines (if required). This |
| 424 | * optimizes for the case when the gpu will dirty the data |
| 425 | * anyway again before the next pread happens. */ |
| 426 | if (obj->cache_level == I915_CACHE_NONE) |
| 427 | needs_clflush = 1; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 428 | if (obj->gtt_space) { |
| 429 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
| 430 | if (ret) |
| 431 | return ret; |
| 432 | } |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 433 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 434 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 435 | ret = i915_gem_object_get_pages(obj); |
| 436 | if (ret) |
| 437 | return ret; |
| 438 | |
| 439 | i915_gem_object_pin_pages(obj); |
| 440 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 441 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 442 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 443 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 444 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 445 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 446 | |
| 447 | if (remain <= 0) |
| 448 | break; |
| 449 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 450 | /* Operation in this page |
| 451 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 452 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 453 | * page_length = bytes to copy for this page |
| 454 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 455 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 456 | page_length = remain; |
| 457 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 458 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 459 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 460 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 461 | (page_to_phys(page) & (1 << 17)) != 0; |
| 462 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 463 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 464 | user_data, page_do_bit17_swizzling, |
| 465 | needs_clflush); |
| 466 | if (ret == 0) |
| 467 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 468 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 469 | mutex_unlock(&dev->struct_mutex); |
| 470 | |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 471 | if (!prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 472 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 473 | /* Userspace is tricking us, but we've already clobbered |
| 474 | * its pages with the prefault and promised to write the |
| 475 | * data up to the first fault. Hence ignore any errors |
| 476 | * and just continue. */ |
| 477 | (void)ret; |
| 478 | prefaulted = 1; |
| 479 | } |
| 480 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 481 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 482 | user_data, page_do_bit17_swizzling, |
| 483 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 484 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 485 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 486 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 487 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 488 | mark_page_accessed(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 489 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 490 | if (ret) |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 491 | goto out; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 492 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 493 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 494 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 495 | offset += page_length; |
| 496 | } |
| 497 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 498 | out: |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 499 | i915_gem_object_unpin_pages(obj); |
| 500 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 501 | return ret; |
| 502 | } |
| 503 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 504 | /** |
| 505 | * Reads data from the object referenced by handle. |
| 506 | * |
| 507 | * On error, the contents of *data are undefined. |
| 508 | */ |
| 509 | int |
| 510 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 511 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 512 | { |
| 513 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 514 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 515 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 516 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 517 | if (args->size == 0) |
| 518 | return 0; |
| 519 | |
| 520 | if (!access_ok(VERIFY_WRITE, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 521 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 522 | args->size)) |
| 523 | return -EFAULT; |
| 524 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 525 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 526 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 527 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 528 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 529 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 530 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 531 | ret = -ENOENT; |
| 532 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 533 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 534 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 535 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 536 | if (args->offset > obj->base.size || |
| 537 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 538 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 539 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 540 | } |
| 541 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 542 | /* prime objects have no backing filp to GEM pread/pwrite |
| 543 | * pages from. |
| 544 | */ |
| 545 | if (!obj->base.filp) { |
| 546 | ret = -EINVAL; |
| 547 | goto out; |
| 548 | } |
| 549 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 550 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 551 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 552 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 553 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 554 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 555 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 556 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 557 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 558 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 559 | } |
| 560 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 561 | /* This is the fast write path which cannot handle |
| 562 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 563 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 564 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 565 | static inline int |
| 566 | fast_user_write(struct io_mapping *mapping, |
| 567 | loff_t page_base, int page_offset, |
| 568 | char __user *user_data, |
| 569 | int length) |
| 570 | { |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 571 | void __iomem *vaddr_atomic; |
| 572 | void *vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 573 | unsigned long unwritten; |
| 574 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 575 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 576 | /* We can use the cpu mem copy function because this is X86. */ |
| 577 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 578 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 579 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 580 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 581 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 582 | } |
| 583 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 584 | /** |
| 585 | * This is the fast pwrite path, where we copy the data directly from the |
| 586 | * user into the GTT, uncached. |
| 587 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 588 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 589 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 590 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 591 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 592 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 593 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 594 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 595 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 596 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 597 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 598 | int page_offset, page_length, ret; |
| 599 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 600 | ret = i915_gem_object_pin(obj, 0, true, true); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 601 | if (ret) |
| 602 | goto out; |
| 603 | |
| 604 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 605 | if (ret) |
| 606 | goto out_unpin; |
| 607 | |
| 608 | ret = i915_gem_object_put_fence(obj); |
| 609 | if (ret) |
| 610 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 611 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 612 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 613 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 614 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 615 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 616 | |
| 617 | while (remain > 0) { |
| 618 | /* Operation in this page |
| 619 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 620 | * page_base = page offset within aperture |
| 621 | * page_offset = offset within page |
| 622 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 623 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 624 | page_base = offset & PAGE_MASK; |
| 625 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 626 | page_length = remain; |
| 627 | if ((page_offset + remain) > PAGE_SIZE) |
| 628 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 629 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 630 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 631 | * source page isn't available. Return the error and we'll |
| 632 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 633 | */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 634 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 635 | page_offset, user_data, page_length)) { |
| 636 | ret = -EFAULT; |
| 637 | goto out_unpin; |
| 638 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 639 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 640 | remain -= page_length; |
| 641 | user_data += page_length; |
| 642 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 643 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 644 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 645 | out_unpin: |
| 646 | i915_gem_object_unpin(obj); |
| 647 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 648 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 649 | } |
| 650 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 651 | /* Per-page copy function for the shmem pwrite fastpath. |
| 652 | * Flushes invalid cachelines before writing to the target if |
| 653 | * needs_clflush_before is set and flushes out any written cachelines after |
| 654 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 655 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 656 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 657 | char __user *user_data, |
| 658 | bool page_do_bit17_swizzling, |
| 659 | bool needs_clflush_before, |
| 660 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 661 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 662 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 663 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 664 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 665 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 666 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 667 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 668 | vaddr = kmap_atomic(page); |
| 669 | if (needs_clflush_before) |
| 670 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 671 | page_length); |
| 672 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, |
| 673 | user_data, |
| 674 | page_length); |
| 675 | if (needs_clflush_after) |
| 676 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 677 | page_length); |
| 678 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 679 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 680 | return ret ? -EFAULT : 0; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 681 | } |
| 682 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 683 | /* Only difference to the fast-path function is that this can handle bit17 |
| 684 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 685 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 686 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 687 | char __user *user_data, |
| 688 | bool page_do_bit17_swizzling, |
| 689 | bool needs_clflush_before, |
| 690 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 691 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 692 | char *vaddr; |
| 693 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 694 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 695 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 696 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 697 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 698 | page_length, |
| 699 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 700 | if (page_do_bit17_swizzling) |
| 701 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 702 | user_data, |
| 703 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 704 | else |
| 705 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 706 | user_data, |
| 707 | page_length); |
| 708 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 709 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 710 | page_length, |
| 711 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 712 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 713 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 714 | return ret ? -EFAULT : 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 715 | } |
| 716 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 717 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 718 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 719 | struct drm_i915_gem_object *obj, |
| 720 | struct drm_i915_gem_pwrite *args, |
| 721 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 722 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 723 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 724 | loff_t offset; |
| 725 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 726 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 727 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 728 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 729 | int needs_clflush_after = 0; |
| 730 | int needs_clflush_before = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 731 | struct sg_page_iter sg_iter; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 732 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 733 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 734 | remain = args->size; |
| 735 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 736 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 737 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 738 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 739 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 740 | * write domain and manually flush cachelines (if required). This |
| 741 | * optimizes for the case when the gpu will use the data |
| 742 | * right away and we therefore have to clflush anyway. */ |
| 743 | if (obj->cache_level == I915_CACHE_NONE) |
| 744 | needs_clflush_after = 1; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 745 | if (obj->gtt_space) { |
| 746 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 747 | if (ret) |
| 748 | return ret; |
| 749 | } |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 750 | } |
| 751 | /* Same trick applies for invalidate partially written cachelines before |
| 752 | * writing. */ |
| 753 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) |
| 754 | && obj->cache_level == I915_CACHE_NONE) |
| 755 | needs_clflush_before = 1; |
| 756 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 757 | ret = i915_gem_object_get_pages(obj); |
| 758 | if (ret) |
| 759 | return ret; |
| 760 | |
| 761 | i915_gem_object_pin_pages(obj); |
| 762 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 763 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 764 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 765 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 766 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 767 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 768 | struct page *page = sg_page_iter_page(&sg_iter); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 769 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 770 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 771 | if (remain <= 0) |
| 772 | break; |
| 773 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 774 | /* Operation in this page |
| 775 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 776 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 777 | * page_length = bytes to copy for this page |
| 778 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 779 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 780 | |
| 781 | page_length = remain; |
| 782 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 783 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 784 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 785 | /* If we don't overwrite a cacheline completely we need to be |
| 786 | * careful to have up-to-date data by first clflushing. Don't |
| 787 | * overcomplicate things and flush the entire patch. */ |
| 788 | partial_cacheline_write = needs_clflush_before && |
| 789 | ((shmem_page_offset | page_length) |
| 790 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 791 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 792 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 793 | (page_to_phys(page) & (1 << 17)) != 0; |
| 794 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 795 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 796 | user_data, page_do_bit17_swizzling, |
| 797 | partial_cacheline_write, |
| 798 | needs_clflush_after); |
| 799 | if (ret == 0) |
| 800 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 801 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 802 | hit_slowpath = 1; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 803 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 804 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 805 | user_data, page_do_bit17_swizzling, |
| 806 | partial_cacheline_write, |
| 807 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 808 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 809 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 810 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 811 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 812 | set_page_dirty(page); |
| 813 | mark_page_accessed(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 814 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 815 | if (ret) |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 816 | goto out; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 817 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 818 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 819 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 820 | offset += page_length; |
| 821 | } |
| 822 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 823 | out: |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 824 | i915_gem_object_unpin_pages(obj); |
| 825 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 826 | if (hit_slowpath) { |
Daniel Vetter | 8dcf015 | 2012-11-15 16:53:58 +0100 | [diff] [blame] | 827 | /* |
| 828 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
| 829 | * cachelines in-line while writing and the object moved |
| 830 | * out of the cpu write domain while we've dropped the lock. |
| 831 | */ |
| 832 | if (!needs_clflush_after && |
| 833 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 834 | i915_gem_clflush_object(obj); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 835 | i915_gem_chipset_flush(dev); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 836 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 837 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 838 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 839 | if (needs_clflush_after) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 840 | i915_gem_chipset_flush(dev); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 841 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 842 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 843 | } |
| 844 | |
| 845 | /** |
| 846 | * Writes data to the object referenced by handle. |
| 847 | * |
| 848 | * On error, the contents of the buffer that were to be modified are undefined. |
| 849 | */ |
| 850 | int |
| 851 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 852 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 853 | { |
| 854 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 855 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 856 | int ret; |
| 857 | |
| 858 | if (args->size == 0) |
| 859 | return 0; |
| 860 | |
| 861 | if (!access_ok(VERIFY_READ, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 862 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 863 | args->size)) |
| 864 | return -EFAULT; |
| 865 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 866 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 867 | args->size); |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 868 | if (ret) |
| 869 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 870 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 871 | ret = i915_mutex_lock_interruptible(dev); |
| 872 | if (ret) |
| 873 | return ret; |
| 874 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 875 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 876 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 877 | ret = -ENOENT; |
| 878 | goto unlock; |
| 879 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 880 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 881 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 882 | if (args->offset > obj->base.size || |
| 883 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 884 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 885 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 886 | } |
| 887 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 888 | /* prime objects have no backing filp to GEM pread/pwrite |
| 889 | * pages from. |
| 890 | */ |
| 891 | if (!obj->base.filp) { |
| 892 | ret = -EINVAL; |
| 893 | goto out; |
| 894 | } |
| 895 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 896 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 897 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 898 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 899 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 900 | * it would end up going through the fenced access, and we'll get |
| 901 | * different detiling behavior between reading and writing. |
| 902 | * pread/pwrite currently are reading and writing from the CPU |
| 903 | * perspective, requiring manual detiling by the client. |
| 904 | */ |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 905 | if (obj->phys_obj) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 906 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 907 | goto out; |
| 908 | } |
| 909 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 910 | if (obj->cache_level == I915_CACHE_NONE && |
Daniel Vetter | c07496f | 2012-04-13 15:51:51 +0200 | [diff] [blame] | 911 | obj->tiling_mode == I915_TILING_NONE && |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 912 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 913 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 914 | /* Note that the gtt paths might fail with non-page-backed user |
| 915 | * pointers (e.g. gtt mappings when moving data between |
| 916 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 917 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 918 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 919 | if (ret == -EFAULT || ret == -ENOSPC) |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 920 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 921 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 922 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 923 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 924 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 925 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 926 | return ret; |
| 927 | } |
| 928 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 929 | int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 930 | i915_gem_check_wedge(struct i915_gpu_error *error, |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 931 | bool interruptible) |
| 932 | { |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 933 | if (i915_reset_in_progress(error)) { |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 934 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 935 | * -EIO unconditionally for these. */ |
| 936 | if (!interruptible) |
| 937 | return -EIO; |
| 938 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 939 | /* Recovery complete, but the reset failed ... */ |
| 940 | if (i915_terminally_wedged(error)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 941 | return -EIO; |
| 942 | |
| 943 | return -EAGAIN; |
| 944 | } |
| 945 | |
| 946 | return 0; |
| 947 | } |
| 948 | |
| 949 | /* |
| 950 | * Compare seqno against outstanding lazy request. Emit a request if they are |
| 951 | * equal. |
| 952 | */ |
| 953 | static int |
| 954 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) |
| 955 | { |
| 956 | int ret; |
| 957 | |
| 958 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
| 959 | |
| 960 | ret = 0; |
| 961 | if (seqno == ring->outstanding_lazy_request) |
| 962 | ret = i915_add_request(ring, NULL, NULL); |
| 963 | |
| 964 | return ret; |
| 965 | } |
| 966 | |
| 967 | /** |
| 968 | * __wait_seqno - wait until execution of seqno has finished |
| 969 | * @ring: the ring expected to report seqno |
| 970 | * @seqno: duh! |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 971 | * @reset_counter: reset sequence associated with the given seqno |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 972 | * @interruptible: do an interruptible wait (normally yes) |
| 973 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 974 | * |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 975 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
| 976 | * values have been read by the caller in an smp safe manner. Where read-side |
| 977 | * locks are involved, it is sufficient to read the reset_counter before |
| 978 | * unlocking the lock that protects the seqno. For lockless tricks, the |
| 979 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
| 980 | * inserted. |
| 981 | * |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 982 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
| 983 | * errno with remaining time filled in timeout argument. |
| 984 | */ |
| 985 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 986 | unsigned reset_counter, |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 987 | bool interruptible, struct timespec *timeout) |
| 988 | { |
| 989 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 990 | struct timespec before, now, wait_time={1,0}; |
| 991 | unsigned long timeout_jiffies; |
| 992 | long end; |
| 993 | bool wait_forever = true; |
| 994 | int ret; |
| 995 | |
| 996 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
| 997 | return 0; |
| 998 | |
| 999 | trace_i915_gem_request_wait_begin(ring, seqno); |
| 1000 | |
| 1001 | if (timeout != NULL) { |
| 1002 | wait_time = *timeout; |
| 1003 | wait_forever = false; |
| 1004 | } |
| 1005 | |
| 1006 | timeout_jiffies = timespec_to_jiffies(&wait_time); |
| 1007 | |
| 1008 | if (WARN_ON(!ring->irq_get(ring))) |
| 1009 | return -ENODEV; |
| 1010 | |
| 1011 | /* Record current time in case interrupted by signal, or wedged * */ |
| 1012 | getrawmonotonic(&before); |
| 1013 | |
| 1014 | #define EXIT_COND \ |
| 1015 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1016 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
| 1017 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1018 | do { |
| 1019 | if (interruptible) |
| 1020 | end = wait_event_interruptible_timeout(ring->irq_queue, |
| 1021 | EXIT_COND, |
| 1022 | timeout_jiffies); |
| 1023 | else |
| 1024 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, |
| 1025 | timeout_jiffies); |
| 1026 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1027 | /* We need to check whether any gpu reset happened in between |
| 1028 | * the caller grabbing the seqno and now ... */ |
| 1029 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
| 1030 | end = -EAGAIN; |
| 1031 | |
| 1032 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely |
| 1033 | * gone. */ |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1034 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1035 | if (ret) |
| 1036 | end = ret; |
| 1037 | } while (end == 0 && wait_forever); |
| 1038 | |
| 1039 | getrawmonotonic(&now); |
| 1040 | |
| 1041 | ring->irq_put(ring); |
| 1042 | trace_i915_gem_request_wait_end(ring, seqno); |
| 1043 | #undef EXIT_COND |
| 1044 | |
| 1045 | if (timeout) { |
| 1046 | struct timespec sleep_time = timespec_sub(now, before); |
| 1047 | *timeout = timespec_sub(*timeout, sleep_time); |
| 1048 | } |
| 1049 | |
| 1050 | switch (end) { |
| 1051 | case -EIO: |
| 1052 | case -EAGAIN: /* Wedged */ |
| 1053 | case -ERESTARTSYS: /* Signal */ |
| 1054 | return (int)end; |
| 1055 | case 0: /* Timeout */ |
| 1056 | if (timeout) |
| 1057 | set_normalized_timespec(timeout, 0, 0); |
| 1058 | return -ETIME; |
| 1059 | default: /* Completed */ |
| 1060 | WARN_ON(end < 0); /* We're not aware of other errors */ |
| 1061 | return 0; |
| 1062 | } |
| 1063 | } |
| 1064 | |
| 1065 | /** |
| 1066 | * Waits for a sequence number to be signaled, and cleans up the |
| 1067 | * request and object lists appropriately for that event. |
| 1068 | */ |
| 1069 | int |
| 1070 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
| 1071 | { |
| 1072 | struct drm_device *dev = ring->dev; |
| 1073 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1074 | bool interruptible = dev_priv->mm.interruptible; |
| 1075 | int ret; |
| 1076 | |
| 1077 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1078 | BUG_ON(seqno == 0); |
| 1079 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1080 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1081 | if (ret) |
| 1082 | return ret; |
| 1083 | |
| 1084 | ret = i915_gem_check_olr(ring, seqno); |
| 1085 | if (ret) |
| 1086 | return ret; |
| 1087 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1088 | return __wait_seqno(ring, seqno, |
| 1089 | atomic_read(&dev_priv->gpu_error.reset_counter), |
| 1090 | interruptible, NULL); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1091 | } |
| 1092 | |
| 1093 | /** |
| 1094 | * Ensures that all rendering to the object has completed and the object is |
| 1095 | * safe to unbind from the GTT or access from the CPU. |
| 1096 | */ |
| 1097 | static __must_check int |
| 1098 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1099 | bool readonly) |
| 1100 | { |
| 1101 | struct intel_ring_buffer *ring = obj->ring; |
| 1102 | u32 seqno; |
| 1103 | int ret; |
| 1104 | |
| 1105 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1106 | if (seqno == 0) |
| 1107 | return 0; |
| 1108 | |
| 1109 | ret = i915_wait_seqno(ring, seqno); |
| 1110 | if (ret) |
| 1111 | return ret; |
| 1112 | |
| 1113 | i915_gem_retire_requests_ring(ring); |
| 1114 | |
| 1115 | /* Manually manage the write flush as we may have not yet |
| 1116 | * retired the buffer. |
| 1117 | */ |
| 1118 | if (obj->last_write_seqno && |
| 1119 | i915_seqno_passed(seqno, obj->last_write_seqno)) { |
| 1120 | obj->last_write_seqno = 0; |
| 1121 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 1122 | } |
| 1123 | |
| 1124 | return 0; |
| 1125 | } |
| 1126 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1127 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1128 | * as the object state may change during this call. |
| 1129 | */ |
| 1130 | static __must_check int |
| 1131 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
| 1132 | bool readonly) |
| 1133 | { |
| 1134 | struct drm_device *dev = obj->base.dev; |
| 1135 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1136 | struct intel_ring_buffer *ring = obj->ring; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1137 | unsigned reset_counter; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1138 | u32 seqno; |
| 1139 | int ret; |
| 1140 | |
| 1141 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1142 | BUG_ON(!dev_priv->mm.interruptible); |
| 1143 | |
| 1144 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1145 | if (seqno == 0) |
| 1146 | return 0; |
| 1147 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1148 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1149 | if (ret) |
| 1150 | return ret; |
| 1151 | |
| 1152 | ret = i915_gem_check_olr(ring, seqno); |
| 1153 | if (ret) |
| 1154 | return ret; |
| 1155 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1156 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1157 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1158 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1159 | mutex_lock(&dev->struct_mutex); |
| 1160 | |
| 1161 | i915_gem_retire_requests_ring(ring); |
| 1162 | |
| 1163 | /* Manually manage the write flush as we may have not yet |
| 1164 | * retired the buffer. |
| 1165 | */ |
| 1166 | if (obj->last_write_seqno && |
| 1167 | i915_seqno_passed(seqno, obj->last_write_seqno)) { |
| 1168 | obj->last_write_seqno = 0; |
| 1169 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 1170 | } |
| 1171 | |
| 1172 | return ret; |
| 1173 | } |
| 1174 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1175 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1176 | * Called when user space prepares to use an object with the CPU, either |
| 1177 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1178 | */ |
| 1179 | int |
| 1180 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1181 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1182 | { |
| 1183 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1184 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1185 | uint32_t read_domains = args->read_domains; |
| 1186 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1187 | int ret; |
| 1188 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1189 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1190 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1191 | return -EINVAL; |
| 1192 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1193 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1194 | return -EINVAL; |
| 1195 | |
| 1196 | /* Having something in the write domain implies it's in the read |
| 1197 | * domain, and only that read domain. Enforce that in the request. |
| 1198 | */ |
| 1199 | if (write_domain != 0 && read_domains != write_domain) |
| 1200 | return -EINVAL; |
| 1201 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1202 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1203 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1204 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1205 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1206 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1207 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1208 | ret = -ENOENT; |
| 1209 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1210 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1211 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1212 | /* Try to flush the object off the GPU without holding the lock. |
| 1213 | * We will repeat the flush holding the lock in the normal manner |
| 1214 | * to catch cases where we are gazumped. |
| 1215 | */ |
| 1216 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); |
| 1217 | if (ret) |
| 1218 | goto unref; |
| 1219 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1220 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1221 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1222 | |
| 1223 | /* Silently promote "you're not bound, there was nothing to do" |
| 1224 | * to success, since the client was just asking us to |
| 1225 | * make sure everything was done. |
| 1226 | */ |
| 1227 | if (ret == -EINVAL) |
| 1228 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1229 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1230 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1231 | } |
| 1232 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1233 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1234 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1235 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1236 | mutex_unlock(&dev->struct_mutex); |
| 1237 | return ret; |
| 1238 | } |
| 1239 | |
| 1240 | /** |
| 1241 | * Called when user space has done writes to this buffer |
| 1242 | */ |
| 1243 | int |
| 1244 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1245 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1246 | { |
| 1247 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1248 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1249 | int ret = 0; |
| 1250 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1251 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1252 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1253 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1254 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1255 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1256 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1257 | ret = -ENOENT; |
| 1258 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1259 | } |
| 1260 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1261 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1262 | if (obj->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1263 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1264 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1265 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1266 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1267 | mutex_unlock(&dev->struct_mutex); |
| 1268 | return ret; |
| 1269 | } |
| 1270 | |
| 1271 | /** |
| 1272 | * Maps the contents of an object, returning the address it is mapped |
| 1273 | * into. |
| 1274 | * |
| 1275 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1276 | * imply a ref on the object itself. |
| 1277 | */ |
| 1278 | int |
| 1279 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1280 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1281 | { |
| 1282 | struct drm_i915_gem_mmap *args = data; |
| 1283 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1284 | unsigned long addr; |
| 1285 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1286 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1287 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1288 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1289 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1290 | /* prime objects have no backing filp to GEM mmap |
| 1291 | * pages from. |
| 1292 | */ |
| 1293 | if (!obj->filp) { |
| 1294 | drm_gem_object_unreference_unlocked(obj); |
| 1295 | return -EINVAL; |
| 1296 | } |
| 1297 | |
Linus Torvalds | 6be5ceb | 2012-04-20 17:13:58 -0700 | [diff] [blame] | 1298 | addr = vm_mmap(obj->filp, 0, args->size, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1299 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1300 | args->offset); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1301 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1302 | if (IS_ERR((void *)addr)) |
| 1303 | return addr; |
| 1304 | |
| 1305 | args->addr_ptr = (uint64_t) addr; |
| 1306 | |
| 1307 | return 0; |
| 1308 | } |
| 1309 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1310 | /** |
| 1311 | * i915_gem_fault - fault a page into the GTT |
| 1312 | * vma: VMA in question |
| 1313 | * vmf: fault info |
| 1314 | * |
| 1315 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1316 | * from userspace. The fault handler takes care of binding the object to |
| 1317 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1318 | * only if needed based on whether the old reg is still valid or the object |
| 1319 | * is tiled) and inserting a new PTE into the faulting process. |
| 1320 | * |
| 1321 | * Note that the faulting process may involve evicting existing objects |
| 1322 | * from the GTT and/or fence registers to make room. So performance may |
| 1323 | * suffer if the GTT working set is large or there are few fence registers |
| 1324 | * left. |
| 1325 | */ |
| 1326 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1327 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1328 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1329 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1330 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1331 | pgoff_t page_offset; |
| 1332 | unsigned long pfn; |
| 1333 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1334 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1335 | |
| 1336 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1337 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1338 | PAGE_SHIFT; |
| 1339 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1340 | ret = i915_mutex_lock_interruptible(dev); |
| 1341 | if (ret) |
| 1342 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1343 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1344 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1345 | |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1346 | /* Access to snoopable pages through the GTT is incoherent. */ |
| 1347 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { |
| 1348 | ret = -EINVAL; |
| 1349 | goto unlock; |
| 1350 | } |
| 1351 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1352 | /* Now bind it into the GTT if needed */ |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1353 | ret = i915_gem_object_pin(obj, 0, true, false); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1354 | if (ret) |
| 1355 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1356 | |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1357 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1358 | if (ret) |
| 1359 | goto unpin; |
| 1360 | |
| 1361 | ret = i915_gem_object_get_fence(obj); |
| 1362 | if (ret) |
| 1363 | goto unpin; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1364 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1365 | obj->fault_mappable = true; |
| 1366 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1367 | pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) + |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1368 | page_offset; |
| 1369 | |
| 1370 | /* Finally, remap it using the new GTT offset */ |
| 1371 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1372 | unpin: |
| 1373 | i915_gem_object_unpin(obj); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1374 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1375 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1376 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1377 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1378 | case -EIO: |
Daniel Vetter | a9340cc | 2012-07-04 22:18:42 +0200 | [diff] [blame] | 1379 | /* If this -EIO is due to a gpu hang, give the reset code a |
| 1380 | * chance to clean up the mess. Otherwise return the proper |
| 1381 | * SIGBUS. */ |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1382 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
Daniel Vetter | a9340cc | 2012-07-04 22:18:42 +0200 | [diff] [blame] | 1383 | return VM_FAULT_SIGBUS; |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1384 | case -EAGAIN: |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1385 | /* Give the error handler a chance to run and move the |
| 1386 | * objects off the GPU active list. Next time we service the |
| 1387 | * fault, we should be able to transition the page into the |
| 1388 | * GTT without touching the GPU (and so avoid further |
| 1389 | * EIO/EGAIN). If the GPU is wedged, then there is no issue |
| 1390 | * with coherency, just lost writes. |
| 1391 | */ |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1392 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1393 | case 0: |
| 1394 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1395 | case -EINTR: |
Dmitry Rogozhkin | e79e0fe | 2012-10-03 17:15:26 +0300 | [diff] [blame] | 1396 | case -EBUSY: |
| 1397 | /* |
| 1398 | * EBUSY is ok: this just means that another thread |
| 1399 | * already did the job. |
| 1400 | */ |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1401 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1402 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1403 | return VM_FAULT_OOM; |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1404 | case -ENOSPC: |
| 1405 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1406 | default: |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1407 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1408 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1409 | } |
| 1410 | } |
| 1411 | |
| 1412 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1413 | * i915_gem_release_mmap - remove physical page mappings |
| 1414 | * @obj: obj in question |
| 1415 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1416 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1417 | * relinquish ownership of the pages back to the system. |
| 1418 | * |
| 1419 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1420 | * object through the GTT and then lose the fence register due to |
| 1421 | * resource pressure. Similarly if the object has been moved out of the |
| 1422 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1423 | * mapping will then trigger a page fault on the next user access, allowing |
| 1424 | * fixup by i915_gem_fault(). |
| 1425 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1426 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1427 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1428 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1429 | if (!obj->fault_mappable) |
| 1430 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1431 | |
Chris Wilson | f6e4788 | 2011-03-20 21:09:12 +0000 | [diff] [blame] | 1432 | if (obj->base.dev->dev_mapping) |
| 1433 | unmap_mapping_range(obj->base.dev->dev_mapping, |
| 1434 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
| 1435 | obj->base.size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1436 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1437 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1438 | } |
| 1439 | |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 1440 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1441 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1442 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1443 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1444 | |
| 1445 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1446 | tiling_mode == I915_TILING_NONE) |
| 1447 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1448 | |
| 1449 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1450 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1451 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1452 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1453 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1454 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1455 | while (gtt_size < size) |
| 1456 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1457 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1458 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1459 | } |
| 1460 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1461 | /** |
| 1462 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1463 | * @obj: object to check |
| 1464 | * |
| 1465 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1466 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1467 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1468 | uint32_t |
| 1469 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 1470 | int tiling_mode, bool fenced) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1471 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1472 | /* |
| 1473 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1474 | * if a fence register is needed for the object. |
| 1475 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1476 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1477 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1478 | return 4096; |
| 1479 | |
| 1480 | /* |
| 1481 | * Previous chips need to be aligned to the size of the smallest |
| 1482 | * fence register that can contain the object. |
| 1483 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1484 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1485 | } |
| 1486 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1487 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 1488 | { |
| 1489 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1490 | int ret; |
| 1491 | |
| 1492 | if (obj->base.map_list.map) |
| 1493 | return 0; |
| 1494 | |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1495 | dev_priv->mm.shrinker_no_lock_stealing = true; |
| 1496 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1497 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1498 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1499 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1500 | |
| 1501 | /* Badly fragmented mmap space? The only way we can recover |
| 1502 | * space is by destroying unwanted objects. We can't randomly release |
| 1503 | * mmap_offsets as userspace expects them to be persistent for the |
| 1504 | * lifetime of the objects. The closest we can is to release the |
| 1505 | * offsets on purgeable objects by truncating it and marking it purged, |
| 1506 | * which prevents userspace from ever using that object again. |
| 1507 | */ |
| 1508 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); |
| 1509 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1510 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1511 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1512 | |
| 1513 | i915_gem_shrink_all(dev_priv); |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1514 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1515 | out: |
| 1516 | dev_priv->mm.shrinker_no_lock_stealing = false; |
| 1517 | |
| 1518 | return ret; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1519 | } |
| 1520 | |
| 1521 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 1522 | { |
| 1523 | if (!obj->base.map_list.map) |
| 1524 | return; |
| 1525 | |
| 1526 | drm_gem_free_mmap_offset(&obj->base); |
| 1527 | } |
| 1528 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1529 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1530 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1531 | struct drm_device *dev, |
| 1532 | uint32_t handle, |
| 1533 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1534 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1535 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1536 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1537 | int ret; |
| 1538 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1539 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1540 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1541 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1542 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1543 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1544 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1545 | ret = -ENOENT; |
| 1546 | goto unlock; |
| 1547 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1548 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1549 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1550 | ret = -E2BIG; |
Eric Anholt | ff56b0b | 2011-10-31 23:16:21 -0700 | [diff] [blame] | 1551 | goto out; |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1552 | } |
| 1553 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1554 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1555 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1556 | ret = -EINVAL; |
| 1557 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1558 | } |
| 1559 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1560 | ret = i915_gem_object_create_mmap_offset(obj); |
| 1561 | if (ret) |
| 1562 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1563 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1564 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1565 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1566 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1567 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1568 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1569 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1570 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1571 | } |
| 1572 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1573 | /** |
| 1574 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1575 | * @dev: DRM device |
| 1576 | * @data: GTT mapping ioctl data |
| 1577 | * @file: GEM object info |
| 1578 | * |
| 1579 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1580 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1581 | * up so we can get faults in the handler above. |
| 1582 | * |
| 1583 | * The fault handler will take care of binding the object into the GTT |
| 1584 | * (since it may have been evicted to make room for something), allocating |
| 1585 | * a fence register, and mapping the appropriate aperture address into |
| 1586 | * userspace. |
| 1587 | */ |
| 1588 | int |
| 1589 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1590 | struct drm_file *file) |
| 1591 | { |
| 1592 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1593 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1594 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1595 | } |
| 1596 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1597 | /* Immediately discard the backing storage */ |
| 1598 | static void |
| 1599 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1600 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1601 | struct inode *inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1602 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1603 | i915_gem_object_free_mmap_offset(obj); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1604 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1605 | if (obj->base.filp == NULL) |
| 1606 | return; |
| 1607 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1608 | /* Our goal here is to return as much of the memory as |
| 1609 | * is possible back to the system as we are called from OOM. |
| 1610 | * To do this we must instruct the shmfs to drop all of its |
| 1611 | * backing pages, *now*. |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1612 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 1613 | inode = file_inode(obj->base.filp); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1614 | shmem_truncate_range(inode, 0, (loff_t)-1); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1615 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1616 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1617 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1618 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1619 | static inline int |
| 1620 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
| 1621 | { |
| 1622 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1623 | } |
| 1624 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1625 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1626 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1627 | { |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1628 | struct sg_page_iter sg_iter; |
| 1629 | int ret; |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1630 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1631 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1632 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1633 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 1634 | if (ret) { |
| 1635 | /* In the event of a disaster, abandon all caches and |
| 1636 | * hope for the best. |
| 1637 | */ |
| 1638 | WARN_ON(ret != -EIO); |
| 1639 | i915_gem_clflush_object(obj); |
| 1640 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 1641 | } |
| 1642 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1643 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1644 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1645 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1646 | if (obj->madv == I915_MADV_DONTNEED) |
| 1647 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1648 | |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1649 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1650 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1651 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1652 | if (obj->dirty) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1653 | set_page_dirty(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1654 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1655 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1656 | mark_page_accessed(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1657 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1658 | page_cache_release(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1659 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1660 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1661 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1662 | sg_free_table(obj->pages); |
| 1663 | kfree(obj->pages); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1664 | } |
| 1665 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1666 | int |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1667 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 1668 | { |
| 1669 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1670 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 1671 | if (obj->pages == NULL) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1672 | return 0; |
| 1673 | |
| 1674 | BUG_ON(obj->gtt_space); |
| 1675 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1676 | if (obj->pages_pin_count) |
| 1677 | return -EBUSY; |
| 1678 | |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 1679 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
| 1680 | * array, hence protect them from being reaped by removing them from gtt |
| 1681 | * lists early. */ |
| 1682 | list_del(&obj->gtt_list); |
| 1683 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1684 | ops->put_pages(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1685 | obj->pages = NULL; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1686 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1687 | if (i915_gem_object_is_purgeable(obj)) |
| 1688 | i915_gem_object_truncate(obj); |
| 1689 | |
| 1690 | return 0; |
| 1691 | } |
| 1692 | |
| 1693 | static long |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1694 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
| 1695 | bool purgeable_only) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1696 | { |
| 1697 | struct drm_i915_gem_object *obj, *next; |
| 1698 | long count = 0; |
| 1699 | |
| 1700 | list_for_each_entry_safe(obj, next, |
| 1701 | &dev_priv->mm.unbound_list, |
| 1702 | gtt_list) { |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1703 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1704 | i915_gem_object_put_pages(obj) == 0) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1705 | count += obj->base.size >> PAGE_SHIFT; |
| 1706 | if (count >= target) |
| 1707 | return count; |
| 1708 | } |
| 1709 | } |
| 1710 | |
| 1711 | list_for_each_entry_safe(obj, next, |
| 1712 | &dev_priv->mm.inactive_list, |
| 1713 | mm_list) { |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1714 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1715 | i915_gem_object_unbind(obj) == 0 && |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1716 | i915_gem_object_put_pages(obj) == 0) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1717 | count += obj->base.size >> PAGE_SHIFT; |
| 1718 | if (count >= target) |
| 1719 | return count; |
| 1720 | } |
| 1721 | } |
| 1722 | |
| 1723 | return count; |
| 1724 | } |
| 1725 | |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1726 | static long |
| 1727 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
| 1728 | { |
| 1729 | return __i915_gem_shrink(dev_priv, target, true); |
| 1730 | } |
| 1731 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1732 | static void |
| 1733 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
| 1734 | { |
| 1735 | struct drm_i915_gem_object *obj, *next; |
| 1736 | |
| 1737 | i915_gem_evict_everything(dev_priv->dev); |
| 1738 | |
| 1739 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1740 | i915_gem_object_put_pages(obj); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1741 | } |
| 1742 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1743 | static int |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1744 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1745 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1746 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1747 | int page_count, i; |
| 1748 | struct address_space *mapping; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1749 | struct sg_table *st; |
| 1750 | struct scatterlist *sg; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1751 | struct sg_page_iter sg_iter; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1752 | struct page *page; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1753 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1754 | gfp_t gfp; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1755 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1756 | /* Assert that the object is not currently in any GPU domain. As it |
| 1757 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 1758 | * a GPU cache |
| 1759 | */ |
| 1760 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 1761 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 1762 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1763 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 1764 | if (st == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1765 | return -ENOMEM; |
| 1766 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1767 | page_count = obj->base.size / PAGE_SIZE; |
| 1768 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
| 1769 | sg_free_table(st); |
| 1770 | kfree(st); |
| 1771 | return -ENOMEM; |
| 1772 | } |
| 1773 | |
| 1774 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1775 | * at this point until we release them. |
| 1776 | * |
| 1777 | * Fail silently without starting the shrinker |
| 1778 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 1779 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1780 | gfp = mapping_gfp_mask(mapping); |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 1781 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1782 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1783 | sg = st->sgl; |
| 1784 | st->nents = 0; |
| 1785 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1786 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1787 | if (IS_ERR(page)) { |
| 1788 | i915_gem_purge(dev_priv, page_count); |
| 1789 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1790 | } |
| 1791 | if (IS_ERR(page)) { |
| 1792 | /* We've tried hard to allocate the memory by reaping |
| 1793 | * our own buffer, now let the real VM do its job and |
| 1794 | * go down in flames if truly OOM. |
| 1795 | */ |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 1796 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1797 | gfp |= __GFP_IO | __GFP_WAIT; |
| 1798 | |
| 1799 | i915_gem_shrink_all(dev_priv); |
| 1800 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1801 | if (IS_ERR(page)) |
| 1802 | goto err_pages; |
| 1803 | |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 1804 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1805 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
| 1806 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1807 | |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1808 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
| 1809 | if (i) |
| 1810 | sg = sg_next(sg); |
| 1811 | st->nents++; |
| 1812 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 1813 | } else { |
| 1814 | sg->length += PAGE_SIZE; |
| 1815 | } |
| 1816 | last_pfn = page_to_pfn(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1817 | } |
| 1818 | |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1819 | sg_mark_end(sg); |
Chris Wilson | 74ce6b6 | 2012-10-19 15:51:06 +0100 | [diff] [blame] | 1820 | obj->pages = st; |
| 1821 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1822 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 1823 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1824 | |
| 1825 | return 0; |
| 1826 | |
| 1827 | err_pages: |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1828 | sg_mark_end(sg); |
| 1829 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1830 | page_cache_release(sg_page_iter_page(&sg_iter)); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1831 | sg_free_table(st); |
| 1832 | kfree(st); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1833 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1834 | } |
| 1835 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1836 | /* Ensure that the associated pages are gathered from the backing storage |
| 1837 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 1838 | * multiple times before they are released by a single call to |
| 1839 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 1840 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 1841 | * or as the object is itself released. |
| 1842 | */ |
| 1843 | int |
| 1844 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 1845 | { |
| 1846 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1847 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1848 | int ret; |
| 1849 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 1850 | if (obj->pages) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1851 | return 0; |
| 1852 | |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 1853 | if (obj->madv != I915_MADV_WILLNEED) { |
| 1854 | DRM_ERROR("Attempting to obtain a purgeable object\n"); |
| 1855 | return -EINVAL; |
| 1856 | } |
| 1857 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1858 | BUG_ON(obj->pages_pin_count); |
| 1859 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1860 | ret = ops->get_pages(obj); |
| 1861 | if (ret) |
| 1862 | return ret; |
| 1863 | |
| 1864 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); |
| 1865 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1866 | } |
| 1867 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1868 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1869 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1870 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1871 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1872 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1873 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1874 | u32 seqno = intel_ring_get_seqno(ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1875 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1876 | BUG_ON(ring == NULL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1877 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1878 | |
| 1879 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1880 | if (!obj->active) { |
| 1881 | drm_gem_object_reference(&obj->base); |
| 1882 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1883 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1884 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1885 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1886 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
| 1887 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1888 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 1889 | obj->last_read_seqno = seqno; |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1890 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1891 | if (obj->fenced_gpu_access) { |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1892 | obj->last_fenced_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1893 | |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1894 | /* Bump MRU to take account of the delayed flush */ |
| 1895 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 1896 | struct drm_i915_fence_reg *reg; |
| 1897 | |
| 1898 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1899 | list_move_tail(®->lru_list, |
| 1900 | &dev_priv->mm.fence_list); |
| 1901 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1902 | } |
| 1903 | } |
| 1904 | |
| 1905 | static void |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1906 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1907 | { |
| 1908 | struct drm_device *dev = obj->base.dev; |
| 1909 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1910 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1911 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1912 | BUG_ON(!obj->active); |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1913 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1914 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 1915 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1916 | list_del_init(&obj->ring_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1917 | obj->ring = NULL; |
| 1918 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1919 | obj->last_read_seqno = 0; |
| 1920 | obj->last_write_seqno = 0; |
| 1921 | obj->base.write_domain = 0; |
| 1922 | |
| 1923 | obj->last_fenced_seqno = 0; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1924 | obj->fenced_gpu_access = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1925 | |
| 1926 | obj->active = 0; |
| 1927 | drm_gem_object_unreference(&obj->base); |
| 1928 | |
| 1929 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1930 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1931 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1932 | static int |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 1933 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1934 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1935 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1936 | struct intel_ring_buffer *ring; |
| 1937 | int ret, i, j; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1938 | |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 1939 | /* Carefully retire all requests without writing to the rings */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1940 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 1941 | ret = intel_ring_idle(ring); |
| 1942 | if (ret) |
| 1943 | return ret; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1944 | } |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1945 | i915_gem_retire_requests(dev); |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 1946 | |
| 1947 | /* Finally reset hw state */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1948 | for_each_ring(ring, dev_priv, i) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 1949 | intel_ring_init_seqno(ring, seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1950 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1951 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
| 1952 | ring->sync_seqno[j] = 0; |
| 1953 | } |
| 1954 | |
| 1955 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1956 | } |
| 1957 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 1958 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
| 1959 | { |
| 1960 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1961 | int ret; |
| 1962 | |
| 1963 | if (seqno == 0) |
| 1964 | return -EINVAL; |
| 1965 | |
| 1966 | /* HWS page needs to be set less than what we |
| 1967 | * will inject to ring |
| 1968 | */ |
| 1969 | ret = i915_gem_init_seqno(dev, seqno - 1); |
| 1970 | if (ret) |
| 1971 | return ret; |
| 1972 | |
| 1973 | /* Carefully set the last_seqno value so that wrap |
| 1974 | * detection still works |
| 1975 | */ |
| 1976 | dev_priv->next_seqno = seqno; |
| 1977 | dev_priv->last_seqno = seqno - 1; |
| 1978 | if (dev_priv->last_seqno == 0) |
| 1979 | dev_priv->last_seqno--; |
| 1980 | |
| 1981 | return 0; |
| 1982 | } |
| 1983 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1984 | int |
| 1985 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1986 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1987 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1988 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1989 | /* reserve 0 for non-seqno */ |
| 1990 | if (dev_priv->next_seqno == 0) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 1991 | int ret = i915_gem_init_seqno(dev, 0); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1992 | if (ret) |
| 1993 | return ret; |
| 1994 | |
| 1995 | dev_priv->next_seqno = 1; |
| 1996 | } |
| 1997 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1998 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1999 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2000 | } |
| 2001 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2002 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2003 | i915_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2004 | struct drm_file *file, |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2005 | u32 *out_seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2006 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2007 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2008 | struct drm_i915_gem_request *request; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2009 | u32 request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2010 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2011 | int ret; |
| 2012 | |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2013 | /* |
| 2014 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 2015 | * after having emitted the batchbuffer command. Hence we need to fix |
| 2016 | * things up similar to emitting the lazy request. The difference here |
| 2017 | * is that the flush _must_ happen before the next request, no matter |
| 2018 | * what. |
| 2019 | */ |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2020 | ret = intel_ring_flush_all_caches(ring); |
| 2021 | if (ret) |
| 2022 | return ret; |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2023 | |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2024 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
| 2025 | if (request == NULL) |
| 2026 | return -ENOMEM; |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2027 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2028 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2029 | /* Record the position of the start of the request so that |
| 2030 | * should we detect the updated seqno part-way through the |
| 2031 | * GPU processing the request, we never over-estimate the |
| 2032 | * position of the head. |
| 2033 | */ |
| 2034 | request_ring_position = intel_ring_get_tail(ring); |
| 2035 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2036 | ret = ring->add_request(ring); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2037 | if (ret) { |
| 2038 | kfree(request); |
| 2039 | return ret; |
| 2040 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2041 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2042 | request->seqno = intel_ring_get_seqno(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2043 | request->ring = ring; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2044 | request->tail = request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2045 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2046 | was_empty = list_empty(&ring->request_list); |
| 2047 | list_add_tail(&request->list, &ring->request_list); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2048 | request->file_priv = NULL; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2049 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2050 | if (file) { |
| 2051 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 2052 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2053 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2054 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2055 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2056 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2057 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2058 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2059 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2060 | trace_i915_gem_request_add(ring, request->seqno); |
Daniel Vetter | 5391d0c | 2012-01-25 14:03:57 +0100 | [diff] [blame] | 2061 | ring->outstanding_lazy_request = 0; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2062 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2063 | if (!dev_priv->mm.suspended) { |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 2064 | if (i915_enable_hangcheck) { |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 2065 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
Chris Wilson | cecc21f | 2012-10-05 17:02:56 +0100 | [diff] [blame] | 2066 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 2067 | } |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2068 | if (was_empty) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 2069 | queue_delayed_work(dev_priv->wq, |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2070 | &dev_priv->mm.retire_work, |
| 2071 | round_jiffies_up_relative(HZ)); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2072 | intel_mark_busy(dev_priv->dev); |
| 2073 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2074 | } |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2075 | |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2076 | if (out_seqno) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2077 | *out_seqno = request->seqno; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2078 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2079 | } |
| 2080 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2081 | static inline void |
| 2082 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2083 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2084 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2085 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2086 | if (!file_priv) |
| 2087 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2088 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2089 | spin_lock(&file_priv->mm.lock); |
Herton Ronaldo Krzesinski | 09bfa51 | 2011-03-17 13:45:12 +0000 | [diff] [blame] | 2090 | if (request->file_priv) { |
| 2091 | list_del(&request->client_list); |
| 2092 | request->file_priv = NULL; |
| 2093 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2094 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2095 | } |
| 2096 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2097 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 2098 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2099 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2100 | while (!list_empty(&ring->request_list)) { |
| 2101 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2102 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2103 | request = list_first_entry(&ring->request_list, |
| 2104 | struct drm_i915_gem_request, |
| 2105 | list); |
| 2106 | |
| 2107 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2108 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2109 | kfree(request); |
| 2110 | } |
| 2111 | |
| 2112 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2113 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2114 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2115 | obj = list_first_entry(&ring->active_list, |
| 2116 | struct drm_i915_gem_object, |
| 2117 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2118 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2119 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2120 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2121 | } |
| 2122 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2123 | static void i915_gem_reset_fences(struct drm_device *dev) |
| 2124 | { |
| 2125 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2126 | int i; |
| 2127 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 2128 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2129 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 2130 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 2131 | if (reg->obj) |
| 2132 | i915_gem_object_fence_lost(reg->obj); |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 2133 | |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 2134 | i915_gem_write_fence(dev, i, NULL); |
| 2135 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 2136 | reg->pin_count = 0; |
| 2137 | reg->obj = NULL; |
| 2138 | INIT_LIST_HEAD(®->lru_list); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2139 | } |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 2140 | |
| 2141 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2142 | } |
| 2143 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2144 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2145 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2146 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2147 | struct drm_i915_gem_object *obj; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2148 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2149 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2150 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2151 | for_each_ring(ring, dev_priv, i) |
| 2152 | i915_gem_reset_ring_lists(dev_priv, ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2153 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2154 | /* Move everything out of the GPU domains to ensure we do any |
| 2155 | * necessary invalidation upon reuse. |
| 2156 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2157 | list_for_each_entry(obj, |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 2158 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2159 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 2160 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2161 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 2162 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2163 | |
| 2164 | /* The fence registers are invalidated so clear them out */ |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2165 | i915_gem_reset_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2166 | } |
| 2167 | |
| 2168 | /** |
| 2169 | * This function clears the request list as sequence numbers are passed. |
| 2170 | */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2171 | void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2172 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2173 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2174 | uint32_t seqno; |
| 2175 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2176 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 2177 | return; |
| 2178 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2179 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2180 | |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 2181 | seqno = ring->get_seqno(ring, true); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2182 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2183 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2184 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2185 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2186 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2187 | struct drm_i915_gem_request, |
| 2188 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2189 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2190 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2191 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2192 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2193 | trace_i915_gem_request_retire(ring, request->seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2194 | /* We know the GPU must have read the request to have |
| 2195 | * sent us the seqno + interrupt, so use the position |
| 2196 | * of tail of the request to update the last known position |
| 2197 | * of the GPU head. |
| 2198 | */ |
| 2199 | ring->last_retired_head = request->tail; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2200 | |
| 2201 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2202 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2203 | kfree(request); |
| 2204 | } |
| 2205 | |
| 2206 | /* Move any buffers on the active list that are no longer referenced |
| 2207 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 2208 | */ |
| 2209 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2210 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2211 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2212 | obj = list_first_entry(&ring->active_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2213 | struct drm_i915_gem_object, |
| 2214 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2215 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2216 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2217 | break; |
| 2218 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2219 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2220 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2221 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2222 | if (unlikely(ring->trace_irq_seqno && |
| 2223 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2224 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2225 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2226 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2227 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2228 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2229 | } |
| 2230 | |
| 2231 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2232 | i915_gem_retire_requests(struct drm_device *dev) |
| 2233 | { |
| 2234 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2235 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2236 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2237 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2238 | for_each_ring(ring, dev_priv, i) |
| 2239 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2240 | } |
| 2241 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2242 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2243 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2244 | { |
| 2245 | drm_i915_private_t *dev_priv; |
| 2246 | struct drm_device *dev; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2247 | struct intel_ring_buffer *ring; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2248 | bool idle; |
| 2249 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2250 | |
| 2251 | dev_priv = container_of(work, drm_i915_private_t, |
| 2252 | mm.retire_work.work); |
| 2253 | dev = dev_priv->dev; |
| 2254 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2255 | /* Come back later if the device is busy... */ |
| 2256 | if (!mutex_trylock(&dev->struct_mutex)) { |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2257 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 2258 | round_jiffies_up_relative(HZ)); |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2259 | return; |
| 2260 | } |
| 2261 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2262 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2263 | |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2264 | /* Send a periodic flush down the ring so we don't hold onto GEM |
| 2265 | * objects indefinitely. |
| 2266 | */ |
| 2267 | idle = true; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2268 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2269 | if (ring->gpu_caches_dirty) |
| 2270 | i915_add_request(ring, NULL, NULL); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2271 | |
| 2272 | idle &= list_empty(&ring->request_list); |
| 2273 | } |
| 2274 | |
| 2275 | if (!dev_priv->mm.suspended && !idle) |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2276 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 2277 | round_jiffies_up_relative(HZ)); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2278 | if (idle) |
| 2279 | intel_mark_idle(dev); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2280 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2281 | mutex_unlock(&dev->struct_mutex); |
| 2282 | } |
| 2283 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2284 | /** |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2285 | * Ensures that an object will eventually get non-busy by flushing any required |
| 2286 | * write domains, emitting any outstanding lazy request and retiring and |
| 2287 | * completed requests. |
| 2288 | */ |
| 2289 | static int |
| 2290 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 2291 | { |
| 2292 | int ret; |
| 2293 | |
| 2294 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2295 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2296 | if (ret) |
| 2297 | return ret; |
| 2298 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2299 | i915_gem_retire_requests_ring(obj->ring); |
| 2300 | } |
| 2301 | |
| 2302 | return 0; |
| 2303 | } |
| 2304 | |
| 2305 | /** |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2306 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 2307 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 2308 | * |
| 2309 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 2310 | * the timeout parameter. |
| 2311 | * -ETIME: object is still busy after timeout |
| 2312 | * -ERESTARTSYS: signal interrupted the wait |
| 2313 | * -ENONENT: object doesn't exist |
| 2314 | * Also possible, but rare: |
| 2315 | * -EAGAIN: GPU wedged |
| 2316 | * -ENOMEM: damn |
| 2317 | * -ENODEV: Internal IRQ fail |
| 2318 | * -E?: The add request failed |
| 2319 | * |
| 2320 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 2321 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 2322 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 2323 | * without holding struct_mutex the object may become re-busied before this |
| 2324 | * function completes. A similar but shorter * race condition exists in the busy |
| 2325 | * ioctl |
| 2326 | */ |
| 2327 | int |
| 2328 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 2329 | { |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2330 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2331 | struct drm_i915_gem_wait *args = data; |
| 2332 | struct drm_i915_gem_object *obj; |
| 2333 | struct intel_ring_buffer *ring = NULL; |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2334 | struct timespec timeout_stack, *timeout = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2335 | unsigned reset_counter; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2336 | u32 seqno = 0; |
| 2337 | int ret = 0; |
| 2338 | |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2339 | if (args->timeout_ns >= 0) { |
| 2340 | timeout_stack = ns_to_timespec(args->timeout_ns); |
| 2341 | timeout = &timeout_stack; |
| 2342 | } |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2343 | |
| 2344 | ret = i915_mutex_lock_interruptible(dev); |
| 2345 | if (ret) |
| 2346 | return ret; |
| 2347 | |
| 2348 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 2349 | if (&obj->base == NULL) { |
| 2350 | mutex_unlock(&dev->struct_mutex); |
| 2351 | return -ENOENT; |
| 2352 | } |
| 2353 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2354 | /* Need to make sure the object gets inactive eventually. */ |
| 2355 | ret = i915_gem_object_flush_active(obj); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2356 | if (ret) |
| 2357 | goto out; |
| 2358 | |
| 2359 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2360 | seqno = obj->last_read_seqno; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2361 | ring = obj->ring; |
| 2362 | } |
| 2363 | |
| 2364 | if (seqno == 0) |
| 2365 | goto out; |
| 2366 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2367 | /* Do this after OLR check to make sure we make forward progress polling |
| 2368 | * on this IOCTL with a 0 timeout (like busy ioctl) |
| 2369 | */ |
| 2370 | if (!args->timeout_ns) { |
| 2371 | ret = -ETIME; |
| 2372 | goto out; |
| 2373 | } |
| 2374 | |
| 2375 | drm_gem_object_unreference(&obj->base); |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2376 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2377 | mutex_unlock(&dev->struct_mutex); |
| 2378 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2379 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout); |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2380 | if (timeout) { |
| 2381 | WARN_ON(!timespec_valid(timeout)); |
| 2382 | args->timeout_ns = timespec_to_ns(timeout); |
| 2383 | } |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2384 | return ret; |
| 2385 | |
| 2386 | out: |
| 2387 | drm_gem_object_unreference(&obj->base); |
| 2388 | mutex_unlock(&dev->struct_mutex); |
| 2389 | return ret; |
| 2390 | } |
| 2391 | |
| 2392 | /** |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2393 | * i915_gem_object_sync - sync an object to a ring. |
| 2394 | * |
| 2395 | * @obj: object which may be in use on another ring. |
| 2396 | * @to: ring we wish to use the object on. May be NULL. |
| 2397 | * |
| 2398 | * This code is meant to abstract object synchronization with the GPU. |
| 2399 | * Calling with NULL implies synchronizing the object with the CPU |
| 2400 | * rather than a particular GPU ring. |
| 2401 | * |
| 2402 | * Returns 0 if successful, else propagates up the lower layer error. |
| 2403 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2404 | int |
| 2405 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 2406 | struct intel_ring_buffer *to) |
| 2407 | { |
| 2408 | struct intel_ring_buffer *from = obj->ring; |
| 2409 | u32 seqno; |
| 2410 | int ret, idx; |
| 2411 | |
| 2412 | if (from == NULL || to == from) |
| 2413 | return 0; |
| 2414 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2415 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2416 | return i915_gem_object_wait_rendering(obj, false); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2417 | |
| 2418 | idx = intel_ring_sync_index(from, to); |
| 2419 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2420 | seqno = obj->last_read_seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2421 | if (seqno <= from->sync_seqno[idx]) |
| 2422 | return 0; |
| 2423 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 2424 | ret = i915_gem_check_olr(obj->ring, seqno); |
| 2425 | if (ret) |
| 2426 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2427 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 2428 | ret = to->sync_to(to, from, seqno); |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2429 | if (!ret) |
Mika Kuoppala | 7b01e26 | 2012-11-28 17:18:45 +0200 | [diff] [blame] | 2430 | /* We use last_read_seqno because sync_to() |
| 2431 | * might have just caused seqno wrap under |
| 2432 | * the radar. |
| 2433 | */ |
| 2434 | from->sync_seqno[idx] = obj->last_read_seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2435 | |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2436 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2437 | } |
| 2438 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2439 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 2440 | { |
| 2441 | u32 old_write_domain, old_read_domains; |
| 2442 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2443 | /* Force a pagefault for domain tracking on next user access */ |
| 2444 | i915_gem_release_mmap(obj); |
| 2445 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 2446 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 2447 | return; |
| 2448 | |
Chris Wilson | 97c809fd | 2012-10-09 19:24:38 +0100 | [diff] [blame] | 2449 | /* Wait for any direct GTT access to complete */ |
| 2450 | mb(); |
| 2451 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2452 | old_read_domains = obj->base.read_domains; |
| 2453 | old_write_domain = obj->base.write_domain; |
| 2454 | |
| 2455 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 2456 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 2457 | |
| 2458 | trace_i915_gem_object_change_domain(obj, |
| 2459 | old_read_domains, |
| 2460 | old_write_domain); |
| 2461 | } |
| 2462 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2463 | /** |
| 2464 | * Unbinds an object from the GTT aperture. |
| 2465 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2466 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2467 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2468 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2469 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2470 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2471 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2472 | if (obj->gtt_space == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2473 | return 0; |
| 2474 | |
Chris Wilson | 31d8d65 | 2012-05-24 19:11:20 +0100 | [diff] [blame] | 2475 | if (obj->pin_count) |
| 2476 | return -EBUSY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2477 | |
Chris Wilson | c4670ad | 2012-08-20 10:23:27 +0100 | [diff] [blame] | 2478 | BUG_ON(obj->pages == NULL); |
| 2479 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2480 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2481 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2482 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2483 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2484 | * should be safe and we need to cleanup or else we might |
| 2485 | * cause memory corruption through use-after-free. |
| 2486 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2487 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2488 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2489 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2490 | /* release the fence reg _after_ flushing */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2491 | ret = i915_gem_object_put_fence(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2492 | if (ret) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2493 | return ret; |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2494 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2495 | trace_i915_gem_object_unbind(obj); |
| 2496 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 2497 | if (obj->has_global_gtt_mapping) |
| 2498 | i915_gem_gtt_unbind_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2499 | if (obj->has_aliasing_ppgtt_mapping) { |
| 2500 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); |
| 2501 | obj->has_aliasing_ppgtt_mapping = 0; |
| 2502 | } |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2503 | i915_gem_gtt_finish_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2504 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2505 | list_del(&obj->mm_list); |
| 2506 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2507 | /* Avoid an unnecessary call to unbind on rebind. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2508 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2509 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2510 | drm_mm_put_block(obj->gtt_space); |
| 2511 | obj->gtt_space = NULL; |
| 2512 | obj->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2513 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2514 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2515 | } |
| 2516 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2517 | int i915_gpu_idle(struct drm_device *dev) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2518 | { |
| 2519 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2520 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2521 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2522 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2523 | /* Flush everything onto the inactive list. */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2524 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | b6c7488 | 2012-08-14 14:35:14 -0700 | [diff] [blame] | 2525 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
| 2526 | if (ret) |
| 2527 | return ret; |
| 2528 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2529 | ret = intel_ring_idle(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2530 | if (ret) |
| 2531 | return ret; |
| 2532 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2533 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2534 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2535 | } |
| 2536 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2537 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 2538 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2539 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2540 | drm_i915_private_t *dev_priv = dev->dev_private; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2541 | int fence_reg; |
| 2542 | int fence_pitch_shift; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2543 | uint64_t val; |
| 2544 | |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2545 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2546 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
| 2547 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2548 | } else { |
| 2549 | fence_reg = FENCE_REG_965_0; |
| 2550 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
| 2551 | } |
| 2552 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2553 | if (obj) { |
| 2554 | u32 size = obj->gtt_space->size; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2555 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2556 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
| 2557 | 0xfffff000) << 32; |
| 2558 | val |= obj->gtt_offset & 0xfffff000; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2559 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2560 | if (obj->tiling_mode == I915_TILING_Y) |
| 2561 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2562 | val |= I965_FENCE_REG_VALID; |
| 2563 | } else |
| 2564 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2565 | |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2566 | fence_reg += reg * 8; |
| 2567 | I915_WRITE64(fence_reg, val); |
| 2568 | POSTING_READ(fence_reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2569 | } |
| 2570 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2571 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 2572 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2573 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2574 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2575 | u32 val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2576 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2577 | if (obj) { |
| 2578 | u32 size = obj->gtt_space->size; |
| 2579 | int pitch_val; |
| 2580 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2581 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2582 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2583 | (size & -size) != size || |
| 2584 | (obj->gtt_offset & (size - 1)), |
| 2585 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2586 | obj->gtt_offset, obj->map_and_fenceable, size); |
| 2587 | |
| 2588 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 2589 | tile_width = 128; |
| 2590 | else |
| 2591 | tile_width = 512; |
| 2592 | |
| 2593 | /* Note: pitch better be a power of two tile widths */ |
| 2594 | pitch_val = obj->stride / tile_width; |
| 2595 | pitch_val = ffs(pitch_val) - 1; |
| 2596 | |
| 2597 | val = obj->gtt_offset; |
| 2598 | if (obj->tiling_mode == I915_TILING_Y) |
| 2599 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2600 | val |= I915_FENCE_SIZE_BITS(size); |
| 2601 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2602 | val |= I830_FENCE_REG_VALID; |
| 2603 | } else |
| 2604 | val = 0; |
| 2605 | |
| 2606 | if (reg < 8) |
| 2607 | reg = FENCE_REG_830_0 + reg * 4; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2608 | else |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2609 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2610 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2611 | I915_WRITE(reg, val); |
| 2612 | POSTING_READ(reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2613 | } |
| 2614 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2615 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 2616 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2617 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2618 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2619 | uint32_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2620 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2621 | if (obj) { |
| 2622 | u32 size = obj->gtt_space->size; |
| 2623 | uint32_t pitch_val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2624 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2625 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
| 2626 | (size & -size) != size || |
| 2627 | (obj->gtt_offset & (size - 1)), |
| 2628 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", |
| 2629 | obj->gtt_offset, size); |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2630 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2631 | pitch_val = obj->stride / 128; |
| 2632 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2633 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2634 | val = obj->gtt_offset; |
| 2635 | if (obj->tiling_mode == I915_TILING_Y) |
| 2636 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2637 | val |= I830_FENCE_SIZE_BITS(size); |
| 2638 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2639 | val |= I830_FENCE_REG_VALID; |
| 2640 | } else |
| 2641 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2642 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2643 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 2644 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 2645 | } |
| 2646 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2647 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
| 2648 | { |
| 2649 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
| 2650 | } |
| 2651 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2652 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 2653 | struct drm_i915_gem_object *obj) |
| 2654 | { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2655 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2656 | |
| 2657 | /* Ensure that all CPU reads are completed before installing a fence |
| 2658 | * and all writes before removing the fence. |
| 2659 | */ |
| 2660 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
| 2661 | mb(); |
| 2662 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2663 | switch (INTEL_INFO(dev)->gen) { |
| 2664 | case 7: |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2665 | case 6: |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2666 | case 5: |
| 2667 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
| 2668 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
| 2669 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
Ben Widawsky | 7dbf9d6 | 2012-12-18 10:31:22 -0800 | [diff] [blame] | 2670 | default: BUG(); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2671 | } |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2672 | |
| 2673 | /* And similarly be paranoid that no direct access to this region |
| 2674 | * is reordered to before the fence is installed. |
| 2675 | */ |
| 2676 | if (i915_gem_object_needs_mb(obj)) |
| 2677 | mb(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2678 | } |
| 2679 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2680 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 2681 | struct drm_i915_fence_reg *fence) |
| 2682 | { |
| 2683 | return fence - dev_priv->fence_regs; |
| 2684 | } |
| 2685 | |
| 2686 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 2687 | struct drm_i915_fence_reg *fence, |
| 2688 | bool enable) |
| 2689 | { |
| 2690 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2691 | int reg = fence_number(dev_priv, fence); |
| 2692 | |
| 2693 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
| 2694 | |
| 2695 | if (enable) { |
| 2696 | obj->fence_reg = reg; |
| 2697 | fence->obj = obj; |
| 2698 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 2699 | } else { |
| 2700 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 2701 | fence->obj = NULL; |
| 2702 | list_del_init(&fence->lru_list); |
| 2703 | } |
| 2704 | } |
| 2705 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2706 | static int |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2707 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2708 | { |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 2709 | if (obj->last_fenced_seqno) { |
Chris Wilson | 86d5bc3 | 2012-07-20 12:41:04 +0100 | [diff] [blame] | 2710 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
Chris Wilson | 1899184 | 2012-04-17 15:31:29 +0100 | [diff] [blame] | 2711 | if (ret) |
| 2712 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2713 | |
| 2714 | obj->last_fenced_seqno = 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2715 | } |
| 2716 | |
Chris Wilson | 86d5bc3 | 2012-07-20 12:41:04 +0100 | [diff] [blame] | 2717 | obj->fenced_gpu_access = false; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2718 | return 0; |
| 2719 | } |
| 2720 | |
| 2721 | int |
| 2722 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 2723 | { |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2724 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 2725 | struct drm_i915_fence_reg *fence; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2726 | int ret; |
| 2727 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2728 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2729 | if (ret) |
| 2730 | return ret; |
| 2731 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2732 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 2733 | return 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2734 | |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 2735 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
| 2736 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2737 | i915_gem_object_fence_lost(obj); |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 2738 | i915_gem_object_update_fence(obj, fence, false); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2739 | |
| 2740 | return 0; |
| 2741 | } |
| 2742 | |
| 2743 | static struct drm_i915_fence_reg * |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2744 | i915_find_fence_reg(struct drm_device *dev) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2745 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2746 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2747 | struct drm_i915_fence_reg *reg, *avail; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2748 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2749 | |
| 2750 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2751 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2752 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2753 | reg = &dev_priv->fence_regs[i]; |
| 2754 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2755 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2756 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2757 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2758 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2759 | } |
| 2760 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2761 | if (avail == NULL) |
| 2762 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2763 | |
| 2764 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2765 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2766 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2767 | continue; |
| 2768 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2769 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2770 | } |
| 2771 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2772 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2773 | } |
| 2774 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2775 | /** |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2776 | * i915_gem_object_get_fence - set up fencing for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2777 | * @obj: object to map through a fence reg |
| 2778 | * |
| 2779 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2780 | * to them without having to worry about swizzling if the object is tiled. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2781 | * This function walks the fence regs looking for a free one for @obj, |
| 2782 | * stealing one if it can't find any. |
| 2783 | * |
| 2784 | * It then sets up the reg based on the object's properties: address, pitch |
| 2785 | * and tiling format. |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2786 | * |
| 2787 | * For an untiled surface, this removes any existing fence. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2788 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2789 | int |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 2790 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2791 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2792 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2793 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2794 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2795 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2796 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2797 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2798 | /* Have we updated the tiling parameters upon the object and so |
| 2799 | * will need to serialise the write to the associated fence register? |
| 2800 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2801 | if (obj->fence_dirty) { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2802 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2803 | if (ret) |
| 2804 | return ret; |
| 2805 | } |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2806 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2807 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2808 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2809 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2810 | if (!obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2811 | list_move_tail(®->lru_list, |
| 2812 | &dev_priv->mm.fence_list); |
| 2813 | return 0; |
| 2814 | } |
| 2815 | } else if (enable) { |
| 2816 | reg = i915_find_fence_reg(dev); |
| 2817 | if (reg == NULL) |
| 2818 | return -EDEADLK; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2819 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2820 | if (reg->obj) { |
| 2821 | struct drm_i915_gem_object *old = reg->obj; |
| 2822 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2823 | ret = i915_gem_object_wait_fence(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2824 | if (ret) |
| 2825 | return ret; |
| 2826 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2827 | i915_gem_object_fence_lost(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2828 | } |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2829 | } else |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2830 | return 0; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2831 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2832 | i915_gem_object_update_fence(obj, reg, enable); |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2833 | obj->fence_dirty = false; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2834 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2835 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2836 | } |
| 2837 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2838 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
| 2839 | struct drm_mm_node *gtt_space, |
| 2840 | unsigned long cache_level) |
| 2841 | { |
| 2842 | struct drm_mm_node *other; |
| 2843 | |
| 2844 | /* On non-LLC machines we have to be careful when putting differing |
| 2845 | * types of snoopable memory together to avoid the prefetcher |
Damien Lespiau | 4239ca7 | 2012-12-03 16:26:16 +0000 | [diff] [blame] | 2846 | * crossing memory domains and dying. |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2847 | */ |
| 2848 | if (HAS_LLC(dev)) |
| 2849 | return true; |
| 2850 | |
| 2851 | if (gtt_space == NULL) |
| 2852 | return true; |
| 2853 | |
| 2854 | if (list_empty(>t_space->node_list)) |
| 2855 | return true; |
| 2856 | |
| 2857 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 2858 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 2859 | return false; |
| 2860 | |
| 2861 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 2862 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 2863 | return false; |
| 2864 | |
| 2865 | return true; |
| 2866 | } |
| 2867 | |
| 2868 | static void i915_gem_verify_gtt(struct drm_device *dev) |
| 2869 | { |
| 2870 | #if WATCH_GTT |
| 2871 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2872 | struct drm_i915_gem_object *obj; |
| 2873 | int err = 0; |
| 2874 | |
| 2875 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { |
| 2876 | if (obj->gtt_space == NULL) { |
| 2877 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); |
| 2878 | err++; |
| 2879 | continue; |
| 2880 | } |
| 2881 | |
| 2882 | if (obj->cache_level != obj->gtt_space->color) { |
| 2883 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", |
| 2884 | obj->gtt_space->start, |
| 2885 | obj->gtt_space->start + obj->gtt_space->size, |
| 2886 | obj->cache_level, |
| 2887 | obj->gtt_space->color); |
| 2888 | err++; |
| 2889 | continue; |
| 2890 | } |
| 2891 | |
| 2892 | if (!i915_gem_valid_gtt_space(dev, |
| 2893 | obj->gtt_space, |
| 2894 | obj->cache_level)) { |
| 2895 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", |
| 2896 | obj->gtt_space->start, |
| 2897 | obj->gtt_space->start + obj->gtt_space->size, |
| 2898 | obj->cache_level); |
| 2899 | err++; |
| 2900 | continue; |
| 2901 | } |
| 2902 | } |
| 2903 | |
| 2904 | WARN_ON(err); |
| 2905 | #endif |
| 2906 | } |
| 2907 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2908 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2909 | * Finds free space in the GTT aperture and binds the object there. |
| 2910 | */ |
| 2911 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2912 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2913 | unsigned alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 2914 | bool map_and_fenceable, |
| 2915 | bool nonblocking) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2916 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2917 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2918 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 2919 | struct drm_mm_node *node; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2920 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2921 | bool mappable, fenceable; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2922 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2923 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2924 | fence_size = i915_gem_get_gtt_size(dev, |
| 2925 | obj->base.size, |
| 2926 | obj->tiling_mode); |
| 2927 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 2928 | obj->base.size, |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 2929 | obj->tiling_mode, true); |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2930 | unfenced_alignment = |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 2931 | i915_gem_get_gtt_alignment(dev, |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2932 | obj->base.size, |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 2933 | obj->tiling_mode, false); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2934 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2935 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2936 | alignment = map_and_fenceable ? fence_alignment : |
| 2937 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2938 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2939 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2940 | return -EINVAL; |
| 2941 | } |
| 2942 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2943 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2944 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2945 | /* If the object is bigger than the entire aperture, reject it early |
| 2946 | * before evicting everything in a vain attempt to find space. |
| 2947 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2948 | if (obj->base.size > |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 2949 | (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2950 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2951 | return -E2BIG; |
| 2952 | } |
| 2953 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2954 | ret = i915_gem_object_get_pages(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2955 | if (ret) |
| 2956 | return ret; |
| 2957 | |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 2958 | i915_gem_object_pin_pages(obj); |
| 2959 | |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 2960 | node = kzalloc(sizeof(*node), GFP_KERNEL); |
| 2961 | if (node == NULL) { |
| 2962 | i915_gem_object_unpin_pages(obj); |
| 2963 | return -ENOMEM; |
| 2964 | } |
| 2965 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2966 | search_free: |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2967 | if (map_and_fenceable) |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 2968 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node, |
| 2969 | size, alignment, obj->cache_level, |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 2970 | 0, dev_priv->gtt.mappable_end); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2971 | else |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 2972 | ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node, |
| 2973 | size, alignment, obj->cache_level); |
| 2974 | if (ret) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2975 | ret = i915_gem_evict_something(dev, size, alignment, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2976 | obj->cache_level, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 2977 | map_and_fenceable, |
| 2978 | nonblocking); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 2979 | if (ret == 0) |
| 2980 | goto search_free; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2981 | |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 2982 | i915_gem_object_unpin_pages(obj); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 2983 | kfree(node); |
| 2984 | return ret; |
| 2985 | } |
| 2986 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) { |
| 2987 | i915_gem_object_unpin_pages(obj); |
| 2988 | drm_mm_put_block(node); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2989 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2990 | } |
| 2991 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2992 | ret = i915_gem_gtt_prepare_object(obj); |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2993 | if (ret) { |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 2994 | i915_gem_object_unpin_pages(obj); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 2995 | drm_mm_put_block(node); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2996 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2997 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2998 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2999 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3000 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 3001 | |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3002 | obj->gtt_space = node; |
| 3003 | obj->gtt_offset = node->start; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3004 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3005 | fenceable = |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3006 | node->size == fence_size && |
| 3007 | (node->start & (fence_alignment - 1)) == 0; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3008 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3009 | mappable = |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 3010 | obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3011 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3012 | obj->map_and_fenceable = mappable && fenceable; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3013 | |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 3014 | i915_gem_object_unpin_pages(obj); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3015 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3016 | i915_gem_verify_gtt(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3017 | return 0; |
| 3018 | } |
| 3019 | |
| 3020 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3021 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3022 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3023 | /* If we don't have a page list set up, then we're not pinned |
| 3024 | * to GPU, and we can ignore the cache flush because it'll happen |
| 3025 | * again at bind time. |
| 3026 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3027 | if (obj->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3028 | return; |
| 3029 | |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3030 | /* |
| 3031 | * Stolen memory is always coherent with the GPU as it is explicitly |
| 3032 | * marked as wc by the system, or the system is cache-coherent. |
| 3033 | */ |
| 3034 | if (obj->stolen) |
| 3035 | return; |
| 3036 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3037 | /* If the GPU is snooping the contents of the CPU cache, |
| 3038 | * we do not need to manually clear the CPU cache lines. However, |
| 3039 | * the caches are only snooped when the render cache is |
| 3040 | * flushed/invalidated. As we always have to emit invalidations |
| 3041 | * and flushes when moving into and out of the RENDER domain, correct |
| 3042 | * snooping behaviour occurs naturally as the result of our domain |
| 3043 | * tracking. |
| 3044 | */ |
| 3045 | if (obj->cache_level != I915_CACHE_NONE) |
| 3046 | return; |
| 3047 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3048 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 3049 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3050 | drm_clflush_sg(obj->pages); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3051 | } |
| 3052 | |
| 3053 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3054 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3055 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3056 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3057 | uint32_t old_write_domain; |
| 3058 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3059 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3060 | return; |
| 3061 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3062 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3063 | * to it immediately go to main memory as far as we know, so there's |
| 3064 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3065 | * |
| 3066 | * However, we do have to enforce the order so that all writes through |
| 3067 | * the GTT land before any writes to the device, such as updates to |
| 3068 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3069 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3070 | wmb(); |
| 3071 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3072 | old_write_domain = obj->base.write_domain; |
| 3073 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3074 | |
| 3075 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3076 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3077 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3078 | } |
| 3079 | |
| 3080 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3081 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3082 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3083 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3084 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3085 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3086 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3087 | return; |
| 3088 | |
| 3089 | i915_gem_clflush_object(obj); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 3090 | i915_gem_chipset_flush(obj->base.dev); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3091 | old_write_domain = obj->base.write_domain; |
| 3092 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3093 | |
| 3094 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3095 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3096 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3097 | } |
| 3098 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3099 | /** |
| 3100 | * Moves a single object to the GTT read, and possibly write domain. |
| 3101 | * |
| 3102 | * This function returns when the move is complete, including waiting on |
| 3103 | * flushes to occur. |
| 3104 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3105 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3106 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3107 | { |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3108 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3109 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3110 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3111 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3112 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3113 | if (obj->gtt_space == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3114 | return -EINVAL; |
| 3115 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3116 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3117 | return 0; |
| 3118 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3119 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3120 | if (ret) |
| 3121 | return ret; |
| 3122 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 3123 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3124 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3125 | /* Serialise direct access to this object with the barriers for |
| 3126 | * coherent writes from the GPU, by effectively invalidating the |
| 3127 | * GTT domain upon first access. |
| 3128 | */ |
| 3129 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3130 | mb(); |
| 3131 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3132 | old_write_domain = obj->base.write_domain; |
| 3133 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3134 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3135 | /* It should now be out of any other write domains, and we can update |
| 3136 | * the domain values for our changes. |
| 3137 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3138 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 3139 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3140 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3141 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 3142 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 3143 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3144 | } |
| 3145 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3146 | trace_i915_gem_object_change_domain(obj, |
| 3147 | old_read_domains, |
| 3148 | old_write_domain); |
| 3149 | |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3150 | /* And bump the LRU for this access */ |
| 3151 | if (i915_gem_object_is_inactive(obj)) |
| 3152 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 3153 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3154 | return 0; |
| 3155 | } |
| 3156 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3157 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 3158 | enum i915_cache_level cache_level) |
| 3159 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3160 | struct drm_device *dev = obj->base.dev; |
| 3161 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3162 | int ret; |
| 3163 | |
| 3164 | if (obj->cache_level == cache_level) |
| 3165 | return 0; |
| 3166 | |
| 3167 | if (obj->pin_count) { |
| 3168 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 3169 | return -EBUSY; |
| 3170 | } |
| 3171 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3172 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
| 3173 | ret = i915_gem_object_unbind(obj); |
| 3174 | if (ret) |
| 3175 | return ret; |
| 3176 | } |
| 3177 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3178 | if (obj->gtt_space) { |
| 3179 | ret = i915_gem_object_finish_gpu(obj); |
| 3180 | if (ret) |
| 3181 | return ret; |
| 3182 | |
| 3183 | i915_gem_object_finish_gtt(obj); |
| 3184 | |
| 3185 | /* Before SandyBridge, you could not use tiling or fence |
| 3186 | * registers with snooped memory, so relinquish any fences |
| 3187 | * currently pointing to our region in the aperture. |
| 3188 | */ |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3189 | if (INTEL_INFO(dev)->gen < 6) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3190 | ret = i915_gem_object_put_fence(obj); |
| 3191 | if (ret) |
| 3192 | return ret; |
| 3193 | } |
| 3194 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3195 | if (obj->has_global_gtt_mapping) |
| 3196 | i915_gem_gtt_bind_object(obj, cache_level); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3197 | if (obj->has_aliasing_ppgtt_mapping) |
| 3198 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
| 3199 | obj, cache_level); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3200 | |
| 3201 | obj->gtt_space->color = cache_level; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3202 | } |
| 3203 | |
| 3204 | if (cache_level == I915_CACHE_NONE) { |
| 3205 | u32 old_read_domains, old_write_domain; |
| 3206 | |
| 3207 | /* If we're coming from LLC cached, then we haven't |
| 3208 | * actually been tracking whether the data is in the |
| 3209 | * CPU cache or not, since we only allow one bit set |
| 3210 | * in obj->write_domain and have been skipping the clflushes. |
| 3211 | * Just set it to the CPU cache for now. |
| 3212 | */ |
| 3213 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
| 3214 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); |
| 3215 | |
| 3216 | old_read_domains = obj->base.read_domains; |
| 3217 | old_write_domain = obj->base.write_domain; |
| 3218 | |
| 3219 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3220 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3221 | |
| 3222 | trace_i915_gem_object_change_domain(obj, |
| 3223 | old_read_domains, |
| 3224 | old_write_domain); |
| 3225 | } |
| 3226 | |
| 3227 | obj->cache_level = cache_level; |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3228 | i915_gem_verify_gtt(dev); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3229 | return 0; |
| 3230 | } |
| 3231 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3232 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 3233 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3234 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3235 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3236 | struct drm_i915_gem_object *obj; |
| 3237 | int ret; |
| 3238 | |
| 3239 | ret = i915_mutex_lock_interruptible(dev); |
| 3240 | if (ret) |
| 3241 | return ret; |
| 3242 | |
| 3243 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3244 | if (&obj->base == NULL) { |
| 3245 | ret = -ENOENT; |
| 3246 | goto unlock; |
| 3247 | } |
| 3248 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3249 | args->caching = obj->cache_level != I915_CACHE_NONE; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3250 | |
| 3251 | drm_gem_object_unreference(&obj->base); |
| 3252 | unlock: |
| 3253 | mutex_unlock(&dev->struct_mutex); |
| 3254 | return ret; |
| 3255 | } |
| 3256 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3257 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 3258 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3259 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3260 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3261 | struct drm_i915_gem_object *obj; |
| 3262 | enum i915_cache_level level; |
| 3263 | int ret; |
| 3264 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3265 | switch (args->caching) { |
| 3266 | case I915_CACHING_NONE: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3267 | level = I915_CACHE_NONE; |
| 3268 | break; |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3269 | case I915_CACHING_CACHED: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3270 | level = I915_CACHE_LLC; |
| 3271 | break; |
| 3272 | default: |
| 3273 | return -EINVAL; |
| 3274 | } |
| 3275 | |
Ben Widawsky | 3bc2913 | 2012-09-26 16:15:20 -0700 | [diff] [blame] | 3276 | ret = i915_mutex_lock_interruptible(dev); |
| 3277 | if (ret) |
| 3278 | return ret; |
| 3279 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3280 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3281 | if (&obj->base == NULL) { |
| 3282 | ret = -ENOENT; |
| 3283 | goto unlock; |
| 3284 | } |
| 3285 | |
| 3286 | ret = i915_gem_object_set_cache_level(obj, level); |
| 3287 | |
| 3288 | drm_gem_object_unreference(&obj->base); |
| 3289 | unlock: |
| 3290 | mutex_unlock(&dev->struct_mutex); |
| 3291 | return ret; |
| 3292 | } |
| 3293 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3294 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3295 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 3296 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 3297 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3298 | */ |
| 3299 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3300 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 3301 | u32 alignment, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3302 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3303 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3304 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3305 | int ret; |
| 3306 | |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 3307 | if (pipelined != obj->ring) { |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3308 | ret = i915_gem_object_sync(obj, pipelined); |
| 3309 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3310 | return ret; |
| 3311 | } |
| 3312 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3313 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 3314 | * a result, we make sure that the pinning that is about to occur is |
| 3315 | * done with uncached PTEs. This is lowest common denominator for all |
| 3316 | * chipsets. |
| 3317 | * |
| 3318 | * However for gen6+, we could do better by using the GFDT bit instead |
| 3319 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 3320 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 3321 | */ |
| 3322 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); |
| 3323 | if (ret) |
| 3324 | return ret; |
| 3325 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3326 | /* As the user may map the buffer once pinned in the display plane |
| 3327 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 3328 | * always use map_and_fenceable for all scanout buffers. |
| 3329 | */ |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3330 | ret = i915_gem_object_pin(obj, alignment, true, false); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3331 | if (ret) |
| 3332 | return ret; |
| 3333 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3334 | i915_gem_object_flush_cpu_write_domain(obj); |
| 3335 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3336 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3337 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3338 | |
| 3339 | /* It should now be out of any other write domains, and we can update |
| 3340 | * the domain values for our changes. |
| 3341 | */ |
Chris Wilson | e5f1d96 | 2012-07-20 12:41:00 +0100 | [diff] [blame] | 3342 | obj->base.write_domain = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3343 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3344 | |
| 3345 | trace_i915_gem_object_change_domain(obj, |
| 3346 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3347 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3348 | |
| 3349 | return 0; |
| 3350 | } |
| 3351 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3352 | int |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3353 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3354 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3355 | int ret; |
| 3356 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3357 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3358 | return 0; |
| 3359 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3360 | ret = i915_gem_object_wait_rendering(obj, false); |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3361 | if (ret) |
| 3362 | return ret; |
| 3363 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3364 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 3365 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3366 | return 0; |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3367 | } |
| 3368 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3369 | /** |
| 3370 | * Moves a single object to the CPU read, and possibly write domain. |
| 3371 | * |
| 3372 | * This function returns when the move is complete, including waiting on |
| 3373 | * flushes to occur. |
| 3374 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 3375 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3376 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3377 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3378 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3379 | int ret; |
| 3380 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3381 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 3382 | return 0; |
| 3383 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3384 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3385 | if (ret) |
| 3386 | return ret; |
| 3387 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3388 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3389 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3390 | old_write_domain = obj->base.write_domain; |
| 3391 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3392 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3393 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3394 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3395 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3396 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3397 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3398 | } |
| 3399 | |
| 3400 | /* It should now be out of any other write domains, and we can update |
| 3401 | * the domain values for our changes. |
| 3402 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3403 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3404 | |
| 3405 | /* If we're writing through the CPU, then the GPU read domains will |
| 3406 | * need to be invalidated at next use. |
| 3407 | */ |
| 3408 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3409 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3410 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3411 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3412 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3413 | trace_i915_gem_object_change_domain(obj, |
| 3414 | old_read_domains, |
| 3415 | old_write_domain); |
| 3416 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3417 | return 0; |
| 3418 | } |
| 3419 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3420 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3421 | * emitted over 20 msec ago. |
| 3422 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3423 | * Note that if we were to use the current jiffies each time around the loop, |
| 3424 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3425 | * render a frame was over 20ms. |
| 3426 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3427 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3428 | * relatively low latency when blocking on a particular request to finish. |
| 3429 | */ |
| 3430 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3431 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3432 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3433 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3434 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3435 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3436 | struct drm_i915_gem_request *request; |
| 3437 | struct intel_ring_buffer *ring = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3438 | unsigned reset_counter; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3439 | u32 seqno = 0; |
| 3440 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3441 | |
Daniel Vetter | 308887a | 2012-11-14 17:14:06 +0100 | [diff] [blame] | 3442 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 3443 | if (ret) |
| 3444 | return ret; |
| 3445 | |
| 3446 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
| 3447 | if (ret) |
| 3448 | return ret; |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 3449 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3450 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3451 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3452 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3453 | break; |
| 3454 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3455 | ring = request->ring; |
| 3456 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3457 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3458 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3459 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3460 | |
| 3461 | if (seqno == 0) |
| 3462 | return 0; |
| 3463 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3464 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3465 | if (ret == 0) |
| 3466 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3467 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3468 | return ret; |
| 3469 | } |
| 3470 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3471 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3472 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 3473 | uint32_t alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3474 | bool map_and_fenceable, |
| 3475 | bool nonblocking) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3476 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3477 | int ret; |
| 3478 | |
Chris Wilson | 7e81a42 | 2012-09-15 09:41:57 +0100 | [diff] [blame] | 3479 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 3480 | return -EBUSY; |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3481 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3482 | if (obj->gtt_space != NULL) { |
| 3483 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
| 3484 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 3485 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 3486 | "bo is already pinned with incorrect alignment:" |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3487 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
| 3488 | " obj->map_and_fenceable=%d\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3489 | obj->gtt_offset, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3490 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3491 | obj->map_and_fenceable); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3492 | ret = i915_gem_object_unbind(obj); |
| 3493 | if (ret) |
| 3494 | return ret; |
| 3495 | } |
| 3496 | } |
| 3497 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3498 | if (obj->gtt_space == NULL) { |
Chris Wilson | 8742267 | 2012-11-21 13:04:03 +0000 | [diff] [blame] | 3499 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 3500 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3501 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3502 | map_and_fenceable, |
| 3503 | nonblocking); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3504 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3505 | return ret; |
Chris Wilson | 8742267 | 2012-11-21 13:04:03 +0000 | [diff] [blame] | 3506 | |
| 3507 | if (!dev_priv->mm.aliasing_ppgtt) |
| 3508 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3509 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3510 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3511 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
| 3512 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 3513 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3514 | obj->pin_count++; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3515 | obj->pin_mappable |= map_and_fenceable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3516 | |
| 3517 | return 0; |
| 3518 | } |
| 3519 | |
| 3520 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3521 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3522 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3523 | BUG_ON(obj->pin_count == 0); |
| 3524 | BUG_ON(obj->gtt_space == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3525 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3526 | if (--obj->pin_count == 0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3527 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3528 | } |
| 3529 | |
| 3530 | int |
| 3531 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3532 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3533 | { |
| 3534 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3535 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3536 | int ret; |
| 3537 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3538 | ret = i915_mutex_lock_interruptible(dev); |
| 3539 | if (ret) |
| 3540 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3541 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3542 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3543 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3544 | ret = -ENOENT; |
| 3545 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3546 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3547 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3548 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3549 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3550 | ret = -EINVAL; |
| 3551 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3552 | } |
| 3553 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3554 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3555 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3556 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3557 | ret = -EINVAL; |
| 3558 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3559 | } |
| 3560 | |
Chris Wilson | 93be878 | 2013-01-02 10:31:22 +0000 | [diff] [blame] | 3561 | if (obj->user_pin_count == 0) { |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3562 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3563 | if (ret) |
| 3564 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3565 | } |
| 3566 | |
Chris Wilson | 93be878 | 2013-01-02 10:31:22 +0000 | [diff] [blame] | 3567 | obj->user_pin_count++; |
| 3568 | obj->pin_filp = file; |
| 3569 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3570 | /* XXX - flush the CPU caches for pinned objects |
| 3571 | * as the X server doesn't manage domains yet |
| 3572 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3573 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3574 | args->offset = obj->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3575 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3576 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3577 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3578 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3579 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3580 | } |
| 3581 | |
| 3582 | int |
| 3583 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3584 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3585 | { |
| 3586 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3587 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3588 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3589 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3590 | ret = i915_mutex_lock_interruptible(dev); |
| 3591 | if (ret) |
| 3592 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3593 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3594 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3595 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3596 | ret = -ENOENT; |
| 3597 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3598 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3599 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3600 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3601 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 3602 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3603 | ret = -EINVAL; |
| 3604 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3605 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3606 | obj->user_pin_count--; |
| 3607 | if (obj->user_pin_count == 0) { |
| 3608 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3609 | i915_gem_object_unpin(obj); |
| 3610 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3611 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3612 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3613 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3614 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3615 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3616 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3617 | } |
| 3618 | |
| 3619 | int |
| 3620 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3621 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3622 | { |
| 3623 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3624 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3625 | int ret; |
| 3626 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3627 | ret = i915_mutex_lock_interruptible(dev); |
| 3628 | if (ret) |
| 3629 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3630 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3631 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3632 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3633 | ret = -ENOENT; |
| 3634 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3635 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3636 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3637 | /* Count all active objects as busy, even if they are currently not used |
| 3638 | * by the gpu. Users of this interface expect objects to eventually |
| 3639 | * become non-busy without any further actions, therefore emit any |
| 3640 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 3641 | */ |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3642 | ret = i915_gem_object_flush_active(obj); |
| 3643 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3644 | args->busy = obj->active; |
Chris Wilson | e9808ed | 2012-07-04 12:25:08 +0100 | [diff] [blame] | 3645 | if (obj->ring) { |
| 3646 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
| 3647 | args->busy |= intel_ring_flag(obj->ring) << 16; |
| 3648 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3649 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3650 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3651 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3652 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3653 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3654 | } |
| 3655 | |
| 3656 | int |
| 3657 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 3658 | struct drm_file *file_priv) |
| 3659 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3660 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3661 | } |
| 3662 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3663 | int |
| 3664 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 3665 | struct drm_file *file_priv) |
| 3666 | { |
| 3667 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3668 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3669 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3670 | |
| 3671 | switch (args->madv) { |
| 3672 | case I915_MADV_DONTNEED: |
| 3673 | case I915_MADV_WILLNEED: |
| 3674 | break; |
| 3675 | default: |
| 3676 | return -EINVAL; |
| 3677 | } |
| 3678 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3679 | ret = i915_mutex_lock_interruptible(dev); |
| 3680 | if (ret) |
| 3681 | return ret; |
| 3682 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3683 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3684 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3685 | ret = -ENOENT; |
| 3686 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3687 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3688 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3689 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3690 | ret = -EINVAL; |
| 3691 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3692 | } |
| 3693 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3694 | if (obj->madv != __I915_MADV_PURGED) |
| 3695 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3696 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3697 | /* if the object is no longer attached, discard its backing storage */ |
| 3698 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3699 | i915_gem_object_truncate(obj); |
| 3700 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3701 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3702 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3703 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3704 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3705 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3706 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3707 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3708 | } |
| 3709 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3710 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 3711 | const struct drm_i915_gem_object_ops *ops) |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 3712 | { |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 3713 | INIT_LIST_HEAD(&obj->mm_list); |
| 3714 | INIT_LIST_HEAD(&obj->gtt_list); |
| 3715 | INIT_LIST_HEAD(&obj->ring_list); |
| 3716 | INIT_LIST_HEAD(&obj->exec_list); |
| 3717 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3718 | obj->ops = ops; |
| 3719 | |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 3720 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 3721 | obj->madv = I915_MADV_WILLNEED; |
| 3722 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 3723 | obj->map_and_fenceable = true; |
| 3724 | |
| 3725 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 3726 | } |
| 3727 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3728 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
| 3729 | .get_pages = i915_gem_object_get_pages_gtt, |
| 3730 | .put_pages = i915_gem_object_put_pages_gtt, |
| 3731 | }; |
| 3732 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3733 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 3734 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3735 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3736 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3737 | struct address_space *mapping; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 3738 | gfp_t mask; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3739 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 3740 | obj = i915_gem_object_alloc(dev); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3741 | if (obj == NULL) |
| 3742 | return NULL; |
| 3743 | |
| 3744 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 3745 | i915_gem_object_free(obj); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3746 | return NULL; |
| 3747 | } |
| 3748 | |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 3749 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 3750 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 3751 | /* 965gm cannot relocate objects above 4GiB. */ |
| 3752 | mask &= ~__GFP_HIGHMEM; |
| 3753 | mask |= __GFP_DMA32; |
| 3754 | } |
| 3755 | |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 3756 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 3757 | mapping_set_gfp_mask(mapping, mask); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3758 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3759 | i915_gem_object_init(obj, &i915_gem_object_ops); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3760 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3761 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3762 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3763 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 3764 | if (HAS_LLC(dev)) { |
| 3765 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 3766 | * cache) for about a 10% performance improvement |
| 3767 | * compared to uncached. Graphics requests other than |
| 3768 | * display scanout are coherent with the CPU in |
| 3769 | * accessing this cache. This means in this mode we |
| 3770 | * don't need to clflush on the CPU side, and on the |
| 3771 | * GPU side we only need to flush internal caches to |
| 3772 | * get data visible to the CPU. |
| 3773 | * |
| 3774 | * However, we maintain the display planes as UC, and so |
| 3775 | * need to rebind when first used as such. |
| 3776 | */ |
| 3777 | obj->cache_level = I915_CACHE_LLC; |
| 3778 | } else |
| 3779 | obj->cache_level = I915_CACHE_NONE; |
| 3780 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3781 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3782 | } |
| 3783 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3784 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 3785 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3786 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3787 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3788 | return 0; |
| 3789 | } |
| 3790 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3791 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3792 | { |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3793 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3794 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3795 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3796 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 3797 | trace_i915_gem_object_destroy(obj); |
| 3798 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3799 | if (obj->phys_obj) |
| 3800 | i915_gem_detach_phys_object(dev, obj); |
| 3801 | |
| 3802 | obj->pin_count = 0; |
| 3803 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { |
| 3804 | bool was_interruptible; |
| 3805 | |
| 3806 | was_interruptible = dev_priv->mm.interruptible; |
| 3807 | dev_priv->mm.interruptible = false; |
| 3808 | |
| 3809 | WARN_ON(i915_gem_object_unbind(obj)); |
| 3810 | |
| 3811 | dev_priv->mm.interruptible = was_interruptible; |
| 3812 | } |
| 3813 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 3814 | obj->pages_pin_count = 0; |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3815 | i915_gem_object_put_pages(obj); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 3816 | i915_gem_object_free_mmap_offset(obj); |
Chris Wilson | 0104fdb | 2012-11-15 11:32:26 +0000 | [diff] [blame] | 3817 | i915_gem_object_release_stolen(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3818 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3819 | BUG_ON(obj->pages); |
| 3820 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 3821 | if (obj->base.import_attach) |
| 3822 | drm_prime_gem_destroy(&obj->base, NULL); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3823 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3824 | drm_gem_object_release(&obj->base); |
| 3825 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3826 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3827 | kfree(obj->bit_17); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 3828 | i915_gem_object_free(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3829 | } |
| 3830 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 3831 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3832 | i915_gem_idle(struct drm_device *dev) |
| 3833 | { |
| 3834 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3835 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3836 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3837 | mutex_lock(&dev->struct_mutex); |
| 3838 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 3839 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3840 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3841 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3842 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3843 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3844 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3845 | if (ret) { |
| 3846 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3847 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3848 | } |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3849 | i915_gem_retire_requests(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3850 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3851 | /* Under UMS, be paranoid and evict. */ |
Chris Wilson | a39d7ef | 2012-04-24 18:22:52 +0100 | [diff] [blame] | 3852 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3853 | i915_gem_evict_everything(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3854 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 3855 | i915_gem_reset_fences(dev); |
| 3856 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3857 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 3858 | * We need to replace this with a semaphore, or something. |
| 3859 | * And not confound mm.suspended! |
| 3860 | */ |
| 3861 | dev_priv->mm.suspended = 1; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 3862 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3863 | |
| 3864 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3865 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3866 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3867 | mutex_unlock(&dev->struct_mutex); |
| 3868 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3869 | /* Cancel the retire work handler, which should be idle now. */ |
| 3870 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 3871 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3872 | return 0; |
| 3873 | } |
| 3874 | |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 3875 | void i915_gem_l3_remap(struct drm_device *dev) |
| 3876 | { |
| 3877 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3878 | u32 misccpctl; |
| 3879 | int i; |
| 3880 | |
Daniel Vetter | eb32e45 | 2013-02-14 19:46:07 +0100 | [diff] [blame] | 3881 | if (!HAS_L3_GPU_CACHE(dev)) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 3882 | return; |
| 3883 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 3884 | if (!dev_priv->l3_parity.remap_info) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 3885 | return; |
| 3886 | |
| 3887 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 3888 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 3889 | POSTING_READ(GEN7_MISCCPCTL); |
| 3890 | |
| 3891 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
| 3892 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 3893 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 3894 | DRM_DEBUG("0x%x was already programmed to %x\n", |
| 3895 | GEN7_L3LOG_BASE + i, remap); |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 3896 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 3897 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 3898 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 3899 | } |
| 3900 | |
| 3901 | /* Make sure all the writes land before disabling dop clock gating */ |
| 3902 | POSTING_READ(GEN7_L3LOG_BASE); |
| 3903 | |
| 3904 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 3905 | } |
| 3906 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3907 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 3908 | { |
| 3909 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3910 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3911 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3912 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 3913 | return; |
| 3914 | |
| 3915 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 3916 | DISP_TILE_SURFACE_SWIZZLING); |
| 3917 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3918 | if (IS_GEN5(dev)) |
| 3919 | return; |
| 3920 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3921 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 3922 | if (IS_GEN6(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3923 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 3924 | else if (IS_GEN7(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3925 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 3926 | else |
| 3927 | BUG(); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3928 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3929 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 3930 | static bool |
| 3931 | intel_enable_blt(struct drm_device *dev) |
| 3932 | { |
| 3933 | if (!HAS_BLT(dev)) |
| 3934 | return false; |
| 3935 | |
| 3936 | /* The blitter was dysfunctional on early prototypes */ |
| 3937 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
| 3938 | DRM_INFO("BLT not supported on this pre-production hardware;" |
| 3939 | " graphics performance will be degraded.\n"); |
| 3940 | return false; |
| 3941 | } |
| 3942 | |
| 3943 | return true; |
| 3944 | } |
| 3945 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 3946 | static int i915_gem_init_rings(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3947 | { |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 3948 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3949 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3950 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3951 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3952 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 3953 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3954 | |
| 3955 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3956 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3957 | if (ret) |
| 3958 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3959 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3960 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 3961 | if (intel_enable_blt(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3962 | ret = intel_init_blt_ring_buffer(dev); |
| 3963 | if (ret) |
| 3964 | goto cleanup_bsd_ring; |
| 3965 | } |
| 3966 | |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 3967 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
| 3968 | if (ret) |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 3969 | goto cleanup_blt_ring; |
| 3970 | |
| 3971 | return 0; |
| 3972 | |
| 3973 | cleanup_blt_ring: |
| 3974 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
| 3975 | cleanup_bsd_ring: |
| 3976 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
| 3977 | cleanup_render_ring: |
| 3978 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
| 3979 | |
| 3980 | return ret; |
| 3981 | } |
| 3982 | |
| 3983 | int |
| 3984 | i915_gem_init_hw(struct drm_device *dev) |
| 3985 | { |
| 3986 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3987 | int ret; |
| 3988 | |
| 3989 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
| 3990 | return -EIO; |
| 3991 | |
| 3992 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) |
| 3993 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); |
| 3994 | |
| 3995 | i915_gem_l3_remap(dev); |
| 3996 | |
| 3997 | i915_gem_init_swizzling(dev); |
| 3998 | |
| 3999 | ret = i915_gem_init_rings(dev); |
| 4000 | if (ret) |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4001 | return ret; |
| 4002 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 4003 | /* |
| 4004 | * XXX: There was some w/a described somewhere suggesting loading |
| 4005 | * contexts before PPGTT. |
| 4006 | */ |
| 4007 | i915_gem_context_init(dev); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4008 | i915_gem_init_ppgtt(dev); |
| 4009 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4010 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4011 | } |
| 4012 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4013 | int i915_gem_init(struct drm_device *dev) |
| 4014 | { |
| 4015 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4016 | int ret; |
| 4017 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4018 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4019 | |
| 4020 | if (IS_VALLEYVIEW(dev)) { |
| 4021 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
| 4022 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); |
| 4023 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) |
| 4024 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
| 4025 | } |
| 4026 | |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 4027 | i915_gem_init_global_gtt(dev); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4028 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4029 | ret = i915_gem_init_hw(dev); |
| 4030 | mutex_unlock(&dev->struct_mutex); |
| 4031 | if (ret) { |
| 4032 | i915_gem_cleanup_aliasing_ppgtt(dev); |
| 4033 | return ret; |
| 4034 | } |
| 4035 | |
Daniel Vetter | 53ca26c | 2012-04-26 23:28:03 +0200 | [diff] [blame] | 4036 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
| 4037 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4038 | dev_priv->dri1.allow_batchbuffer = 1; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4039 | return 0; |
| 4040 | } |
| 4041 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4042 | void |
| 4043 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4044 | { |
| 4045 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4046 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4047 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4048 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4049 | for_each_ring(ring, dev_priv, i) |
| 4050 | intel_cleanup_ring_buffer(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4051 | } |
| 4052 | |
| 4053 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4054 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4055 | struct drm_file *file_priv) |
| 4056 | { |
| 4057 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4058 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4059 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4060 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4061 | return 0; |
| 4062 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4063 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4064 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4065 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4066 | } |
| 4067 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4068 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4069 | dev_priv->mm.suspended = 0; |
| 4070 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4071 | ret = i915_gem_init_hw(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4072 | if (ret != 0) { |
| 4073 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4074 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4075 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4076 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4077 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4078 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4079 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4080 | ret = drm_irq_install(dev); |
| 4081 | if (ret) |
| 4082 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4083 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4084 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4085 | |
| 4086 | cleanup_ringbuffer: |
| 4087 | mutex_lock(&dev->struct_mutex); |
| 4088 | i915_gem_cleanup_ringbuffer(dev); |
| 4089 | dev_priv->mm.suspended = 1; |
| 4090 | mutex_unlock(&dev->struct_mutex); |
| 4091 | |
| 4092 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4093 | } |
| 4094 | |
| 4095 | int |
| 4096 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4097 | struct drm_file *file_priv) |
| 4098 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4099 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4100 | return 0; |
| 4101 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4102 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 4103 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4104 | } |
| 4105 | |
| 4106 | void |
| 4107 | i915_gem_lastclose(struct drm_device *dev) |
| 4108 | { |
| 4109 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4110 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4111 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4112 | return; |
| 4113 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4114 | ret = i915_gem_idle(dev); |
| 4115 | if (ret) |
| 4116 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4117 | } |
| 4118 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4119 | static void |
| 4120 | init_ring_lists(struct intel_ring_buffer *ring) |
| 4121 | { |
| 4122 | INIT_LIST_HEAD(&ring->active_list); |
| 4123 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4124 | } |
| 4125 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4126 | void |
| 4127 | i915_gem_load(struct drm_device *dev) |
| 4128 | { |
| 4129 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4130 | int i; |
| 4131 | |
| 4132 | dev_priv->slab = |
| 4133 | kmem_cache_create("i915_gem_object", |
| 4134 | sizeof(struct drm_i915_gem_object), 0, |
| 4135 | SLAB_HWCACHE_ALIGN, |
| 4136 | NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4137 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4138 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4139 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4140 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 4141 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4142 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4143 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 4144 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 4145 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4146 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4147 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4148 | i915_gem_retire_work_handler); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4149 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4150 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4151 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4152 | if (IS_GEN3(dev)) { |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 4153 | I915_WRITE(MI_ARB_STATE, |
| 4154 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4155 | } |
| 4156 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 4157 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 4158 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4159 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4160 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4161 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4162 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4163 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4164 | dev_priv->num_fence_regs = 16; |
| 4165 | else |
| 4166 | dev_priv->num_fence_regs = 8; |
| 4167 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4168 | /* Initialize fence registers to zero */ |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 4169 | i915_gem_reset_fences(dev); |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 4170 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4171 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4172 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4173 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 4174 | dev_priv->mm.interruptible = true; |
| 4175 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4176 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 4177 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 4178 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4179 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4180 | |
| 4181 | /* |
| 4182 | * Create a physically contiguous memory object for this object |
| 4183 | * e.g. for cursor + overlay regs |
| 4184 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4185 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 4186 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4187 | { |
| 4188 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4189 | struct drm_i915_gem_phys_object *phys_obj; |
| 4190 | int ret; |
| 4191 | |
| 4192 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4193 | return 0; |
| 4194 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4195 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4196 | if (!phys_obj) |
| 4197 | return -ENOMEM; |
| 4198 | |
| 4199 | phys_obj->id = id; |
| 4200 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4201 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4202 | if (!phys_obj->handle) { |
| 4203 | ret = -ENOMEM; |
| 4204 | goto kfree_obj; |
| 4205 | } |
| 4206 | #ifdef CONFIG_X86 |
| 4207 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4208 | #endif |
| 4209 | |
| 4210 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4211 | |
| 4212 | return 0; |
| 4213 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4214 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4215 | return ret; |
| 4216 | } |
| 4217 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4218 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4219 | { |
| 4220 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4221 | struct drm_i915_gem_phys_object *phys_obj; |
| 4222 | |
| 4223 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4224 | return; |
| 4225 | |
| 4226 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4227 | if (phys_obj->cur_obj) { |
| 4228 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4229 | } |
| 4230 | |
| 4231 | #ifdef CONFIG_X86 |
| 4232 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4233 | #endif |
| 4234 | drm_pci_free(dev, phys_obj->handle); |
| 4235 | kfree(phys_obj); |
| 4236 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4237 | } |
| 4238 | |
| 4239 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4240 | { |
| 4241 | int i; |
| 4242 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4243 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4244 | i915_gem_free_phys_object(dev, i); |
| 4245 | } |
| 4246 | |
| 4247 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4248 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4249 | { |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4250 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4251 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4252 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4253 | int page_count; |
| 4254 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4255 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4256 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4257 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4258 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4259 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4260 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4261 | struct page *page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4262 | if (!IS_ERR(page)) { |
| 4263 | char *dst = kmap_atomic(page); |
| 4264 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 4265 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4266 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4267 | drm_clflush_pages(&page, 1); |
| 4268 | |
| 4269 | set_page_dirty(page); |
| 4270 | mark_page_accessed(page); |
| 4271 | page_cache_release(page); |
| 4272 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4273 | } |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 4274 | i915_gem_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4275 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4276 | obj->phys_obj->cur_obj = NULL; |
| 4277 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4278 | } |
| 4279 | |
| 4280 | int |
| 4281 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4282 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4283 | int id, |
| 4284 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4285 | { |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4286 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4287 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4288 | int ret = 0; |
| 4289 | int page_count; |
| 4290 | int i; |
| 4291 | |
| 4292 | if (id > I915_MAX_PHYS_OBJECT) |
| 4293 | return -EINVAL; |
| 4294 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4295 | if (obj->phys_obj) { |
| 4296 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4297 | return 0; |
| 4298 | i915_gem_detach_phys_object(dev, obj); |
| 4299 | } |
| 4300 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4301 | /* create a new object */ |
| 4302 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4303 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4304 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4305 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4306 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 4307 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4308 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4309 | } |
| 4310 | } |
| 4311 | |
| 4312 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4313 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4314 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4315 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4316 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4317 | |
| 4318 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4319 | struct page *page; |
| 4320 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4321 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4322 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4323 | if (IS_ERR(page)) |
| 4324 | return PTR_ERR(page); |
| 4325 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 4326 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4327 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4328 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4329 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4330 | |
| 4331 | mark_page_accessed(page); |
| 4332 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4333 | } |
| 4334 | |
| 4335 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4336 | } |
| 4337 | |
| 4338 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4339 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 4340 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4341 | struct drm_i915_gem_pwrite *args, |
| 4342 | struct drm_file *file_priv) |
| 4343 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4344 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 4345 | char __user *user_data = to_user_ptr(args->data_ptr); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4346 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 4347 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 4348 | unsigned long unwritten; |
| 4349 | |
| 4350 | /* The physical object once assigned is fixed for the lifetime |
| 4351 | * of the obj, so we can safely drop the lock and continue |
| 4352 | * to access vaddr. |
| 4353 | */ |
| 4354 | mutex_unlock(&dev->struct_mutex); |
| 4355 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 4356 | mutex_lock(&dev->struct_mutex); |
| 4357 | if (unwritten) |
| 4358 | return -EFAULT; |
| 4359 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4360 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 4361 | i915_gem_chipset_flush(dev); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4362 | return 0; |
| 4363 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4364 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4365 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4366 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4367 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4368 | |
| 4369 | /* Clean up our request list when the client is going away, so that |
| 4370 | * later retire_requests won't dereference our soon-to-be-gone |
| 4371 | * file_priv. |
| 4372 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4373 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4374 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4375 | struct drm_i915_gem_request *request; |
| 4376 | |
| 4377 | request = list_first_entry(&file_priv->mm.request_list, |
| 4378 | struct drm_i915_gem_request, |
| 4379 | client_list); |
| 4380 | list_del(&request->client_list); |
| 4381 | request->file_priv = NULL; |
| 4382 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4383 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4384 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4385 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4386 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
| 4387 | { |
| 4388 | if (!mutex_is_locked(mutex)) |
| 4389 | return false; |
| 4390 | |
| 4391 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) |
| 4392 | return mutex->owner == task; |
| 4393 | #else |
| 4394 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ |
| 4395 | return false; |
| 4396 | #endif |
| 4397 | } |
| 4398 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4399 | static int |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4400 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4401 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4402 | struct drm_i915_private *dev_priv = |
| 4403 | container_of(shrinker, |
| 4404 | struct drm_i915_private, |
| 4405 | mm.inactive_shrinker); |
| 4406 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4407 | struct drm_i915_gem_object *obj; |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4408 | int nr_to_scan = sc->nr_to_scan; |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4409 | bool unlock = true; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4410 | int cnt; |
| 4411 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4412 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 4413 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) |
| 4414 | return 0; |
| 4415 | |
Daniel Vetter | 677feac | 2012-12-19 14:33:45 +0100 | [diff] [blame] | 4416 | if (dev_priv->mm.shrinker_no_lock_stealing) |
| 4417 | return 0; |
| 4418 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4419 | unlock = false; |
| 4420 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4421 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4422 | if (nr_to_scan) { |
| 4423 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); |
| 4424 | if (nr_to_scan > 0) |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 4425 | nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan, |
| 4426 | false); |
| 4427 | if (nr_to_scan > 0) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4428 | i915_gem_shrink_all(dev_priv); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4429 | } |
| 4430 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4431 | cnt = 0; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4432 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 4433 | if (obj->pages_pin_count == 0) |
| 4434 | cnt += obj->base.size >> PAGE_SHIFT; |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 4435 | list_for_each_entry(obj, &dev_priv->mm.inactive_list, gtt_list) |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 4436 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4437 | cnt += obj->base.size >> PAGE_SHIFT; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4438 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4439 | if (unlock) |
| 4440 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4441 | return cnt; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4442 | } |