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Yoshinori Sato7b5bb892015-05-08 23:31:57 +09001/*
2 * H8/300 divide clock driver
3 *
4 * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
5 */
6
Yoshinori Sato7b5bb892015-05-08 23:31:57 +09007#include <linux/clk-provider.h>
8#include <linux/err.h>
9#include <linux/of.h>
10#include <linux/of_address.h>
11
12static DEFINE_SPINLOCK(clklock);
13
14static void __init h8300_div_clk_setup(struct device_node *node)
15{
Stephen Boydebf3f9a2016-02-19 17:36:51 -080016 unsigned int num_parents;
Stephen Boyd8b2bdc72016-08-16 15:37:57 -070017 struct clk_hw *hw;
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090018 const char *clk_name = node->name;
19 const char *parent_name;
20 void __iomem *divcr = NULL;
21 int width;
Yoshinori Satoaca25182015-05-31 23:25:35 +090022 int offset;
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090023
24 num_parents = of_clk_get_parent_count(node);
Stephen Boydebf3f9a2016-02-19 17:36:51 -080025 if (!num_parents) {
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090026 pr_err("%s: no parent found", clk_name);
27 return;
28 }
29
30 divcr = of_iomap(node, 0);
31 if (divcr == NULL) {
32 pr_err("%s: failed to map divide register", clk_name);
33 goto error;
34 }
Yoshinori Satoaca25182015-05-31 23:25:35 +090035 offset = (unsigned long)divcr & 3;
36 offset = (3 - offset) * 8;
Stephen Boydd3622b52016-02-22 12:36:15 -080037 divcr = (void __iomem *)((unsigned long)divcr & ~3);
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090038
39 parent_name = of_clk_get_parent_name(node, 0);
40 of_property_read_u32(node, "renesas,width", &width);
Stephen Boyd8b2bdc72016-08-16 15:37:57 -070041 hw = clk_hw_register_divider(NULL, clk_name, parent_name,
Yoshinori Satoaca25182015-05-31 23:25:35 +090042 CLK_SET_RATE_GATE, divcr, offset, width,
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090043 CLK_DIVIDER_POWER_OF_TWO, &clklock);
Stephen Boyd8b2bdc72016-08-16 15:37:57 -070044 if (!IS_ERR(hw)) {
45 of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090046 return;
47 }
48 pr_err("%s: failed to register %s div clock (%ld)\n",
Stephen Boyd8b2bdc72016-08-16 15:37:57 -070049 __func__, clk_name, PTR_ERR(hw));
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090050error:
51 if (divcr)
52 iounmap(divcr);
53}
54
55CLK_OF_DECLARE(h8300_div_clk, "renesas,h8300-div-clock", h8300_div_clk_setup);