Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mm/mmu.c |
| 3 | * |
| 4 | * Copyright (C) 1995-2005 Russell King |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 10 | #include <linux/module.h> |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/errno.h> |
| 13 | #include <linux/init.h> |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 14 | #include <linux/mman.h> |
| 15 | #include <linux/nodemask.h> |
Russell King | 2778f62 | 2010-07-09 16:27:52 +0100 | [diff] [blame] | 16 | #include <linux/memblock.h> |
Catalin Marinas | d907387 | 2010-09-13 16:01:24 +0100 | [diff] [blame] | 17 | #include <linux/fs.h> |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 18 | #include <linux/vmalloc.h> |
Alessandro Rubini | 158e8bf | 2012-06-24 12:46:26 +0100 | [diff] [blame] | 19 | #include <linux/sizes.h> |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 20 | |
Russell King | 15d07dc | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 21 | #include <asm/cp15.h> |
Russell King | 0ba8b9b | 2008-08-10 18:08:10 +0100 | [diff] [blame] | 22 | #include <asm/cputype.h> |
Russell King | 37efe64 | 2008-12-01 11:53:07 +0000 | [diff] [blame] | 23 | #include <asm/sections.h> |
Nicolas Pitre | 3f973e2 | 2008-11-04 00:48:42 -0500 | [diff] [blame] | 24 | #include <asm/cachetype.h> |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 25 | #include <asm/setup.h> |
Russell King | e616c59 | 2009-09-27 20:55:43 +0100 | [diff] [blame] | 26 | #include <asm/smp_plat.h> |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 27 | #include <asm/tlb.h> |
Nicolas Pitre | d73cd42 | 2008-09-15 16:44:55 -0400 | [diff] [blame] | 28 | #include <asm/highmem.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 29 | #include <asm/system_info.h> |
Catalin Marinas | 247055a | 2010-09-13 16:03:21 +0100 | [diff] [blame] | 30 | #include <asm/traps.h> |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 31 | |
| 32 | #include <asm/mach/arch.h> |
| 33 | #include <asm/mach/map.h> |
| 34 | |
| 35 | #include "mm.h" |
| 36 | |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 37 | /* |
| 38 | * empty_zero_page is a special page that is used for |
| 39 | * zero-initialized data and COW. |
| 40 | */ |
| 41 | struct page *empty_zero_page; |
Aneesh Kumar K.V | 3653f3a | 2008-04-29 08:11:12 -0400 | [diff] [blame] | 42 | EXPORT_SYMBOL(empty_zero_page); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 43 | |
| 44 | /* |
| 45 | * The pmd table for the upper-most set of pages. |
| 46 | */ |
| 47 | pmd_t *top_pmd; |
| 48 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 49 | #define CPOLICY_UNCACHED 0 |
| 50 | #define CPOLICY_BUFFERED 1 |
| 51 | #define CPOLICY_WRITETHROUGH 2 |
| 52 | #define CPOLICY_WRITEBACK 3 |
| 53 | #define CPOLICY_WRITEALLOC 4 |
| 54 | |
| 55 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; |
| 56 | static unsigned int ecc_mask __initdata = 0; |
Imre_Deak | 44b1869 | 2007-02-11 13:45:13 +0100 | [diff] [blame] | 57 | pgprot_t pgprot_user; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 58 | pgprot_t pgprot_kernel; |
| 59 | |
Imre_Deak | 44b1869 | 2007-02-11 13:45:13 +0100 | [diff] [blame] | 60 | EXPORT_SYMBOL(pgprot_user); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 61 | EXPORT_SYMBOL(pgprot_kernel); |
| 62 | |
| 63 | struct cachepolicy { |
| 64 | const char policy[16]; |
| 65 | unsigned int cr_mask; |
Catalin Marinas | 442e70c | 2011-09-05 17:51:56 +0100 | [diff] [blame] | 66 | pmdval_t pmd; |
Russell King | f6e3354 | 2010-11-16 00:22:09 +0000 | [diff] [blame] | 67 | pteval_t pte; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | static struct cachepolicy cache_policies[] __initdata = { |
| 71 | { |
| 72 | .policy = "uncached", |
| 73 | .cr_mask = CR_W|CR_C, |
| 74 | .pmd = PMD_SECT_UNCACHED, |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 75 | .pte = L_PTE_MT_UNCACHED, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 76 | }, { |
| 77 | .policy = "buffered", |
| 78 | .cr_mask = CR_C, |
| 79 | .pmd = PMD_SECT_BUFFERED, |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 80 | .pte = L_PTE_MT_BUFFERABLE, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 81 | }, { |
| 82 | .policy = "writethrough", |
| 83 | .cr_mask = 0, |
| 84 | .pmd = PMD_SECT_WT, |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 85 | .pte = L_PTE_MT_WRITETHROUGH, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 86 | }, { |
| 87 | .policy = "writeback", |
| 88 | .cr_mask = 0, |
| 89 | .pmd = PMD_SECT_WB, |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 90 | .pte = L_PTE_MT_WRITEBACK, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 91 | }, { |
| 92 | .policy = "writealloc", |
| 93 | .cr_mask = 0, |
| 94 | .pmd = PMD_SECT_WBWA, |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 95 | .pte = L_PTE_MT_WRITEALLOC, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 96 | } |
| 97 | }; |
| 98 | |
| 99 | /* |
Simon Arlott | 6cbdc8c | 2007-05-11 20:40:30 +0100 | [diff] [blame] | 100 | * These are useful for identifying cache coherency |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 101 | * problems by allowing the cache or the cache and |
| 102 | * writebuffer to be turned off. (Note: the write |
| 103 | * buffer should not be on and the cache off). |
| 104 | */ |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 105 | static int __init early_cachepolicy(char *p) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 106 | { |
| 107 | int i; |
| 108 | |
| 109 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { |
| 110 | int len = strlen(cache_policies[i].policy); |
| 111 | |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 112 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 113 | cachepolicy = i; |
| 114 | cr_alignment &= ~cache_policies[i].cr_mask; |
| 115 | cr_no_alignment &= ~cache_policies[i].cr_mask; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 116 | break; |
| 117 | } |
| 118 | } |
| 119 | if (i == ARRAY_SIZE(cache_policies)) |
| 120 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); |
Russell King | 4b46d64 | 2009-11-01 17:44:24 +0000 | [diff] [blame] | 121 | /* |
| 122 | * This restriction is partly to do with the way we boot; it is |
| 123 | * unpredictable to have memory mapped using two different sets of |
| 124 | * memory attributes (shared, type, and cache attribs). We can not |
| 125 | * change these attributes once the initial assembly has setup the |
| 126 | * page tables. |
| 127 | */ |
Catalin Marinas | 11179d8 | 2007-07-20 11:42:24 +0100 | [diff] [blame] | 128 | if (cpu_architecture() >= CPU_ARCH_ARMv6) { |
| 129 | printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); |
| 130 | cachepolicy = CPOLICY_WRITEBACK; |
| 131 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 132 | flush_cache_all(); |
| 133 | set_cr(cr_alignment); |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 134 | return 0; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 135 | } |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 136 | early_param("cachepolicy", early_cachepolicy); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 137 | |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 138 | static int __init early_nocache(char *__unused) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 139 | { |
| 140 | char *p = "buffered"; |
| 141 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 142 | early_cachepolicy(p); |
| 143 | return 0; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 144 | } |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 145 | early_param("nocache", early_nocache); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 146 | |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 147 | static int __init early_nowrite(char *__unused) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 148 | { |
| 149 | char *p = "uncached"; |
| 150 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 151 | early_cachepolicy(p); |
| 152 | return 0; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 153 | } |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 154 | early_param("nowb", early_nowrite); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 155 | |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 156 | #ifndef CONFIG_ARM_LPAE |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 157 | static int __init early_ecc(char *p) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 158 | { |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 159 | if (memcmp(p, "on", 2) == 0) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 160 | ecc_mask = PMD_PROTECTION; |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 161 | else if (memcmp(p, "off", 3) == 0) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 162 | ecc_mask = 0; |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 163 | return 0; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 164 | } |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 165 | early_param("ecc", early_ecc); |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 166 | #endif |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 167 | |
| 168 | static int __init noalign_setup(char *__unused) |
| 169 | { |
| 170 | cr_alignment &= ~CR_A; |
| 171 | cr_no_alignment &= ~CR_A; |
| 172 | set_cr(cr_alignment); |
| 173 | return 1; |
| 174 | } |
| 175 | __setup("noalign", noalign_setup); |
| 176 | |
Russell King | 255d1f8 | 2006-12-18 00:12:47 +0000 | [diff] [blame] | 177 | #ifndef CONFIG_SMP |
| 178 | void adjust_cr(unsigned long mask, unsigned long set) |
| 179 | { |
| 180 | unsigned long flags; |
| 181 | |
| 182 | mask &= ~CR_A; |
| 183 | |
| 184 | set &= mask; |
| 185 | |
| 186 | local_irq_save(flags); |
| 187 | |
| 188 | cr_no_alignment = (cr_no_alignment & ~mask) | set; |
| 189 | cr_alignment = (cr_alignment & ~mask) | set; |
| 190 | |
| 191 | set_cr((get_cr() & ~mask) | set); |
| 192 | |
| 193 | local_irq_restore(flags); |
| 194 | } |
| 195 | #endif |
| 196 | |
Russell King | 36bb94b | 2010-11-16 08:40:36 +0000 | [diff] [blame] | 197 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 198 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 199 | |
Russell King | b29e9f5 | 2007-04-21 10:47:29 +0100 | [diff] [blame] | 200 | static struct mem_type mem_types[] = { |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 201 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 202 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
| 203 | L_PTE_SHARED, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 204 | .prot_l1 = PMD_TYPE_TABLE, |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 205 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 206 | .domain = DOMAIN_IO, |
| 207 | }, |
| 208 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 209 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 210 | .prot_l1 = PMD_TYPE_TABLE, |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 211 | .prot_sect = PROT_SECT_DEVICE, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 212 | .domain = DOMAIN_IO, |
| 213 | }, |
| 214 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 215 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 216 | .prot_l1 = PMD_TYPE_TABLE, |
| 217 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, |
| 218 | .domain = DOMAIN_IO, |
| 219 | }, |
Lennert Buytenhek | 1ad77a8 | 2008-09-05 13:17:11 +0100 | [diff] [blame] | 220 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 221 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 222 | .prot_l1 = PMD_TYPE_TABLE, |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 223 | .prot_sect = PROT_SECT_DEVICE, |
Russell King | 0af92be | 2007-05-05 20:28:16 +0100 | [diff] [blame] | 224 | .domain = DOMAIN_IO, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 225 | }, |
Russell King | ebb4c65 | 2008-11-09 11:18:36 +0000 | [diff] [blame] | 226 | [MT_UNCACHED] = { |
| 227 | .prot_pte = PROT_PTE_DEVICE, |
| 228 | .prot_l1 = PMD_TYPE_TABLE, |
| 229 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
| 230 | .domain = DOMAIN_IO, |
| 231 | }, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 232 | [MT_CACHECLEAN] = { |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 233 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 234 | .domain = DOMAIN_KERNEL, |
| 235 | }, |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 236 | #ifndef CONFIG_ARM_LPAE |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 237 | [MT_MINICLEAN] = { |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 238 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 239 | .domain = DOMAIN_KERNEL, |
| 240 | }, |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 241 | #endif |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 242 | [MT_LOW_VECTORS] = { |
| 243 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
Russell King | 36bb94b | 2010-11-16 08:40:36 +0000 | [diff] [blame] | 244 | L_PTE_RDONLY, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 245 | .prot_l1 = PMD_TYPE_TABLE, |
| 246 | .domain = DOMAIN_USER, |
| 247 | }, |
| 248 | [MT_HIGH_VECTORS] = { |
| 249 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
Russell King | 36bb94b | 2010-11-16 08:40:36 +0000 | [diff] [blame] | 250 | L_PTE_USER | L_PTE_RDONLY, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 251 | .prot_l1 = PMD_TYPE_TABLE, |
| 252 | .domain = DOMAIN_USER, |
| 253 | }, |
| 254 | [MT_MEMORY] = { |
Russell King | 36bb94b | 2010-11-16 08:40:36 +0000 | [diff] [blame] | 255 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
Santosh Shilimkar | f1a2481 | 2010-09-24 07:18:22 +0100 | [diff] [blame] | 256 | .prot_l1 = PMD_TYPE_TABLE, |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 257 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 258 | .domain = DOMAIN_KERNEL, |
| 259 | }, |
| 260 | [MT_ROM] = { |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 261 | .prot_sect = PMD_TYPE_SECT, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 262 | .domain = DOMAIN_KERNEL, |
| 263 | }, |
Paul Walmsley | e4707dd | 2009-03-12 20:11:43 +0100 | [diff] [blame] | 264 | [MT_MEMORY_NONCACHED] = { |
Santosh Shilimkar | f1a2481 | 2010-09-24 07:18:22 +0100 | [diff] [blame] | 265 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
Russell King | 36bb94b | 2010-11-16 08:40:36 +0000 | [diff] [blame] | 266 | L_PTE_MT_BUFFERABLE, |
Santosh Shilimkar | f1a2481 | 2010-09-24 07:18:22 +0100 | [diff] [blame] | 267 | .prot_l1 = PMD_TYPE_TABLE, |
Paul Walmsley | e4707dd | 2009-03-12 20:11:43 +0100 | [diff] [blame] | 268 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
| 269 | .domain = DOMAIN_KERNEL, |
| 270 | }, |
Linus Walleij | cb9d770 | 2010-07-12 21:50:59 +0100 | [diff] [blame] | 271 | [MT_MEMORY_DTCM] = { |
Linus Walleij | f444fce | 2010-10-18 09:03:03 +0100 | [diff] [blame] | 272 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
Russell King | 36bb94b | 2010-11-16 08:40:36 +0000 | [diff] [blame] | 273 | L_PTE_XN, |
Linus Walleij | f444fce | 2010-10-18 09:03:03 +0100 | [diff] [blame] | 274 | .prot_l1 = PMD_TYPE_TABLE, |
| 275 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
| 276 | .domain = DOMAIN_KERNEL, |
Linus Walleij | cb9d770 | 2010-07-12 21:50:59 +0100 | [diff] [blame] | 277 | }, |
| 278 | [MT_MEMORY_ITCM] = { |
Russell King | 36bb94b | 2010-11-16 08:40:36 +0000 | [diff] [blame] | 279 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
Linus Walleij | cb9d770 | 2010-07-12 21:50:59 +0100 | [diff] [blame] | 280 | .prot_l1 = PMD_TYPE_TABLE, |
Linus Walleij | f444fce | 2010-10-18 09:03:03 +0100 | [diff] [blame] | 281 | .domain = DOMAIN_KERNEL, |
Linus Walleij | cb9d770 | 2010-07-12 21:50:59 +0100 | [diff] [blame] | 282 | }, |
Santosh Shilimkar | 8fb5428 | 2011-06-28 12:42:56 -0700 | [diff] [blame] | 283 | [MT_MEMORY_SO] = { |
| 284 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
| 285 | L_PTE_MT_UNCACHED, |
| 286 | .prot_l1 = PMD_TYPE_TABLE, |
| 287 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | |
| 288 | PMD_SECT_UNCACHED | PMD_SECT_XN, |
| 289 | .domain = DOMAIN_KERNEL, |
| 290 | }, |
Marek Szyprowski | c790950 | 2011-12-29 13:09:51 +0100 | [diff] [blame] | 291 | [MT_MEMORY_DMA_READY] = { |
| 292 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
| 293 | .prot_l1 = PMD_TYPE_TABLE, |
| 294 | .domain = DOMAIN_KERNEL, |
| 295 | }, |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 296 | }; |
| 297 | |
Russell King | b29e9f5 | 2007-04-21 10:47:29 +0100 | [diff] [blame] | 298 | const struct mem_type *get_mem_type(unsigned int type) |
| 299 | { |
| 300 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; |
| 301 | } |
Hiroshi DOYU | 69d3a84 | 2009-01-28 21:32:08 +0200 | [diff] [blame] | 302 | EXPORT_SYMBOL(get_mem_type); |
Russell King | b29e9f5 | 2007-04-21 10:47:29 +0100 | [diff] [blame] | 303 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 304 | /* |
| 305 | * Adjust the PMD section entries according to the CPU in use. |
| 306 | */ |
| 307 | static void __init build_mem_type_table(void) |
| 308 | { |
| 309 | struct cachepolicy *cp; |
| 310 | unsigned int cr = get_cr(); |
Catalin Marinas | 442e70c | 2011-09-05 17:51:56 +0100 | [diff] [blame] | 311 | pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 312 | int cpu_arch = cpu_architecture(); |
| 313 | int i; |
| 314 | |
Catalin Marinas | 11179d8 | 2007-07-20 11:42:24 +0100 | [diff] [blame] | 315 | if (cpu_arch < CPU_ARCH_ARMv6) { |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 316 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
Catalin Marinas | 11179d8 | 2007-07-20 11:42:24 +0100 | [diff] [blame] | 317 | if (cachepolicy > CPOLICY_BUFFERED) |
| 318 | cachepolicy = CPOLICY_BUFFERED; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 319 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
Catalin Marinas | 11179d8 | 2007-07-20 11:42:24 +0100 | [diff] [blame] | 320 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
| 321 | cachepolicy = CPOLICY_WRITETHROUGH; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 322 | #endif |
Catalin Marinas | 11179d8 | 2007-07-20 11:42:24 +0100 | [diff] [blame] | 323 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 324 | if (cpu_arch < CPU_ARCH_ARMv5) { |
| 325 | if (cachepolicy >= CPOLICY_WRITEALLOC) |
| 326 | cachepolicy = CPOLICY_WRITEBACK; |
| 327 | ecc_mask = 0; |
| 328 | } |
Russell King | f00ec48 | 2010-09-04 10:47:48 +0100 | [diff] [blame] | 329 | if (is_smp()) |
| 330 | cachepolicy = CPOLICY_WRITEALLOC; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 331 | |
| 332 | /* |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 333 | * Strip out features not present on earlier architectures. |
| 334 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those |
| 335 | * without extended page tables don't have the 'Shared' bit. |
Lennert Buytenhek | 1ad77a8 | 2008-09-05 13:17:11 +0100 | [diff] [blame] | 336 | */ |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 337 | if (cpu_arch < CPU_ARCH_ARMv5) |
| 338 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) |
| 339 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); |
| 340 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) |
| 341 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) |
| 342 | mem_types[i].prot_sect &= ~PMD_SECT_S; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 343 | |
| 344 | /* |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 345 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
| 346 | * "update-able on write" bit on ARM610). However, Xscale and |
| 347 | * Xscale3 require this bit to be cleared. |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 348 | */ |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 349 | if (cpu_is_xscale() || cpu_is_xsc3()) { |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 350 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 351 | mem_types[i].prot_sect &= ~PMD_BIT4; |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 352 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
| 353 | } |
| 354 | } else if (cpu_arch < CPU_ARCH_ARMv6) { |
| 355 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 356 | if (mem_types[i].prot_l1) |
| 357 | mem_types[i].prot_l1 |= PMD_BIT4; |
Russell King | 9ef7963 | 2007-05-05 20:03:35 +0100 | [diff] [blame] | 358 | if (mem_types[i].prot_sect) |
| 359 | mem_types[i].prot_sect |= PMD_BIT4; |
| 360 | } |
| 361 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 362 | |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 363 | /* |
| 364 | * Mark the device areas according to the CPU/architecture. |
| 365 | */ |
| 366 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { |
| 367 | if (!cpu_is_xsc3()) { |
| 368 | /* |
| 369 | * Mark device regions on ARMv6+ as execute-never |
| 370 | * to prevent speculative instruction fetches. |
| 371 | */ |
| 372 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; |
| 373 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; |
| 374 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; |
| 375 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; |
| 376 | } |
| 377 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { |
| 378 | /* |
| 379 | * For ARMv7 with TEX remapping, |
| 380 | * - shared device is SXCB=1100 |
| 381 | * - nonshared device is SXCB=0100 |
| 382 | * - write combine device mem is SXCB=0001 |
| 383 | * (Uncached Normal memory) |
| 384 | */ |
| 385 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); |
| 386 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); |
| 387 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; |
| 388 | } else if (cpu_is_xsc3()) { |
| 389 | /* |
| 390 | * For Xscale3, |
| 391 | * - shared device is TEXCB=00101 |
| 392 | * - nonshared device is TEXCB=01000 |
| 393 | * - write combine device mem is TEXCB=00100 |
| 394 | * (Inner/Outer Uncacheable in xsc3 parlance) |
| 395 | */ |
| 396 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; |
| 397 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); |
| 398 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); |
| 399 | } else { |
| 400 | /* |
| 401 | * For ARMv6 and ARMv7 without TEX remapping, |
| 402 | * - shared device is TEXCB=00001 |
| 403 | * - nonshared device is TEXCB=01000 |
| 404 | * - write combine device mem is TEXCB=00100 |
| 405 | * (Uncached Normal in ARMv6 parlance). |
| 406 | */ |
| 407 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; |
| 408 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); |
| 409 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); |
| 410 | } |
| 411 | } else { |
| 412 | /* |
| 413 | * On others, write combining is "Uncached/Buffered" |
| 414 | */ |
| 415 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; |
| 416 | } |
| 417 | |
| 418 | /* |
| 419 | * Now deal with the memory-type mappings |
| 420 | */ |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 421 | cp = &cache_policies[cachepolicy]; |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 422 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
| 423 | |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 424 | /* |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 425 | * Enable CPU-specific coherency if supported. |
| 426 | * (Only available on XSC3 at the moment.) |
| 427 | */ |
Santosh Shilimkar | f1a2481 | 2010-09-24 07:18:22 +0100 | [diff] [blame] | 428 | if (arch_is_coherent() && cpu_is_xsc3()) { |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 429 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
Santosh Shilimkar | f1a2481 | 2010-09-24 07:18:22 +0100 | [diff] [blame] | 430 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; |
Marek Szyprowski | c790950 | 2011-12-29 13:09:51 +0100 | [diff] [blame] | 431 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
Santosh Shilimkar | f1a2481 | 2010-09-24 07:18:22 +0100 | [diff] [blame] | 432 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; |
| 433 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; |
| 434 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 435 | /* |
| 436 | * ARMv6 and above have extended page tables. |
| 437 | */ |
| 438 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 439 | #ifndef CONFIG_ARM_LPAE |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 440 | /* |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 441 | * Mark cache clean areas and XIP ROM read only |
| 442 | * from SVC mode and no access from userspace. |
| 443 | */ |
| 444 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
| 445 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
| 446 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 447 | #endif |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 448 | |
Russell King | f00ec48 | 2010-09-04 10:47:48 +0100 | [diff] [blame] | 449 | if (is_smp()) { |
| 450 | /* |
| 451 | * Mark memory with the "shared" attribute |
| 452 | * for SMP systems |
| 453 | */ |
| 454 | user_pgprot |= L_PTE_SHARED; |
| 455 | kern_pgprot |= L_PTE_SHARED; |
| 456 | vecs_pgprot |= L_PTE_SHARED; |
| 457 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; |
| 458 | mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; |
| 459 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; |
| 460 | mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; |
| 461 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
| 462 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; |
Marek Szyprowski | c790950 | 2011-12-29 13:09:51 +0100 | [diff] [blame] | 463 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
Russell King | f00ec48 | 2010-09-04 10:47:48 +0100 | [diff] [blame] | 464 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; |
| 465 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; |
| 466 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 467 | } |
| 468 | |
Paul Walmsley | e4707dd | 2009-03-12 20:11:43 +0100 | [diff] [blame] | 469 | /* |
| 470 | * Non-cacheable Normal - intended for memory areas that must |
| 471 | * not cause dirty cache line writebacks when used |
| 472 | */ |
| 473 | if (cpu_arch >= CPU_ARCH_ARMv6) { |
| 474 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { |
| 475 | /* Non-cacheable Normal is XCB = 001 */ |
| 476 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= |
| 477 | PMD_SECT_BUFFERED; |
| 478 | } else { |
| 479 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ |
| 480 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= |
| 481 | PMD_SECT_TEX(1); |
| 482 | } |
| 483 | } else { |
| 484 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; |
| 485 | } |
| 486 | |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 487 | #ifdef CONFIG_ARM_LPAE |
| 488 | /* |
| 489 | * Do not generate access flag faults for the kernel mappings. |
| 490 | */ |
| 491 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
| 492 | mem_types[i].prot_pte |= PTE_EXT_AF; |
Vitaly Andrianov | 1a3abcf | 2012-05-15 15:01:16 +0100 | [diff] [blame] | 493 | if (mem_types[i].prot_sect) |
| 494 | mem_types[i].prot_sect |= PMD_SECT_AF; |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 495 | } |
| 496 | kern_pgprot |= PTE_EXT_AF; |
| 497 | vecs_pgprot |= PTE_EXT_AF; |
| 498 | #endif |
| 499 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 500 | for (i = 0; i < 16; i++) { |
| 501 | unsigned long v = pgprot_val(protection_map[i]); |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 502 | protection_map[i] = __pgprot(v | user_pgprot); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 503 | } |
| 504 | |
Russell King | bb30f36 | 2008-09-06 20:04:59 +0100 | [diff] [blame] | 505 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
| 506 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 507 | |
Imre_Deak | 44b1869 | 2007-02-11 13:45:13 +0100 | [diff] [blame] | 508 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 509 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
Russell King | 36bb94b | 2010-11-16 08:40:36 +0000 | [diff] [blame] | 510 | L_PTE_DIRTY | kern_pgprot); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 511 | |
| 512 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; |
| 513 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; |
| 514 | mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; |
Santosh Shilimkar | f1a2481 | 2010-09-24 07:18:22 +0100 | [diff] [blame] | 515 | mem_types[MT_MEMORY].prot_pte |= kern_pgprot; |
Marek Szyprowski | c790950 | 2011-12-29 13:09:51 +0100 | [diff] [blame] | 516 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; |
Santosh Shilimkar | f1a2481 | 2010-09-24 07:18:22 +0100 | [diff] [blame] | 517 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 518 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
| 519 | |
| 520 | switch (cp->pmd) { |
| 521 | case PMD_SECT_WT: |
| 522 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; |
| 523 | break; |
| 524 | case PMD_SECT_WB: |
| 525 | case PMD_SECT_WBWA: |
| 526 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; |
| 527 | break; |
| 528 | } |
| 529 | printk("Memory policy: ECC %sabled, Data cache %s\n", |
| 530 | ecc_mask ? "en" : "dis", cp->policy); |
Russell King | 2497f0a | 2007-04-21 09:59:44 +0100 | [diff] [blame] | 531 | |
| 532 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
| 533 | struct mem_type *t = &mem_types[i]; |
| 534 | if (t->prot_l1) |
| 535 | t->prot_l1 |= PMD_DOMAIN(t->domain); |
| 536 | if (t->prot_sect) |
| 537 | t->prot_sect |= PMD_DOMAIN(t->domain); |
| 538 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 539 | } |
| 540 | |
Catalin Marinas | d907387 | 2010-09-13 16:01:24 +0100 | [diff] [blame] | 541 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
| 542 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, |
| 543 | unsigned long size, pgprot_t vma_prot) |
| 544 | { |
| 545 | if (!pfn_valid(pfn)) |
| 546 | return pgprot_noncached(vma_prot); |
| 547 | else if (file->f_flags & O_SYNC) |
| 548 | return pgprot_writecombine(vma_prot); |
| 549 | return vma_prot; |
| 550 | } |
| 551 | EXPORT_SYMBOL(phys_mem_access_prot); |
| 552 | #endif |
| 553 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 554 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
| 555 | |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 556 | static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) |
Russell King | 3abe9d3 | 2010-03-25 17:02:59 +0000 | [diff] [blame] | 557 | { |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 558 | void *ptr = __va(memblock_alloc(sz, align)); |
Russell King | 2778f62 | 2010-07-09 16:27:52 +0100 | [diff] [blame] | 559 | memset(ptr, 0, sz); |
| 560 | return ptr; |
Russell King | 3abe9d3 | 2010-03-25 17:02:59 +0000 | [diff] [blame] | 561 | } |
| 562 | |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 563 | static void __init *early_alloc(unsigned long sz) |
| 564 | { |
| 565 | return early_alloc_aligned(sz, sz); |
| 566 | } |
| 567 | |
Russell King | 4bb2e27 | 2010-07-01 18:33:29 +0100 | [diff] [blame] | 568 | static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) |
| 569 | { |
| 570 | if (pmd_none(*pmd)) { |
Catalin Marinas | 410f148 | 2011-02-14 12:58:04 +0100 | [diff] [blame] | 571 | pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); |
Russell King | 97092e0 | 2010-11-16 00:16:01 +0000 | [diff] [blame] | 572 | __pmd_populate(pmd, __pa(pte), prot); |
Russell King | 4bb2e27 | 2010-07-01 18:33:29 +0100 | [diff] [blame] | 573 | } |
| 574 | BUG_ON(pmd_bad(*pmd)); |
| 575 | return pte_offset_kernel(pmd, addr); |
| 576 | } |
| 577 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 578 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
| 579 | unsigned long end, unsigned long pfn, |
| 580 | const struct mem_type *type) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 581 | { |
Russell King | 4bb2e27 | 2010-07-01 18:33:29 +0100 | [diff] [blame] | 582 | pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 583 | do { |
Russell King | 40d192b | 2008-09-06 21:15:56 +0100 | [diff] [blame] | 584 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 585 | pfn++; |
| 586 | } while (pte++, addr += PAGE_SIZE, addr != end); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 587 | } |
| 588 | |
Russell King | 516295e | 2010-11-21 16:27:49 +0000 | [diff] [blame] | 589 | static void __init alloc_init_section(pud_t *pud, unsigned long addr, |
Russell King | 97092e0 | 2010-11-16 00:16:01 +0000 | [diff] [blame] | 590 | unsigned long end, phys_addr_t phys, |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 591 | const struct mem_type *type) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 592 | { |
Russell King | 516295e | 2010-11-21 16:27:49 +0000 | [diff] [blame] | 593 | pmd_t *pmd = pmd_offset(pud, addr); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 594 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 595 | /* |
| 596 | * Try a section mapping - end, addr and phys must all be aligned |
| 597 | * to a section boundary. Note that PMDs refer to the individual |
| 598 | * L1 entries, whereas PGDs refer to a group of L1 entries making |
| 599 | * up one logical pointer to an L2 table. |
| 600 | */ |
Marek Szyprowski | c790950 | 2011-12-29 13:09:51 +0100 | [diff] [blame] | 601 | if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) { |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 602 | pmd_t *p = pmd; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 603 | |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 604 | #ifndef CONFIG_ARM_LPAE |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 605 | if (addr & SECTION_SIZE) |
| 606 | pmd++; |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 607 | #endif |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 608 | |
| 609 | do { |
| 610 | *pmd = __pmd(phys | type->prot_sect); |
| 611 | phys += SECTION_SIZE; |
| 612 | } while (pmd++, addr += SECTION_SIZE, addr != end); |
| 613 | |
| 614 | flush_pmd_entry(p); |
| 615 | } else { |
| 616 | /* |
| 617 | * No need to loop; pte's aren't interested in the |
| 618 | * individual L1 entries. |
| 619 | */ |
| 620 | alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 621 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 622 | } |
| 623 | |
Stephen Boyd | 1490492 | 2012-04-27 01:40:10 +0100 | [diff] [blame] | 624 | static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, |
| 625 | unsigned long end, unsigned long phys, const struct mem_type *type) |
Russell King | 516295e | 2010-11-21 16:27:49 +0000 | [diff] [blame] | 626 | { |
| 627 | pud_t *pud = pud_offset(pgd, addr); |
| 628 | unsigned long next; |
| 629 | |
| 630 | do { |
| 631 | next = pud_addr_end(addr, end); |
| 632 | alloc_init_section(pud, addr, next, phys, type); |
| 633 | phys += next - addr; |
| 634 | } while (pud++, addr = next, addr != end); |
| 635 | } |
| 636 | |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 637 | #ifndef CONFIG_ARM_LPAE |
Russell King | 4a56c1e | 2007-04-21 10:16:48 +0100 | [diff] [blame] | 638 | static void __init create_36bit_mapping(struct map_desc *md, |
| 639 | const struct mem_type *type) |
| 640 | { |
Russell King | 97092e0 | 2010-11-16 00:16:01 +0000 | [diff] [blame] | 641 | unsigned long addr, length, end; |
| 642 | phys_addr_t phys; |
Russell King | 4a56c1e | 2007-04-21 10:16:48 +0100 | [diff] [blame] | 643 | pgd_t *pgd; |
| 644 | |
| 645 | addr = md->virtual; |
Will Deacon | cae6292 | 2011-02-15 12:42:57 +0100 | [diff] [blame] | 646 | phys = __pfn_to_phys(md->pfn); |
Russell King | 4a56c1e | 2007-04-21 10:16:48 +0100 | [diff] [blame] | 647 | length = PAGE_ALIGN(md->length); |
| 648 | |
| 649 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { |
| 650 | printk(KERN_ERR "MM: CPU does not support supersection " |
| 651 | "mapping for 0x%08llx at 0x%08lx\n", |
Will Deacon | 29a3819 | 2011-02-15 14:31:37 +0100 | [diff] [blame] | 652 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
Russell King | 4a56c1e | 2007-04-21 10:16:48 +0100 | [diff] [blame] | 653 | return; |
| 654 | } |
| 655 | |
| 656 | /* N.B. ARMv6 supersections are only defined to work with domain 0. |
| 657 | * Since domain assignments can in fact be arbitrary, the |
| 658 | * 'domain == 0' check below is required to insure that ARMv6 |
| 659 | * supersections are only allocated for domain 0 regardless |
| 660 | * of the actual domain assignments in use. |
| 661 | */ |
| 662 | if (type->domain) { |
| 663 | printk(KERN_ERR "MM: invalid domain in supersection " |
| 664 | "mapping for 0x%08llx at 0x%08lx\n", |
Will Deacon | 29a3819 | 2011-02-15 14:31:37 +0100 | [diff] [blame] | 665 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
Russell King | 4a56c1e | 2007-04-21 10:16:48 +0100 | [diff] [blame] | 666 | return; |
| 667 | } |
| 668 | |
| 669 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { |
Will Deacon | 29a3819 | 2011-02-15 14:31:37 +0100 | [diff] [blame] | 670 | printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" |
| 671 | " at 0x%08lx invalid alignment\n", |
| 672 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
Russell King | 4a56c1e | 2007-04-21 10:16:48 +0100 | [diff] [blame] | 673 | return; |
| 674 | } |
| 675 | |
| 676 | /* |
| 677 | * Shift bits [35:32] of address into bits [23:20] of PMD |
| 678 | * (See ARMv6 spec). |
| 679 | */ |
| 680 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); |
| 681 | |
| 682 | pgd = pgd_offset_k(addr); |
| 683 | end = addr + length; |
| 684 | do { |
Russell King | 516295e | 2010-11-21 16:27:49 +0000 | [diff] [blame] | 685 | pud_t *pud = pud_offset(pgd, addr); |
| 686 | pmd_t *pmd = pmd_offset(pud, addr); |
Russell King | 4a56c1e | 2007-04-21 10:16:48 +0100 | [diff] [blame] | 687 | int i; |
| 688 | |
| 689 | for (i = 0; i < 16; i++) |
| 690 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); |
| 691 | |
| 692 | addr += SUPERSECTION_SIZE; |
| 693 | phys += SUPERSECTION_SIZE; |
| 694 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; |
| 695 | } while (addr != end); |
| 696 | } |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 697 | #endif /* !CONFIG_ARM_LPAE */ |
Russell King | 4a56c1e | 2007-04-21 10:16:48 +0100 | [diff] [blame] | 698 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 699 | /* |
| 700 | * Create the page directory entries and any necessary |
| 701 | * page tables for the mapping specified by `md'. We |
| 702 | * are able to cope here with varying sizes and address |
| 703 | * offsets, and we take full advantage of sections and |
| 704 | * supersections. |
| 705 | */ |
Russell King | a222712 | 2010-03-25 18:56:05 +0000 | [diff] [blame] | 706 | static void __init create_mapping(struct map_desc *md) |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 707 | { |
Will Deacon | cae6292 | 2011-02-15 12:42:57 +0100 | [diff] [blame] | 708 | unsigned long addr, length, end; |
| 709 | phys_addr_t phys; |
Russell King | d5c9817 | 2007-04-21 10:05:32 +0100 | [diff] [blame] | 710 | const struct mem_type *type; |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 711 | pgd_t *pgd; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 712 | |
| 713 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { |
Will Deacon | 29a3819 | 2011-02-15 14:31:37 +0100 | [diff] [blame] | 714 | printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" |
| 715 | " at 0x%08lx in user region\n", |
| 716 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 717 | return; |
| 718 | } |
| 719 | |
| 720 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 721 | md->virtual >= PAGE_OFFSET && |
| 722 | (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { |
Will Deacon | 29a3819 | 2011-02-15 14:31:37 +0100 | [diff] [blame] | 723 | printk(KERN_WARNING "BUG: mapping for 0x%08llx" |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 724 | " at 0x%08lx out of vmalloc space\n", |
Will Deacon | 29a3819 | 2011-02-15 14:31:37 +0100 | [diff] [blame] | 725 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 726 | } |
| 727 | |
Russell King | d5c9817 | 2007-04-21 10:05:32 +0100 | [diff] [blame] | 728 | type = &mem_types[md->type]; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 729 | |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 730 | #ifndef CONFIG_ARM_LPAE |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 731 | /* |
| 732 | * Catch 36-bit addresses |
| 733 | */ |
Russell King | 4a56c1e | 2007-04-21 10:16:48 +0100 | [diff] [blame] | 734 | if (md->pfn >= 0x100000) { |
| 735 | create_36bit_mapping(md, type); |
| 736 | return; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 737 | } |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 738 | #endif |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 739 | |
Russell King | 7b9c7b4 | 2007-07-04 21:16:33 +0100 | [diff] [blame] | 740 | addr = md->virtual & PAGE_MASK; |
Will Deacon | cae6292 | 2011-02-15 12:42:57 +0100 | [diff] [blame] | 741 | phys = __pfn_to_phys(md->pfn); |
Russell King | 7b9c7b4 | 2007-07-04 21:16:33 +0100 | [diff] [blame] | 742 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 743 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 744 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
Will Deacon | 29a3819 | 2011-02-15 14:31:37 +0100 | [diff] [blame] | 745 | printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 746 | "be mapped using pages, ignoring.\n", |
Will Deacon | 29a3819 | 2011-02-15 14:31:37 +0100 | [diff] [blame] | 747 | (long long)__pfn_to_phys(md->pfn), addr); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 748 | return; |
| 749 | } |
| 750 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 751 | pgd = pgd_offset_k(addr); |
| 752 | end = addr + length; |
| 753 | do { |
| 754 | unsigned long next = pgd_addr_end(addr, end); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 755 | |
Russell King | 516295e | 2010-11-21 16:27:49 +0000 | [diff] [blame] | 756 | alloc_init_pud(pgd, addr, next, phys, type); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 757 | |
Russell King | 24e6c69 | 2007-04-21 10:21:28 +0100 | [diff] [blame] | 758 | phys += next - addr; |
| 759 | addr = next; |
| 760 | } while (pgd++, addr != end); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 761 | } |
| 762 | |
| 763 | /* |
| 764 | * Create the architecture specific mappings |
| 765 | */ |
| 766 | void __init iotable_init(struct map_desc *io_desc, int nr) |
| 767 | { |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 768 | struct map_desc *md; |
| 769 | struct vm_struct *vm; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 770 | |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 771 | if (!nr) |
| 772 | return; |
| 773 | |
| 774 | vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm)); |
| 775 | |
| 776 | for (md = io_desc; nr; md++, nr--) { |
| 777 | create_mapping(md); |
| 778 | vm->addr = (void *)(md->virtual & PAGE_MASK); |
| 779 | vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
| 780 | vm->phys_addr = __pfn_to_phys(md->pfn); |
Nicolas Pitre | 576d2f2 | 2011-09-16 01:14:23 -0400 | [diff] [blame] | 781 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; |
| 782 | vm->flags |= VM_ARM_MTYPE(md->type); |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 783 | vm->caller = iotable_init; |
| 784 | vm_area_add_early(vm++); |
| 785 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 786 | } |
| 787 | |
Nicolas Pitre | 19b52ab | 2012-06-27 17:28:57 +0100 | [diff] [blame] | 788 | #ifndef CONFIG_ARM_LPAE |
| 789 | |
| 790 | /* |
| 791 | * The Linux PMD is made of two consecutive section entries covering 2MB |
| 792 | * (see definition in include/asm/pgtable-2level.h). However a call to |
| 793 | * create_mapping() may optimize static mappings by using individual |
| 794 | * 1MB section mappings. This leaves the actual PMD potentially half |
| 795 | * initialized if the top or bottom section entry isn't used, leaving it |
| 796 | * open to problems if a subsequent ioremap() or vmalloc() tries to use |
| 797 | * the virtual space left free by that unused section entry. |
| 798 | * |
| 799 | * Let's avoid the issue by inserting dummy vm entries covering the unused |
| 800 | * PMD halves once the static mappings are in place. |
| 801 | */ |
| 802 | |
| 803 | static void __init pmd_empty_section_gap(unsigned long addr) |
| 804 | { |
| 805 | struct vm_struct *vm; |
| 806 | |
| 807 | vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm)); |
| 808 | vm->addr = (void *)addr; |
| 809 | vm->size = SECTION_SIZE; |
Russell King | a849088 | 2012-08-25 09:03:15 +0100 | [diff] [blame] | 810 | vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; |
Nicolas Pitre | 19b52ab | 2012-06-27 17:28:57 +0100 | [diff] [blame] | 811 | vm->caller = pmd_empty_section_gap; |
| 812 | vm_area_add_early(vm); |
| 813 | } |
| 814 | |
| 815 | static void __init fill_pmd_gaps(void) |
| 816 | { |
| 817 | struct vm_struct *vm; |
| 818 | unsigned long addr, next = 0; |
| 819 | pmd_t *pmd; |
| 820 | |
| 821 | /* we're still single threaded hence no lock needed here */ |
| 822 | for (vm = vmlist; vm; vm = vm->next) { |
Russell King | a849088 | 2012-08-25 09:03:15 +0100 | [diff] [blame] | 823 | if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING))) |
Nicolas Pitre | 19b52ab | 2012-06-27 17:28:57 +0100 | [diff] [blame] | 824 | continue; |
| 825 | addr = (unsigned long)vm->addr; |
| 826 | if (addr < next) |
| 827 | continue; |
| 828 | |
| 829 | /* |
| 830 | * Check if this vm starts on an odd section boundary. |
| 831 | * If so and the first section entry for this PMD is free |
| 832 | * then we block the corresponding virtual address. |
| 833 | */ |
| 834 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { |
| 835 | pmd = pmd_off_k(addr); |
| 836 | if (pmd_none(*pmd)) |
| 837 | pmd_empty_section_gap(addr & PMD_MASK); |
| 838 | } |
| 839 | |
| 840 | /* |
| 841 | * Then check if this vm ends on an odd section boundary. |
| 842 | * If so and the second section entry for this PMD is empty |
| 843 | * then we block the corresponding virtual address. |
| 844 | */ |
| 845 | addr += vm->size; |
| 846 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { |
| 847 | pmd = pmd_off_k(addr) + 1; |
| 848 | if (pmd_none(*pmd)) |
| 849 | pmd_empty_section_gap(addr); |
| 850 | } |
| 851 | |
| 852 | /* no need to look at any vm entry until we hit the next PMD */ |
| 853 | next = (addr + PMD_SIZE - 1) & PMD_MASK; |
| 854 | } |
| 855 | } |
| 856 | |
| 857 | #else |
| 858 | #define fill_pmd_gaps() do { } while (0) |
| 859 | #endif |
| 860 | |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 861 | static void * __initdata vmalloc_min = |
| 862 | (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); |
Russell King | 6c5da7a | 2008-09-30 19:31:44 +0100 | [diff] [blame] | 863 | |
| 864 | /* |
| 865 | * vmalloc=size forces the vmalloc area to be exactly 'size' |
| 866 | * bytes. This can be used to increase (or decrease) the vmalloc |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 867 | * area - the default is 240m. |
Russell King | 6c5da7a | 2008-09-30 19:31:44 +0100 | [diff] [blame] | 868 | */ |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 869 | static int __init early_vmalloc(char *arg) |
Russell King | 6c5da7a | 2008-09-30 19:31:44 +0100 | [diff] [blame] | 870 | { |
Russell King | 7961239 | 2010-05-22 16:20:14 +0100 | [diff] [blame] | 871 | unsigned long vmalloc_reserve = memparse(arg, NULL); |
Russell King | 6c5da7a | 2008-09-30 19:31:44 +0100 | [diff] [blame] | 872 | |
| 873 | if (vmalloc_reserve < SZ_16M) { |
| 874 | vmalloc_reserve = SZ_16M; |
| 875 | printk(KERN_WARNING |
| 876 | "vmalloc area too small, limiting to %luMB\n", |
| 877 | vmalloc_reserve >> 20); |
| 878 | } |
Nicolas Pitre | 9210807 | 2008-09-19 10:43:06 -0400 | [diff] [blame] | 879 | |
| 880 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { |
| 881 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); |
| 882 | printk(KERN_WARNING |
| 883 | "vmalloc area is too big, limiting to %luMB\n", |
| 884 | vmalloc_reserve >> 20); |
| 885 | } |
Russell King | 7961239 | 2010-05-22 16:20:14 +0100 | [diff] [blame] | 886 | |
| 887 | vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 888 | return 0; |
Russell King | 6c5da7a | 2008-09-30 19:31:44 +0100 | [diff] [blame] | 889 | } |
Jeremy Kerr | 2b0d8c2 | 2010-01-11 23:17:34 +0100 | [diff] [blame] | 890 | early_param("vmalloc", early_vmalloc); |
Russell King | 6c5da7a | 2008-09-30 19:31:44 +0100 | [diff] [blame] | 891 | |
Marek Szyprowski | c790950 | 2011-12-29 13:09:51 +0100 | [diff] [blame] | 892 | phys_addr_t arm_lowmem_limit __initdata = 0; |
Russell King | 8df6516 | 2010-10-27 19:57:38 +0100 | [diff] [blame] | 893 | |
Russell King | 0371d3f | 2011-07-05 19:58:29 +0100 | [diff] [blame] | 894 | void __init sanity_check_meminfo(void) |
Lennert Buytenhek | 60296c7 | 2008-08-05 01:56:13 +0200 | [diff] [blame] | 895 | { |
Russell King | dde5828 | 2009-08-15 12:36:00 +0100 | [diff] [blame] | 896 | int i, j, highmem = 0; |
Lennert Buytenhek | 60296c7 | 2008-08-05 01:56:13 +0200 | [diff] [blame] | 897 | |
Nicolas Pitre | 4b5f32c | 2008-10-06 13:24:40 -0400 | [diff] [blame] | 898 | for (i = 0, j = 0; i < meminfo.nr_banks; i++) { |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 899 | struct membank *bank = &meminfo.bank[j]; |
| 900 | *bank = meminfo.bank[i]; |
| 901 | |
Will Deacon | 77f73a2 | 2011-11-22 17:30:32 +0000 | [diff] [blame] | 902 | if (bank->start > ULONG_MAX) |
| 903 | highmem = 1; |
| 904 | |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 905 | #ifdef CONFIG_HIGHMEM |
Will Deacon | 40f7bfe | 2011-05-19 13:22:48 +0100 | [diff] [blame] | 906 | if (__va(bank->start) >= vmalloc_min || |
Russell King | dde5828 | 2009-08-15 12:36:00 +0100 | [diff] [blame] | 907 | __va(bank->start) < (void *)PAGE_OFFSET) |
| 908 | highmem = 1; |
| 909 | |
| 910 | bank->highmem = highmem; |
| 911 | |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 912 | /* |
| 913 | * Split those memory banks which are partially overlapping |
| 914 | * the vmalloc area greatly simplifying things later. |
| 915 | */ |
Will Deacon | 77f73a2 | 2011-11-22 17:30:32 +0000 | [diff] [blame] | 916 | if (!highmem && __va(bank->start) < vmalloc_min && |
Russell King | 7961239 | 2010-05-22 16:20:14 +0100 | [diff] [blame] | 917 | bank->size > vmalloc_min - __va(bank->start)) { |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 918 | if (meminfo.nr_banks >= NR_BANKS) { |
| 919 | printk(KERN_CRIT "NR_BANKS too low, " |
| 920 | "ignoring high memory\n"); |
| 921 | } else { |
| 922 | memmove(bank + 1, bank, |
| 923 | (meminfo.nr_banks - i) * sizeof(*bank)); |
| 924 | meminfo.nr_banks++; |
| 925 | i++; |
Russell King | 7961239 | 2010-05-22 16:20:14 +0100 | [diff] [blame] | 926 | bank[1].size -= vmalloc_min - __va(bank->start); |
| 927 | bank[1].start = __pa(vmalloc_min - 1) + 1; |
Russell King | dde5828 | 2009-08-15 12:36:00 +0100 | [diff] [blame] | 928 | bank[1].highmem = highmem = 1; |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 929 | j++; |
| 930 | } |
Russell King | 7961239 | 2010-05-22 16:20:14 +0100 | [diff] [blame] | 931 | bank->size = vmalloc_min - __va(bank->start); |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 932 | } |
| 933 | #else |
Russell King | 041d785 | 2009-09-27 17:40:42 +0100 | [diff] [blame] | 934 | bank->highmem = highmem; |
| 935 | |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 936 | /* |
Will Deacon | 77f73a2 | 2011-11-22 17:30:32 +0000 | [diff] [blame] | 937 | * Highmem banks not allowed with !CONFIG_HIGHMEM. |
| 938 | */ |
| 939 | if (highmem) { |
| 940 | printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " |
| 941 | "(!CONFIG_HIGHMEM).\n", |
| 942 | (unsigned long long)bank->start, |
| 943 | (unsigned long long)bank->start + bank->size - 1); |
| 944 | continue; |
| 945 | } |
| 946 | |
| 947 | /* |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 948 | * Check whether this memory bank would entirely overlap |
| 949 | * the vmalloc area. |
| 950 | */ |
Russell King | 7961239 | 2010-05-22 16:20:14 +0100 | [diff] [blame] | 951 | if (__va(bank->start) >= vmalloc_min || |
Mikael Pettersson | f0bba9f9 | 2009-03-28 19:18:05 +0100 | [diff] [blame] | 952 | __va(bank->start) < (void *)PAGE_OFFSET) { |
Russell King | e33b9d0 | 2011-02-20 11:47:41 +0000 | [diff] [blame] | 953 | printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 954 | "(vmalloc region overlap).\n", |
Russell King | e33b9d0 | 2011-02-20 11:47:41 +0000 | [diff] [blame] | 955 | (unsigned long long)bank->start, |
| 956 | (unsigned long long)bank->start + bank->size - 1); |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 957 | continue; |
| 958 | } |
| 959 | |
| 960 | /* |
| 961 | * Check whether this memory bank would partially overlap |
| 962 | * the vmalloc area. |
| 963 | */ |
Jonathan Austin | 36418c5 | 2012-08-23 14:02:59 +0100 | [diff] [blame^] | 964 | if (__va(bank->start + bank->size - 1) >= vmalloc_min || |
| 965 | __va(bank->start + bank->size - 1) <= __va(bank->start)) { |
Russell King | 7961239 | 2010-05-22 16:20:14 +0100 | [diff] [blame] | 966 | unsigned long newsize = vmalloc_min - __va(bank->start); |
Russell King | e33b9d0 | 2011-02-20 11:47:41 +0000 | [diff] [blame] | 967 | printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " |
| 968 | "to -%.8llx (vmalloc region overlap).\n", |
| 969 | (unsigned long long)bank->start, |
| 970 | (unsigned long long)bank->start + bank->size - 1, |
| 971 | (unsigned long long)bank->start + newsize - 1); |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 972 | bank->size = newsize; |
| 973 | } |
| 974 | #endif |
Marek Szyprowski | c790950 | 2011-12-29 13:09:51 +0100 | [diff] [blame] | 975 | if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit) |
| 976 | arm_lowmem_limit = bank->start + bank->size; |
Will Deacon | 40f7bfe | 2011-05-19 13:22:48 +0100 | [diff] [blame] | 977 | |
Nicolas Pitre | a1bbaec | 2008-09-02 11:44:21 -0400 | [diff] [blame] | 978 | j++; |
Lennert Buytenhek | 60296c7 | 2008-08-05 01:56:13 +0200 | [diff] [blame] | 979 | } |
Russell King | e616c59 | 2009-09-27 20:55:43 +0100 | [diff] [blame] | 980 | #ifdef CONFIG_HIGHMEM |
| 981 | if (highmem) { |
| 982 | const char *reason = NULL; |
| 983 | |
| 984 | if (cache_is_vipt_aliasing()) { |
| 985 | /* |
| 986 | * Interactions between kmap and other mappings |
| 987 | * make highmem support with aliasing VIPT caches |
| 988 | * rather difficult. |
| 989 | */ |
| 990 | reason = "with VIPT aliasing cache"; |
Russell King | e616c59 | 2009-09-27 20:55:43 +0100 | [diff] [blame] | 991 | } |
| 992 | if (reason) { |
| 993 | printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", |
| 994 | reason); |
| 995 | while (j > 0 && meminfo.bank[j - 1].highmem) |
| 996 | j--; |
| 997 | } |
| 998 | } |
| 999 | #endif |
Nicolas Pitre | 4b5f32c | 2008-10-06 13:24:40 -0400 | [diff] [blame] | 1000 | meminfo.nr_banks = j; |
Marek Szyprowski | c790950 | 2011-12-29 13:09:51 +0100 | [diff] [blame] | 1001 | high_memory = __va(arm_lowmem_limit - 1) + 1; |
| 1002 | memblock_set_current_limit(arm_lowmem_limit); |
Lennert Buytenhek | 60296c7 | 2008-08-05 01:56:13 +0200 | [diff] [blame] | 1003 | } |
| 1004 | |
Nicolas Pitre | 4b5f32c | 2008-10-06 13:24:40 -0400 | [diff] [blame] | 1005 | static inline void prepare_page_table(void) |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1006 | { |
| 1007 | unsigned long addr; |
Russell King | 8df6516 | 2010-10-27 19:57:38 +0100 | [diff] [blame] | 1008 | phys_addr_t end; |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1009 | |
| 1010 | /* |
| 1011 | * Clear out all the mappings below the kernel image. |
| 1012 | */ |
Catalin Marinas | e73fc88 | 2011-08-23 14:07:23 +0100 | [diff] [blame] | 1013 | for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1014 | pmd_clear(pmd_off_k(addr)); |
| 1015 | |
| 1016 | #ifdef CONFIG_XIP_KERNEL |
| 1017 | /* The XIP kernel is mapped in the module area -- skip over it */ |
Catalin Marinas | e73fc88 | 2011-08-23 14:07:23 +0100 | [diff] [blame] | 1018 | addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1019 | #endif |
Catalin Marinas | e73fc88 | 2011-08-23 14:07:23 +0100 | [diff] [blame] | 1020 | for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1021 | pmd_clear(pmd_off_k(addr)); |
| 1022 | |
| 1023 | /* |
Russell King | 8df6516 | 2010-10-27 19:57:38 +0100 | [diff] [blame] | 1024 | * Find the end of the first block of lowmem. |
| 1025 | */ |
| 1026 | end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; |
Marek Szyprowski | c790950 | 2011-12-29 13:09:51 +0100 | [diff] [blame] | 1027 | if (end >= arm_lowmem_limit) |
| 1028 | end = arm_lowmem_limit; |
Russell King | 8df6516 | 2010-10-27 19:57:38 +0100 | [diff] [blame] | 1029 | |
| 1030 | /* |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1031 | * Clear out all the kernel space mappings, except for the first |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 1032 | * memory bank, up to the vmalloc region. |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1033 | */ |
Russell King | 8df6516 | 2010-10-27 19:57:38 +0100 | [diff] [blame] | 1034 | for (addr = __phys_to_virt(end); |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 1035 | addr < VMALLOC_START; addr += PMD_SIZE) |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1036 | pmd_clear(pmd_off_k(addr)); |
| 1037 | } |
| 1038 | |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 1039 | #ifdef CONFIG_ARM_LPAE |
| 1040 | /* the first page is reserved for pgd */ |
| 1041 | #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ |
| 1042 | PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) |
| 1043 | #else |
Catalin Marinas | e73fc88 | 2011-08-23 14:07:23 +0100 | [diff] [blame] | 1044 | #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 1045 | #endif |
Catalin Marinas | e73fc88 | 2011-08-23 14:07:23 +0100 | [diff] [blame] | 1046 | |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1047 | /* |
Russell King | 2778f62 | 2010-07-09 16:27:52 +0100 | [diff] [blame] | 1048 | * Reserve the special regions of memory |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1049 | */ |
Russell King | 2778f62 | 2010-07-09 16:27:52 +0100 | [diff] [blame] | 1050 | void __init arm_mm_memblock_reserve(void) |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1051 | { |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1052 | /* |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1053 | * Reserve the page tables. These are already in use, |
| 1054 | * and can only be in node 0. |
| 1055 | */ |
Catalin Marinas | e73fc88 | 2011-08-23 14:07:23 +0100 | [diff] [blame] | 1056 | memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1057 | |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1058 | #ifdef CONFIG_SA1111 |
| 1059 | /* |
| 1060 | * Because of the SA1111 DMA bug, we want to preserve our |
| 1061 | * precious DMA-able memory... |
| 1062 | */ |
Russell King | 2778f62 | 2010-07-09 16:27:52 +0100 | [diff] [blame] | 1063 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1064 | #endif |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1065 | } |
| 1066 | |
| 1067 | /* |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 1068 | * Set up the device mappings. Since we clear out the page tables for all |
| 1069 | * mappings above VMALLOC_START, we will remove any debug device mappings. |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1070 | * This means you have to be careful how you debug this function, or any |
| 1071 | * called function. This means you can't use any function or debugging |
| 1072 | * method which may touch any device, otherwise the kernel _will_ crash. |
| 1073 | */ |
| 1074 | static void __init devicemaps_init(struct machine_desc *mdesc) |
| 1075 | { |
| 1076 | struct map_desc map; |
| 1077 | unsigned long addr; |
Russell King | 94e5a85 | 2012-01-18 15:32:49 +0000 | [diff] [blame] | 1078 | void *vectors; |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1079 | |
| 1080 | /* |
| 1081 | * Allocate the vector page early. |
| 1082 | */ |
Russell King | 94e5a85 | 2012-01-18 15:32:49 +0000 | [diff] [blame] | 1083 | vectors = early_alloc(PAGE_SIZE); |
| 1084 | |
| 1085 | early_trap_init(vectors); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1086 | |
Nicolas Pitre | 0536bdf | 2011-08-25 00:35:59 -0400 | [diff] [blame] | 1087 | for (addr = VMALLOC_START; addr; addr += PMD_SIZE) |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1088 | pmd_clear(pmd_off_k(addr)); |
| 1089 | |
| 1090 | /* |
| 1091 | * Map the kernel if it is XIP. |
| 1092 | * It is always first in the modulearea. |
| 1093 | */ |
| 1094 | #ifdef CONFIG_XIP_KERNEL |
| 1095 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); |
Russell King | ab4f2ee | 2008-11-06 17:11:07 +0000 | [diff] [blame] | 1096 | map.virtual = MODULES_VADDR; |
Russell King | 37efe64 | 2008-12-01 11:53:07 +0000 | [diff] [blame] | 1097 | map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1098 | map.type = MT_ROM; |
| 1099 | create_mapping(&map); |
| 1100 | #endif |
| 1101 | |
| 1102 | /* |
| 1103 | * Map the cache flushing regions. |
| 1104 | */ |
| 1105 | #ifdef FLUSH_BASE |
| 1106 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); |
| 1107 | map.virtual = FLUSH_BASE; |
| 1108 | map.length = SZ_1M; |
| 1109 | map.type = MT_CACHECLEAN; |
| 1110 | create_mapping(&map); |
| 1111 | #endif |
| 1112 | #ifdef FLUSH_BASE_MINICACHE |
| 1113 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); |
| 1114 | map.virtual = FLUSH_BASE_MINICACHE; |
| 1115 | map.length = SZ_1M; |
| 1116 | map.type = MT_MINICLEAN; |
| 1117 | create_mapping(&map); |
| 1118 | #endif |
| 1119 | |
| 1120 | /* |
| 1121 | * Create a mapping for the machine vectors at the high-vectors |
| 1122 | * location (0xffff0000). If we aren't using high-vectors, also |
| 1123 | * create a mapping at the low-vectors virtual address. |
| 1124 | */ |
Russell King | 94e5a85 | 2012-01-18 15:32:49 +0000 | [diff] [blame] | 1125 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1126 | map.virtual = 0xffff0000; |
| 1127 | map.length = PAGE_SIZE; |
| 1128 | map.type = MT_HIGH_VECTORS; |
| 1129 | create_mapping(&map); |
| 1130 | |
| 1131 | if (!vectors_high()) { |
| 1132 | map.virtual = 0; |
| 1133 | map.type = MT_LOW_VECTORS; |
| 1134 | create_mapping(&map); |
| 1135 | } |
| 1136 | |
| 1137 | /* |
| 1138 | * Ask the machine support to map in the statically mapped devices. |
| 1139 | */ |
| 1140 | if (mdesc->map_io) |
| 1141 | mdesc->map_io(); |
Nicolas Pitre | 19b52ab | 2012-06-27 17:28:57 +0100 | [diff] [blame] | 1142 | fill_pmd_gaps(); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1143 | |
| 1144 | /* |
| 1145 | * Finally flush the caches and tlb to ensure that we're in a |
| 1146 | * consistent state wrt the writebuffer. This also ensures that |
| 1147 | * any write-allocated cache lines in the vector page are written |
| 1148 | * back. After this point, we can start to touch devices again. |
| 1149 | */ |
| 1150 | local_flush_tlb_all(); |
| 1151 | flush_cache_all(); |
| 1152 | } |
| 1153 | |
Nicolas Pitre | d73cd42 | 2008-09-15 16:44:55 -0400 | [diff] [blame] | 1154 | static void __init kmap_init(void) |
| 1155 | { |
| 1156 | #ifdef CONFIG_HIGHMEM |
Russell King | 4bb2e27 | 2010-07-01 18:33:29 +0100 | [diff] [blame] | 1157 | pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
| 1158 | PKMAP_BASE, _PAGE_KERNEL_TABLE); |
Nicolas Pitre | d73cd42 | 2008-09-15 16:44:55 -0400 | [diff] [blame] | 1159 | #endif |
| 1160 | } |
| 1161 | |
Russell King | a222712 | 2010-03-25 18:56:05 +0000 | [diff] [blame] | 1162 | static void __init map_lowmem(void) |
| 1163 | { |
Russell King | 8df6516 | 2010-10-27 19:57:38 +0100 | [diff] [blame] | 1164 | struct memblock_region *reg; |
Russell King | a222712 | 2010-03-25 18:56:05 +0000 | [diff] [blame] | 1165 | |
| 1166 | /* Map all the lowmem memory banks. */ |
Russell King | 8df6516 | 2010-10-27 19:57:38 +0100 | [diff] [blame] | 1167 | for_each_memblock(memory, reg) { |
| 1168 | phys_addr_t start = reg->base; |
| 1169 | phys_addr_t end = start + reg->size; |
| 1170 | struct map_desc map; |
Russell King | a222712 | 2010-03-25 18:56:05 +0000 | [diff] [blame] | 1171 | |
Marek Szyprowski | c790950 | 2011-12-29 13:09:51 +0100 | [diff] [blame] | 1172 | if (end > arm_lowmem_limit) |
| 1173 | end = arm_lowmem_limit; |
Russell King | 8df6516 | 2010-10-27 19:57:38 +0100 | [diff] [blame] | 1174 | if (start >= end) |
| 1175 | break; |
| 1176 | |
| 1177 | map.pfn = __phys_to_pfn(start); |
| 1178 | map.virtual = __phys_to_virt(start); |
| 1179 | map.length = end - start; |
| 1180 | map.type = MT_MEMORY; |
| 1181 | |
| 1182 | create_mapping(&map); |
Russell King | a222712 | 2010-03-25 18:56:05 +0000 | [diff] [blame] | 1183 | } |
| 1184 | } |
| 1185 | |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1186 | /* |
| 1187 | * paging_init() sets up the page tables, initialises the zone memory |
| 1188 | * maps, and sets up the zero page, bad page and bad page tables. |
| 1189 | */ |
Nicolas Pitre | 4b5f32c | 2008-10-06 13:24:40 -0400 | [diff] [blame] | 1190 | void __init paging_init(struct machine_desc *mdesc) |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1191 | { |
| 1192 | void *zero_page; |
| 1193 | |
Marek Szyprowski | c790950 | 2011-12-29 13:09:51 +0100 | [diff] [blame] | 1194 | memblock_set_current_limit(arm_lowmem_limit); |
Russell King | 0371d3f | 2011-07-05 19:58:29 +0100 | [diff] [blame] | 1195 | |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1196 | build_mem_type_table(); |
Nicolas Pitre | 4b5f32c | 2008-10-06 13:24:40 -0400 | [diff] [blame] | 1197 | prepare_page_table(); |
Russell King | a222712 | 2010-03-25 18:56:05 +0000 | [diff] [blame] | 1198 | map_lowmem(); |
Marek Szyprowski | c790950 | 2011-12-29 13:09:51 +0100 | [diff] [blame] | 1199 | dma_contiguous_remap(); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1200 | devicemaps_init(mdesc); |
Nicolas Pitre | d73cd42 | 2008-09-15 16:44:55 -0400 | [diff] [blame] | 1201 | kmap_init(); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1202 | |
| 1203 | top_pmd = pmd_off_k(0xffff0000); |
| 1204 | |
Russell King | 3abe9d3 | 2010-03-25 17:02:59 +0000 | [diff] [blame] | 1205 | /* allocate the zero page. */ |
| 1206 | zero_page = early_alloc(PAGE_SIZE); |
Russell King | 2778f62 | 2010-07-09 16:27:52 +0100 | [diff] [blame] | 1207 | |
Russell King | 8d717a5 | 2010-05-22 19:47:18 +0100 | [diff] [blame] | 1208 | bootmem_init(); |
Russell King | 2778f62 | 2010-07-09 16:27:52 +0100 | [diff] [blame] | 1209 | |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1210 | empty_zero_page = virt_to_page(zero_page); |
Russell King | 421fe93 | 2009-10-25 10:23:04 +0000 | [diff] [blame] | 1211 | __flush_dcache_page(NULL, empty_zero_page); |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1212 | } |