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Laurent Pinchart4bf8e192013-06-19 13:54:11 +02001/*
2 * rcar_du_crtc.c -- R-Car Display Unit CRTCs
3 *
Laurent Pinchart36d50462014-02-06 18:13:52 +01004 * Copyright (C) 2013-2014 Renesas Electronics Corporation
Laurent Pinchart4bf8e192013-06-19 13:54:11 +02005 *
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/clk.h>
15#include <linux/mutex.h>
16
17#include <drm/drmP.h>
18#include <drm/drm_crtc.h>
19#include <drm/drm_crtc_helper.h>
20#include <drm/drm_fb_cma_helper.h>
21#include <drm/drm_gem_cma_helper.h>
Daniel Vetter3cb9ae42014-10-29 10:03:57 +010022#include <drm/drm_plane_helper.h>
Laurent Pinchart4bf8e192013-06-19 13:54:11 +020023
24#include "rcar_du_crtc.h"
25#include "rcar_du_drv.h"
26#include "rcar_du_kms.h"
Laurent Pinchart4bf8e192013-06-19 13:54:11 +020027#include "rcar_du_plane.h"
28#include "rcar_du_regs.h"
Laurent Pinchart4bf8e192013-06-19 13:54:11 +020029
Laurent Pinchart4bf8e192013-06-19 13:54:11 +020030static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
31{
Laurent Pinchartcb2025d2013-06-16 21:01:02 +020032 struct rcar_du_device *rcdu = rcrtc->group->dev;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +020033
34 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
35}
36
37static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
38{
Laurent Pinchartcb2025d2013-06-16 21:01:02 +020039 struct rcar_du_device *rcdu = rcrtc->group->dev;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +020040
41 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
42}
43
44static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
45{
Laurent Pinchartcb2025d2013-06-16 21:01:02 +020046 struct rcar_du_device *rcdu = rcrtc->group->dev;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +020047
48 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
49 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
50}
51
52static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
53{
Laurent Pinchartcb2025d2013-06-16 21:01:02 +020054 struct rcar_du_device *rcdu = rcrtc->group->dev;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +020055
56 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
57 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
58}
59
60static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
61 u32 clr, u32 set)
62{
Laurent Pinchartcb2025d2013-06-16 21:01:02 +020063 struct rcar_du_device *rcdu = rcrtc->group->dev;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +020064 u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
65
66 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
67}
68
Laurent Pinchartf66ee302013-06-14 14:15:01 +020069static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
70{
Laurent Pinchartf66ee302013-06-14 14:15:01 +020071 int ret;
72
73 ret = clk_prepare_enable(rcrtc->clock);
74 if (ret < 0)
75 return ret;
76
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +020077 ret = clk_prepare_enable(rcrtc->extclock);
78 if (ret < 0)
79 goto error_clock;
80
Laurent Pinchartcb2025d2013-06-16 21:01:02 +020081 ret = rcar_du_group_get(rcrtc->group);
Laurent Pinchartf66ee302013-06-14 14:15:01 +020082 if (ret < 0)
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +020083 goto error_group;
Laurent Pinchartf66ee302013-06-14 14:15:01 +020084
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +020085 return 0;
86
87error_group:
88 clk_disable_unprepare(rcrtc->extclock);
89error_clock:
90 clk_disable_unprepare(rcrtc->clock);
Laurent Pinchartf66ee302013-06-14 14:15:01 +020091 return ret;
92}
93
94static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
95{
Laurent Pinchartcb2025d2013-06-16 21:01:02 +020096 rcar_du_group_put(rcrtc->group);
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +020097
98 clk_disable_unprepare(rcrtc->extclock);
Laurent Pinchartf66ee302013-06-14 14:15:01 +020099 clk_disable_unprepare(rcrtc->clock);
100}
101
Laurent Pinchart17f6b8a2015-02-18 13:42:40 +0200102/* -----------------------------------------------------------------------------
103 * Hardware Setup
104 */
105
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200106static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
107{
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200108 const struct drm_display_mode *mode = &rcrtc->crtc.mode;
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +0200109 unsigned long mode_clock = mode->clock * 1000;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200110 unsigned long clk;
111 u32 value;
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +0200112 u32 escr;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200113 u32 div;
114
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +0200115 /* Compute the clock divisor and select the internal or external dot
116 * clock based on the requested frequency.
117 */
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200118 clk = clk_get_rate(rcrtc->clock);
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +0200119 div = DIV_ROUND_CLOSEST(clk, mode_clock);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200120 div = clamp(div, 1U, 64U) - 1;
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +0200121 escr = div | ESCR_DCLKSEL_CLKS;
122
123 if (rcrtc->extclock) {
124 unsigned long extclk;
125 unsigned long extrate;
126 unsigned long rate;
127 u32 extdiv;
128
129 extclk = clk_get_rate(rcrtc->extclock);
130 extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
131 extdiv = clamp(extdiv, 1U, 64U) - 1;
132
133 rate = clk / (div + 1);
134 extrate = extclk / (extdiv + 1);
135
136 if (abs((long)extrate - (long)mode_clock) <
137 abs((long)rate - (long)mode_clock)) {
138 dev_dbg(rcrtc->group->dev->dev,
139 "crtc%u: using external clock\n", rcrtc->index);
140 escr = extdiv | ESCR_DCLKSEL_DCLKIN;
141 }
142 }
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200143
Laurent Pincharta5f0ef52013-06-17 00:29:25 +0200144 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +0200145 escr);
Laurent Pincharta5f0ef52013-06-17 00:29:25 +0200146 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200147
148 /* Signal polarities */
149 value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
150 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
Laurent Pinchartf67e1e02014-12-09 00:40:59 +0200151 | DSMR_DIPM_DE | DSMR_CSPM;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200152 rcar_du_crtc_write(rcrtc, DSMR, value);
153
154 /* Display timings */
155 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
156 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
157 mode->hdisplay - 19);
158 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
159 mode->hsync_start - 1);
160 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
161
Laurent Pinchart906eff72014-12-09 19:11:18 +0200162 rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
163 mode->crtc_vsync_end - 2);
164 rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
165 mode->crtc_vsync_end +
166 mode->crtc_vdisplay - 2);
167 rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
168 mode->crtc_vsync_end +
169 mode->crtc_vsync_start - 1);
170 rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200171
172 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start);
173 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
174}
175
Laurent Pinchartef67a902013-06-17 03:13:11 +0200176void rcar_du_crtc_route_output(struct drm_crtc *crtc,
177 enum rcar_du_output output)
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200178{
179 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
Laurent Pinchartef67a902013-06-17 03:13:11 +0200180 struct rcar_du_device *rcdu = rcrtc->group->dev;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200181
182 /* Store the route from the CRTC output to the DU output. The DU will be
183 * configured when starting the CRTC.
184 */
Laurent Pinchartef67a902013-06-17 03:13:11 +0200185 rcrtc->outputs |= BIT(output);
Laurent Pinchart7cbc05c2013-06-17 03:20:08 +0200186
Laurent Pinchart0c1c8772014-12-09 00:21:12 +0200187 /* Store RGB routing to DPAD0, the hardware will be configured when
188 * starting the CRTC.
189 */
190 if (output == RCAR_DU_OUTPUT_DPAD0)
Laurent Pinchart7cbc05c2013-06-17 03:20:08 +0200191 rcdu->dpad0_source = rcrtc->index;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200192}
193
194void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
195{
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200196 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
197 struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
198 unsigned int num_planes = 0;
199 unsigned int prio = 0;
200 unsigned int i;
201 u32 dptsr = 0;
202 u32 dspr = 0;
203
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200204 for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
205 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200206 unsigned int j;
207
208 if (plane->crtc != &rcrtc->crtc || !plane->enabled)
209 continue;
210
211 /* Insert the plane in the sorted planes array. */
212 for (j = num_planes++; j > 0; --j) {
213 if (planes[j-1]->zpos <= plane->zpos)
214 break;
215 planes[j] = planes[j-1];
216 }
217
218 planes[j] = plane;
219 prio += plane->format->planes * 4;
220 }
221
222 for (i = 0; i < num_planes; ++i) {
223 struct rcar_du_plane *plane = planes[i];
224 unsigned int index = plane->hwindex;
225
226 prio -= 4;
227 dspr |= (index + 1) << prio;
228 dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index);
229
230 if (plane->format->planes == 2) {
231 index = (index + 1) % 8;
232
233 prio -= 4;
234 dspr |= (index + 1) << prio;
235 dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index);
236 }
237 }
238
239 /* Select display timing and dot clock generator 2 for planes associated
240 * with superposition controller 2.
241 */
Laurent Pincharta5f0ef52013-06-17 00:29:25 +0200242 if (rcrtc->index % 2) {
243 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200244
245 /* The DPTSR register is updated when the display controller is
246 * stopped. We thus need to restart the DU. Once again, sorry
247 * for the flicker. One way to mitigate the issue would be to
248 * pre-associate planes with CRTCs (either with a fixed 4/4
249 * split, or through a module parameter). Flicker would then
250 * occur only if we need to break the pre-association.
251 */
252 if (value != dptsr) {
Laurent Pincharta5f0ef52013-06-17 00:29:25 +0200253 rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200254 if (rcrtc->group->used_crtcs)
255 rcar_du_group_restart(rcrtc->group);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200256 }
257 }
258
Laurent Pincharta5f0ef52013-06-17 00:29:25 +0200259 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
260 dspr);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200261}
262
Laurent Pinchart17f6b8a2015-02-18 13:42:40 +0200263/* -----------------------------------------------------------------------------
264 * Page Flip
265 */
266
267void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
268 struct drm_file *file)
269{
270 struct drm_pending_vblank_event *event;
271 struct drm_device *dev = rcrtc->crtc.dev;
272 unsigned long flags;
273
274 /* Destroy the pending vertical blanking event associated with the
275 * pending page flip, if any, and disable vertical blanking interrupts.
276 */
277 spin_lock_irqsave(&dev->event_lock, flags);
278 event = rcrtc->event;
279 if (event && event->base.file_priv == file) {
280 rcrtc->event = NULL;
281 event->base.destroy(&event->base);
282 drm_vblank_put(dev, rcrtc->index);
283 }
284 spin_unlock_irqrestore(&dev->event_lock, flags);
285}
286
287static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
288{
289 struct drm_pending_vblank_event *event;
290 struct drm_device *dev = rcrtc->crtc.dev;
291 unsigned long flags;
292
293 spin_lock_irqsave(&dev->event_lock, flags);
294 event = rcrtc->event;
295 rcrtc->event = NULL;
296 spin_unlock_irqrestore(&dev->event_lock, flags);
297
298 if (event == NULL)
299 return;
300
301 spin_lock_irqsave(&dev->event_lock, flags);
302 drm_send_vblank_event(dev, rcrtc->index, event);
Laurent Pinchart36693f32015-02-18 13:21:56 +0200303 wake_up(&rcrtc->flip_wait);
Laurent Pinchart17f6b8a2015-02-18 13:42:40 +0200304 spin_unlock_irqrestore(&dev->event_lock, flags);
305
306 drm_vblank_put(dev, rcrtc->index);
307}
308
Laurent Pinchart36693f32015-02-18 13:21:56 +0200309static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
310{
311 struct drm_device *dev = rcrtc->crtc.dev;
312 unsigned long flags;
313 bool pending;
314
315 spin_lock_irqsave(&dev->event_lock, flags);
316 pending = rcrtc->event != NULL;
317 spin_unlock_irqrestore(&dev->event_lock, flags);
318
319 return pending;
320}
321
322static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
323{
324 struct rcar_du_device *rcdu = rcrtc->group->dev;
325
326 if (wait_event_timeout(rcrtc->flip_wait,
327 !rcar_du_crtc_page_flip_pending(rcrtc),
328 msecs_to_jiffies(50)))
329 return;
330
331 dev_warn(rcdu->dev, "page flip timeout\n");
332
333 rcar_du_crtc_finish_page_flip(rcrtc);
334}
335
Laurent Pinchart17f6b8a2015-02-18 13:42:40 +0200336/* -----------------------------------------------------------------------------
337 * Start/Stop and Suspend/Resume
338 */
339
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200340static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
341{
342 struct drm_crtc *crtc = &rcrtc->crtc;
Laurent Pinchart906eff72014-12-09 19:11:18 +0200343 bool interlaced;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200344 unsigned int i;
345
346 if (rcrtc->started)
347 return;
348
349 if (WARN_ON(rcrtc->plane->format == NULL))
350 return;
351
352 /* Set display off and background to black */
353 rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
354 rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
355
356 /* Configure display timings and output routing */
357 rcar_du_crtc_set_display_timing(rcrtc);
Laurent Pinchart2fd22db2013-06-17 00:11:05 +0200358 rcar_du_group_set_routing(rcrtc->group);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200359
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200360 mutex_lock(&rcrtc->group->planes.lock);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200361 rcrtc->plane->enabled = true;
362 rcar_du_crtc_update_planes(crtc);
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200363 mutex_unlock(&rcrtc->group->planes.lock);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200364
365 /* Setup planes. */
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200366 for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
367 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200368
369 if (plane->crtc != crtc || !plane->enabled)
370 continue;
371
372 rcar_du_plane_setup(plane);
373 }
374
375 /* Select master sync mode. This enables display operation in master
376 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
377 * actively driven).
378 */
Laurent Pinchart906eff72014-12-09 19:11:18 +0200379 interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
380 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
381 (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
382 DSYSR_TVM_MASTER);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200383
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200384 rcar_du_group_start_stop(rcrtc->group, true);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200385
386 rcrtc->started = true;
387}
388
389static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
390{
391 struct drm_crtc *crtc = &rcrtc->crtc;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200392
393 if (!rcrtc->started)
394 return;
395
Laurent Pinchart36693f32015-02-18 13:21:56 +0200396 /* Wait for page flip completion before stopping the CRTC as userspace
397 * excepts page flips to eventually complete.
398 */
399 rcar_du_crtc_wait_page_flip(rcrtc);
400
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200401 mutex_lock(&rcrtc->group->planes.lock);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200402 rcrtc->plane->enabled = false;
403 rcar_du_crtc_update_planes(crtc);
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200404 mutex_unlock(&rcrtc->group->planes.lock);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200405
406 /* Select switch sync mode. This stops display operation and configures
407 * the HSYNC and VSYNC signals as inputs.
408 */
409 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
410
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200411 rcar_du_group_start_stop(rcrtc->group, false);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200412
413 rcrtc->started = false;
414}
415
416void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
417{
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200418 rcar_du_crtc_stop(rcrtc);
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200419 rcar_du_crtc_put(rcrtc);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200420}
421
422void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
423{
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200424 if (rcrtc->dpms != DRM_MODE_DPMS_ON)
425 return;
426
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200427 rcar_du_crtc_get(rcrtc);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200428 rcar_du_crtc_start(rcrtc);
429}
430
431static void rcar_du_crtc_update_base(struct rcar_du_crtc *rcrtc)
432{
433 struct drm_crtc *crtc = &rcrtc->crtc;
434
Matt Roperf4510a22014-04-01 15:22:40 -0700435 rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200436 rcar_du_plane_update_base(rcrtc->plane);
437}
438
Laurent Pinchart17f6b8a2015-02-18 13:42:40 +0200439/* -----------------------------------------------------------------------------
440 * CRTC Functions
441 */
442
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200443static void rcar_du_crtc_dpms(struct drm_crtc *crtc, int mode)
444{
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200445 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
446
Laurent Pinchart3dbf11e2014-12-09 13:19:10 +0200447 if (mode != DRM_MODE_DPMS_ON)
448 mode = DRM_MODE_DPMS_OFF;
449
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200450 if (rcrtc->dpms == mode)
451 return;
452
453 if (mode == DRM_MODE_DPMS_ON) {
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200454 rcar_du_crtc_get(rcrtc);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200455 rcar_du_crtc_start(rcrtc);
456 } else {
457 rcar_du_crtc_stop(rcrtc);
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200458 rcar_du_crtc_put(rcrtc);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200459 }
460
461 rcrtc->dpms = mode;
462}
463
464static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
465 const struct drm_display_mode *mode,
466 struct drm_display_mode *adjusted_mode)
467{
468 /* TODO Fixup modes */
469 return true;
470}
471
472static void rcar_du_crtc_mode_prepare(struct drm_crtc *crtc)
473{
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200474 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
475
476 /* We need to access the hardware during mode set, acquire a reference
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200477 * to the CRTC.
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200478 */
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200479 rcar_du_crtc_get(rcrtc);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200480
481 /* Stop the CRTC and release the plane. Force the DPMS mode to off as a
482 * result.
483 */
484 rcar_du_crtc_stop(rcrtc);
485 rcar_du_plane_release(rcrtc->plane);
486
487 rcrtc->dpms = DRM_MODE_DPMS_OFF;
488}
489
490static int rcar_du_crtc_mode_set(struct drm_crtc *crtc,
491 struct drm_display_mode *mode,
492 struct drm_display_mode *adjusted_mode,
493 int x, int y,
494 struct drm_framebuffer *old_fb)
495{
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200496 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200497 struct rcar_du_device *rcdu = rcrtc->group->dev;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200498 const struct rcar_du_format_info *format;
499 int ret;
500
Matt Roperf4510a22014-04-01 15:22:40 -0700501 format = rcar_du_format_info(crtc->primary->fb->pixel_format);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200502 if (format == NULL) {
503 dev_dbg(rcdu->dev, "mode_set: unsupported format %08x\n",
Matt Roperf4510a22014-04-01 15:22:40 -0700504 crtc->primary->fb->pixel_format);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200505 ret = -EINVAL;
506 goto error;
507 }
508
509 ret = rcar_du_plane_reserve(rcrtc->plane, format);
510 if (ret < 0)
511 goto error;
512
513 rcrtc->plane->format = format;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200514
515 rcrtc->plane->src_x = x;
516 rcrtc->plane->src_y = y;
517 rcrtc->plane->width = mode->hdisplay;
518 rcrtc->plane->height = mode->vdisplay;
519
Matt Roperf4510a22014-04-01 15:22:40 -0700520 rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200521
522 rcrtc->outputs = 0;
523
524 return 0;
525
526error:
527 /* There's no rollback/abort operation to clean up in case of error. We
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200528 * thus need to release the reference to the CRTC acquired in prepare()
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200529 * here.
530 */
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200531 rcar_du_crtc_put(rcrtc);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200532 return ret;
533}
534
535static void rcar_du_crtc_mode_commit(struct drm_crtc *crtc)
536{
537 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
538
539 /* We're done, restart the CRTC and set the DPMS mode to on. The
540 * reference to the DU acquired at prepare() time will thus be released
541 * by the DPMS handler (possibly called by the disable() handler).
542 */
543 rcar_du_crtc_start(rcrtc);
544 rcrtc->dpms = DRM_MODE_DPMS_ON;
545}
546
547static int rcar_du_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
548 struct drm_framebuffer *old_fb)
549{
550 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
551
552 rcrtc->plane->src_x = x;
553 rcrtc->plane->src_y = y;
554
Laurent Pinchartf5abcc42013-11-13 14:38:03 +0100555 rcar_du_crtc_update_base(rcrtc);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200556
557 return 0;
558}
559
560static void rcar_du_crtc_disable(struct drm_crtc *crtc)
561{
562 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
563
564 rcar_du_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
565 rcar_du_plane_release(rcrtc->plane);
566}
567
568static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
569 .dpms = rcar_du_crtc_dpms,
570 .mode_fixup = rcar_du_crtc_mode_fixup,
571 .prepare = rcar_du_crtc_mode_prepare,
572 .commit = rcar_du_crtc_mode_commit,
573 .mode_set = rcar_du_crtc_mode_set,
574 .mode_set_base = rcar_du_crtc_mode_set_base,
575 .disable = rcar_du_crtc_disable,
576};
577
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200578static int rcar_du_crtc_page_flip(struct drm_crtc *crtc,
579 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -0700580 struct drm_pending_vblank_event *event,
581 uint32_t page_flip_flags)
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200582{
583 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
584 struct drm_device *dev = rcrtc->crtc.dev;
585 unsigned long flags;
586
587 spin_lock_irqsave(&dev->event_lock, flags);
588 if (rcrtc->event != NULL) {
589 spin_unlock_irqrestore(&dev->event_lock, flags);
590 return -EBUSY;
591 }
592 spin_unlock_irqrestore(&dev->event_lock, flags);
593
Matt Roperf4510a22014-04-01 15:22:40 -0700594 crtc->primary->fb = fb;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200595 rcar_du_crtc_update_base(rcrtc);
596
597 if (event) {
598 event->pipe = rcrtc->index;
599 drm_vblank_get(dev, rcrtc->index);
600 spin_lock_irqsave(&dev->event_lock, flags);
601 rcrtc->event = event;
602 spin_unlock_irqrestore(&dev->event_lock, flags);
603 }
604
605 return 0;
606}
607
608static const struct drm_crtc_funcs crtc_funcs = {
609 .destroy = drm_crtc_cleanup,
610 .set_config = drm_crtc_helper_set_config,
611 .page_flip = rcar_du_crtc_page_flip,
612};
613
Laurent Pinchart17f6b8a2015-02-18 13:42:40 +0200614/* -----------------------------------------------------------------------------
615 * Interrupt Handling
616 */
617
618static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
619{
620 struct rcar_du_crtc *rcrtc = arg;
621 irqreturn_t ret = IRQ_NONE;
622 u32 status;
623
624 status = rcar_du_crtc_read(rcrtc, DSSR);
625 rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
626
627 if (status & DSSR_FRM) {
628 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
629 rcar_du_crtc_finish_page_flip(rcrtc);
630 ret = IRQ_HANDLED;
631 }
632
633 return ret;
634}
635
636/* -----------------------------------------------------------------------------
637 * Initialization
638 */
639
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200640int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200641{
Laurent Pincharta5f0ef52013-06-17 00:29:25 +0200642 static const unsigned int mmio_offsets[] = {
643 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
644 };
645
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200646 struct rcar_du_device *rcdu = rgrp->dev;
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200647 struct platform_device *pdev = to_platform_device(rcdu->dev);
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200648 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
649 struct drm_crtc *crtc = &rcrtc->crtc;
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200650 unsigned int irqflags;
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +0200651 struct clk *clk;
652 char clk_name[9];
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200653 char *name;
654 int irq;
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200655 int ret;
656
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +0200657 /* Get the CRTC clock and the optional external clock. */
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200658 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
659 sprintf(clk_name, "du.%u", index);
660 name = clk_name;
661 } else {
662 name = NULL;
663 }
664
665 rcrtc->clock = devm_clk_get(rcdu->dev, name);
666 if (IS_ERR(rcrtc->clock)) {
667 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
668 return PTR_ERR(rcrtc->clock);
669 }
670
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +0200671 sprintf(clk_name, "dclkin.%u", index);
672 clk = devm_clk_get(rcdu->dev, clk_name);
673 if (!IS_ERR(clk)) {
674 rcrtc->extclock = clk;
675 } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
676 dev_info(rcdu->dev, "can't get external clock %u\n", index);
677 return -EPROBE_DEFER;
678 }
679
Laurent Pinchart36693f32015-02-18 13:21:56 +0200680 init_waitqueue_head(&rcrtc->flip_wait);
681
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200682 rcrtc->group = rgrp;
Laurent Pincharta5f0ef52013-06-17 00:29:25 +0200683 rcrtc->mmio_offset = mmio_offsets[index];
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200684 rcrtc->index = index;
685 rcrtc->dpms = DRM_MODE_DPMS_OFF;
Laurent Pincharta5f0ef52013-06-17 00:29:25 +0200686 rcrtc->plane = &rgrp->planes.planes[index % 2];
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200687
688 rcrtc->plane->crtc = crtc;
689
690 ret = drm_crtc_init(rcdu->ddev, crtc, &crtc_funcs);
691 if (ret < 0)
692 return ret;
693
694 drm_crtc_helper_add(crtc, &crtc_helper_funcs);
695
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200696 /* Register the interrupt handler. */
697 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
698 irq = platform_get_irq(pdev, index);
699 irqflags = 0;
700 } else {
701 irq = platform_get_irq(pdev, 0);
702 irqflags = IRQF_SHARED;
703 }
704
705 if (irq < 0) {
706 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
Julia Lawall6512f5f2014-11-23 14:11:17 +0100707 return irq;
Laurent Pinchartf66ee302013-06-14 14:15:01 +0200708 }
709
710 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
711 dev_name(rcdu->dev), rcrtc);
712 if (ret < 0) {
713 dev_err(rcdu->dev,
714 "failed to register IRQ for CRTC %u\n", index);
715 return ret;
716 }
717
Laurent Pinchart4bf8e192013-06-19 13:54:11 +0200718 return 0;
719}
720
721void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
722{
723 if (enable) {
724 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
725 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
726 } else {
727 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
728 }
729}