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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/m32r/boot/setup.S -- A setup code.
3 *
Hirokazu Takata9b791d42006-01-06 00:18:44 -08004 * Copyright (C) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
5 * Hitoshi Yamamoto, Hayato Fujiwara
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 *
7 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07008
9#include <linux/linkage.h>
10#include <asm/segment.h>
11#include <asm/page.h>
12#include <asm/pgtable.h>
13
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <asm/assembler.h>
15#include <asm/mmu_context.h>
16#include <asm/m32r.h>
17
18/*
19 * References to members of the boot_cpu_data structure.
20 */
21
22#define CPU_PARAMS boot_cpu_data
23#define M32R_MCICAR 0xfffffff0
24#define M32R_MCDCAR 0xfffffff4
25#define M32R_MCCR 0xfffffffc
26#define M32R_BSCR0 0xffffffd2
27
28;BSEL
29#define BSEL0CR0 0x00ef5000
30#define BSEL0CR1 0x00ef5004
31#define BSEL1CR0 0x00ef5100
32#define BSEL1CR1 0x00ef5104
33#define BSEL0CR0_VAL 0x00000000
34#define BSEL0CR1_VAL 0x01200100
35#define BSEL1CR0_VAL 0x01018000
36#define BSEL1CR1_VAL 0x00200001
37
38;SDRAMC
39#define SDRAMC_SDRF0 0x00ef6000
40#define SDRAMC_SDRF1 0x00ef6004
41#define SDRAMC_SDIR0 0x00ef6008
42#define SDRAMC_SDIR1 0x00ef600c
43#define SDRAMC_SD0ADR 0x00ef6020
44#define SDRAMC_SD0ER 0x00ef6024
45#define SDRAMC_SD0TR 0x00ef6028
46#define SDRAMC_SD0MOD 0x00ef602c
47#define SDRAMC_SD1ADR 0x00ef6040
48#define SDRAMC_SD1ER 0x00ef6044
49#define SDRAMC_SD1TR 0x00ef6048
50#define SDRAMC_SD1MOD 0x00ef604c
51#define SDRAM0 0x18000000
52#define SDRAM1 0x1c000000
53
54/*------------------------------------------------------------------------
55 * start up
56 */
57
58/*------------------------------------------------------------------------
59 * Kernel entry
60 */
61 .section .boot, "ax"
62ENTRY(boot)
63
64/* Set cache mode */
65#if defined(CONFIG_CHIP_XNUX2)
66 ldi r0, #-2 ;LDIMM (r0, M32R_MCCR)
67 ldi r1, #0x0101 ; cache on (with invalidation)
68; ldi r1, #0x00 ; cache off
69 sth r1, @r0
70#elif defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_VDEC2) \
71 || defined(CONFIG_CHIP_OPSP)
72 ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
73 ldi r1, #0x73 ; cache on (with invalidation)
74; ldi r1, #0x00 ; cache off
75 st r1, @r0
76#elif defined(CONFIG_CHIP_M32102)
77 ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
78 ldi r1, #0x101 ; cache on (with invalidation)
79; ldi r1, #0x00 ; cache off
80 st r1, @r0
Hirokazu Takata9287d952006-01-06 00:18:41 -080081#elif defined(CONFIG_CHIP_M32104)
Hirokazu Takata9b791d42006-01-06 00:18:44 -080082 ldi r0, #-96 ; DNCR0
83 seth r1, #0x0060 ; from 0x00600000
84 or3 r1, r1, #0x0005 ; size 2MB
85 st r1, @r0
86 seth r1, #0x0100 ; from 0x01000000
87 or3 r1, r1, #0x0003 ; size 16MB
88 st r1, @+r0
89 seth r1, #0x0200 ; from 0x02000000
90 or3 r1, r1, #0x0002 ; size 32MB
91 st r1, @+r0
Hirokazu Takata9287d952006-01-06 00:18:41 -080092 ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
93 ldi r1, #0x703 ; cache on (with invalidation)
94 st r1, @r0
Linus Torvalds1da177e2005-04-16 15:20:36 -070095#else
96#error unknown chip configuration
97#endif
98
99#ifdef CONFIG_SMP
100 ;; if not BSP (CPU#0) goto AP_loop
101 seth r5, #shigh(M32R_CPUID_PORTL)
102 ld r5, @(low(M32R_CPUID_PORTL), r5)
103 bnez r5, AP_loop
104#if !defined(CONFIG_PLAT_USRV)
105 ;; boot AP
106 ld24 r5, #0xeff2f8 ; IPICR7
107 ldi r6, #0x2 ; IPI to CPU1
108 st r6, @r5
109#endif
110#endif
111
112/*
113 * Now, Jump to stext
114 * if with MMU, TLB on.
115 * if with no MMU, only jump.
116 */
117 .global eit_vector
118mmu_on:
119 LDIMM (r13, stext)
120#ifdef CONFIG_MMU
121 bl init_tlb
122 LDIMM (r2, eit_vector) ; set EVB(cr5)
123 mvtc r2, cr5
124 seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher
125 or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower
126 ldi r1, #0x01
127 st r1, @(MATM_offset,r0) ; Set MATM (T bit ON)
128 ld r0, @(MATM_offset,r0) ; Check
129#else
Hirokazu Takata9287d952006-01-06 00:18:41 -0800130#if defined(CONFIG_CHIP_M32700)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 seth r0,#high(M32R_MCDCAR)
132 or3 r0,r0,#low(M32R_MCDCAR)
133 ld24 r1,#0x8080
134 st r1,@r0
Hirokazu Takata9287d952006-01-06 00:18:41 -0800135#elif defined(CONFIG_CHIP_M32104)
136 LDIMM (r2, eit_vector) ; set EVB(cr5)
137 mvtc r2, cr5
138#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139#endif /* CONFIG_MMU */
140 jmp r13
141 nop
142 nop
143
144#ifdef CONFIG_SMP
145/*
146 * AP wait loop
147 */
148ENTRY(AP_loop)
149 ;; disable interrupt
150 clrpsw #0x40
151 ;; reset EVB
152 LDIMM (r4, _AP_RE)
153 seth r5, #high(__PAGE_OFFSET)
154 or3 r5, r5, #low(__PAGE_OFFSET)
155 not r5, r5
156 and r4, r5
157 mvtc r4, cr5
158 ;; disable maskable interrupt
159 seth r4, #high(M32R_ICU_IMASK_PORTL)
160 or3 r4, r4, #low(M32R_ICU_IMASK_PORTL)
161 ldi r5, #0
162 st r5, @r4
163 ld r5, @r4
164 ;; enable only IPI
165 setpsw #0x40
166 ;; LOOOOOOOOOOOOOOP!!!
167 .fillinsn
1682:
169 nop
170 nop
171 bra 2b
172 nop
173 nop
174
175#ifdef CONFIG_CHIP_M32700_TS1
176 .global dcache_dummy
177 .balign 16, 0
178dcache_dummy:
179 .byte 16
180#endif /* CONFIG_CHIP_M32700_TS1 */
181#endif /* CONFIG_SMP */
182
183 .end
184