blob: 374299ea7aded92999b5e54439e43f017806ce4d [file] [log] [blame]
Kevin Hilman8bd22942009-05-28 10:56:16 -07001/*
2 * OMAP2 Power Management Routines
3 *
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
6 *
7 * Written by:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Tony Lindgren
10 * Juha Yrjola
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/suspend.h>
22#include <linux/sched.h>
23#include <linux/proc_fs.h>
24#include <linux/interrupt.h>
25#include <linux/sysfs.h>
26#include <linux/module.h>
27#include <linux/delay.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/time.h>
32#include <linux/gpio.h>
33
34#include <asm/mach/time.h>
35#include <asm/mach/irq.h>
36#include <asm/mach-types.h>
37
38#include <mach/irqs.h>
Tony Lindgrence491cf2009-10-20 09:40:47 -070039#include <plat/clock.h>
40#include <plat/sram.h>
41#include <plat/control.h>
42#include <plat/mux.h>
43#include <plat/dma.h>
44#include <plat/board.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070045
46#include "prm.h"
47#include "prm-regbits-24xx.h"
48#include "cm.h"
49#include "cm-regbits-24xx.h"
50#include "sdrc.h"
51#include "pm.h"
52
Tony Lindgrence491cf2009-10-20 09:40:47 -070053#include <plat/powerdomain.h>
54#include <plat/clockdomain.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070055
56static void (*omap2_sram_idle)(void);
57static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
58 void __iomem *sdrc_power);
59
Paul Walmsley369d5612010-01-26 20:13:01 -070060static struct powerdomain *mpu_pwrdm, *core_pwrdm;
61static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
Kevin Hilman8bd22942009-05-28 10:56:16 -070062
63static struct clk *osc_ck, *emul_ck;
64
65static int omap2_fclks_active(void)
66{
67 u32 f1, f2;
68
69 f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
70 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
Kevin Hilman4af40162009-02-04 10:51:40 -080071
72 /* Ignore UART clocks. These are handled by UART core (serial.c) */
73 f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2);
74 f2 &= ~OMAP24XX_EN_UART3;
75
Kevin Hilman8bd22942009-05-28 10:56:16 -070076 if (f1 | f2)
77 return 1;
78 return 0;
79}
80
Kevin Hilman8bd22942009-05-28 10:56:16 -070081static void omap2_enter_full_retention(void)
82{
83 u32 l;
84 struct timespec ts_preidle, ts_postidle, ts_idle;
85
86 /* There is 1 reference hold for all children of the oscillator
87 * clock, the following will remove it. If no one else uses the
88 * oscillator itself it will be disabled if/when we enter retention
89 * mode.
90 */
91 clk_disable(osc_ck);
92
93 /* Clear old wake-up events */
94 /* REVISIT: These write to reserved bits? */
95 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
96 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
97 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
98
99 /*
100 * Set MPU powerdomain's next power state to RETENTION;
101 * preserve logic state during retention
102 */
103 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
104 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
105
106 /* Workaround to kill USB */
107 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
108 omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
109
110 omap2_gpio_prepare_for_retention();
111
112 if (omap2_pm_debug) {
113 omap2_pm_dump(0, 0, 0);
114 getnstimeofday(&ts_preidle);
115 }
116
117 /* One last check for pending IRQs to avoid extra latency due
118 * to sleeping unnecessarily. */
Jouni Hogander94434532009-02-03 15:49:04 -0800119 if (omap_irq_pending())
Kevin Hilman8bd22942009-05-28 10:56:16 -0700120 goto no_sleep;
121
Kevin Hilman4af40162009-02-04 10:51:40 -0800122 omap_uart_prepare_idle(0);
123 omap_uart_prepare_idle(1);
124 omap_uart_prepare_idle(2);
125
Kevin Hilman8bd22942009-05-28 10:56:16 -0700126 /* Jump to SRAM suspend code */
127 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
128 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
129 OMAP_SDRC_REGADDR(SDRC_POWER));
Kevin Hilman8bd22942009-05-28 10:56:16 -0700130
Kevin Hilman4af40162009-02-04 10:51:40 -0800131 omap_uart_resume_idle(2);
132 omap_uart_resume_idle(1);
133 omap_uart_resume_idle(0);
134
135no_sleep:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700136 if (omap2_pm_debug) {
137 unsigned long long tmp;
138
139 getnstimeofday(&ts_postidle);
140 ts_idle = timespec_sub(ts_postidle, ts_preidle);
141 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
142 omap2_pm_dump(0, 1, tmp);
143 }
144 omap2_gpio_resume_after_retention();
145
146 clk_enable(osc_ck);
147
148 /* clear CORE wake-up events */
149 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
150 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
151
152 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
153 prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
154
155 /* MPU domain wake events */
156 l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
157 if (l & 0x01)
158 prm_write_mod_reg(0x01, OCP_MOD,
159 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
160 if (l & 0x20)
161 prm_write_mod_reg(0x20, OCP_MOD,
162 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
163
164 /* Mask future PRCM-to-MPU interrupts */
165 prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
166}
167
168static int omap2_i2c_active(void)
169{
170 u32 l;
171
172 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
173 return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
174}
175
176static int sti_console_enabled;
177
178static int omap2_allow_mpu_retention(void)
179{
180 u32 l;
181
182 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
183 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
184 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
185 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
186 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
187 return 0;
188 /* Check for UART3. */
189 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
190 if (l & OMAP24XX_EN_UART3)
191 return 0;
192 if (sti_console_enabled)
193 return 0;
194
195 return 1;
196}
197
198static void omap2_enter_mpu_retention(void)
199{
200 int only_idle = 0;
201 struct timespec ts_preidle, ts_postidle, ts_idle;
202
203 /* Putting MPU into the WFI state while a transfer is active
204 * seems to cause the I2C block to timeout. Why? Good question. */
205 if (omap2_i2c_active())
206 return;
207
208 /* The peripherals seem not to be able to wake up the MPU when
209 * it is in retention mode. */
210 if (omap2_allow_mpu_retention()) {
211 /* REVISIT: These write to reserved bits? */
212 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
213 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
214 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
215
216 /* Try to enter MPU retention */
217 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
218 OMAP_LOGICRETSTATE,
Abhijit Pagare37903002010-01-26 20:12:51 -0700219 MPU_MOD, OMAP2_PM_PWSTCTRL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700220 } else {
221 /* Block MPU retention */
222
Abhijit Pagare37903002010-01-26 20:12:51 -0700223 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD,
224 OMAP2_PM_PWSTCTRL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700225 only_idle = 1;
226 }
227
228 if (omap2_pm_debug) {
229 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
230 getnstimeofday(&ts_preidle);
231 }
232
233 omap2_sram_idle();
234
235 if (omap2_pm_debug) {
236 unsigned long long tmp;
237
238 getnstimeofday(&ts_postidle);
239 ts_idle = timespec_sub(ts_postidle, ts_preidle);
240 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
241 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
242 }
243}
244
245static int omap2_can_sleep(void)
246{
247 if (omap2_fclks_active())
248 return 0;
249 if (osc_ck->usecount > 1)
250 return 0;
251 if (omap_dma_running())
252 return 0;
253
254 return 1;
255}
256
257static void omap2_pm_idle(void)
258{
259 local_irq_disable();
260 local_fiq_disable();
261
262 if (!omap2_can_sleep()) {
Jouni Hogander94434532009-02-03 15:49:04 -0800263 if (omap_irq_pending())
Kevin Hilman8bd22942009-05-28 10:56:16 -0700264 goto out;
265 omap2_enter_mpu_retention();
266 goto out;
267 }
268
Jouni Hogander94434532009-02-03 15:49:04 -0800269 if (omap_irq_pending())
Kevin Hilman8bd22942009-05-28 10:56:16 -0700270 goto out;
271
272 omap2_enter_full_retention();
273
274out:
275 local_fiq_enable();
276 local_irq_enable();
277}
278
279static int omap2_pm_prepare(void)
280{
281 /* We cannot sleep in idle until we have resumed */
282 disable_hlt();
283 return 0;
284}
285
286static int omap2_pm_suspend(void)
287{
288 u32 wken_wkup, mir1;
289
290 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
291 prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
292
293 /* Mask GPT1 */
294 mir1 = omap_readl(0x480fe0a4);
295 omap_writel(1 << 5, 0x480fe0ac);
296
Kevin Hilman4af40162009-02-04 10:51:40 -0800297 omap_uart_prepare_suspend();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700298 omap2_enter_full_retention();
299
300 omap_writel(mir1, 0x480fe0a4);
301 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
302
303 return 0;
304}
305
306static int omap2_pm_enter(suspend_state_t state)
307{
308 int ret = 0;
309
310 switch (state) {
311 case PM_SUSPEND_STANDBY:
312 case PM_SUSPEND_MEM:
313 ret = omap2_pm_suspend();
314 break;
315 default:
316 ret = -EINVAL;
317 }
318
319 return ret;
320}
321
322static void omap2_pm_finish(void)
323{
324 enable_hlt();
325}
326
327static struct platform_suspend_ops omap_pm_ops = {
328 .prepare = omap2_pm_prepare,
329 .enter = omap2_pm_enter,
330 .finish = omap2_pm_finish,
331 .valid = suspend_valid_only_mem,
332};
333
Paul Walmsley369d5612010-01-26 20:13:01 -0700334/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
335static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700336{
Paul Walmsley369d5612010-01-26 20:13:01 -0700337 clkdm_clear_all_wkdeps(clkdm);
338 clkdm_clear_all_sleepdeps(clkdm);
339
340 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
341 omap2_clkdm_allow_idle(clkdm);
342 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
343 atomic_read(&clkdm->usecount) == 0)
344 omap2_clkdm_sleep(clkdm);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700345 return 0;
346}
347
348static void __init prcm_setup_regs(void)
349{
350 int i, num_mem_banks;
351 struct powerdomain *pwrdm;
352
353 /* Enable autoidle */
354 prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
355 OMAP2_PRCM_SYSCONFIG_OFFSET);
356
Kevin Hilman8bd22942009-05-28 10:56:16 -0700357 /*
358 * Set CORE powerdomain memory banks to retain their contents
359 * during RETENTION
360 */
361 num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
362 for (i = 0; i < num_mem_banks; i++)
363 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
364
365 /* Set CORE powerdomain's next power state to RETENTION */
366 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
367
368 /*
369 * Set MPU powerdomain's next power state to RETENTION;
370 * preserve logic state during retention
371 */
372 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
373 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
374
375 /* Force-power down DSP, GFX powerdomains */
376
377 pwrdm = clkdm_get_pwrdm(dsp_clkdm);
378 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
379 omap2_clkdm_sleep(dsp_clkdm);
380
381 pwrdm = clkdm_get_pwrdm(gfx_clkdm);
382 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
383 omap2_clkdm_sleep(gfx_clkdm);
384
Paul Walmsley369d5612010-01-26 20:13:01 -0700385 /*
386 * Clear clockdomain wakeup dependencies and enable
387 * hardware-supervised idle for all clkdms
388 */
389 clkdm_for_each(clkdms_setup, NULL);
390 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700391
392 /* Enable clock autoidle for all domains */
393 cm_write_mod_reg(OMAP24XX_AUTO_CAM |
394 OMAP24XX_AUTO_MAILBOXES |
395 OMAP24XX_AUTO_WDT4 |
396 OMAP2420_AUTO_WDT3 |
397 OMAP24XX_AUTO_MSPRO |
398 OMAP2420_AUTO_MMC |
399 OMAP24XX_AUTO_FAC |
400 OMAP2420_AUTO_EAC |
401 OMAP24XX_AUTO_HDQ |
402 OMAP24XX_AUTO_UART2 |
403 OMAP24XX_AUTO_UART1 |
404 OMAP24XX_AUTO_I2C2 |
405 OMAP24XX_AUTO_I2C1 |
406 OMAP24XX_AUTO_MCSPI2 |
407 OMAP24XX_AUTO_MCSPI1 |
408 OMAP24XX_AUTO_MCBSP2 |
409 OMAP24XX_AUTO_MCBSP1 |
410 OMAP24XX_AUTO_GPT12 |
411 OMAP24XX_AUTO_GPT11 |
412 OMAP24XX_AUTO_GPT10 |
413 OMAP24XX_AUTO_GPT9 |
414 OMAP24XX_AUTO_GPT8 |
415 OMAP24XX_AUTO_GPT7 |
416 OMAP24XX_AUTO_GPT6 |
417 OMAP24XX_AUTO_GPT5 |
418 OMAP24XX_AUTO_GPT4 |
419 OMAP24XX_AUTO_GPT3 |
420 OMAP24XX_AUTO_GPT2 |
421 OMAP2420_AUTO_VLYNQ |
422 OMAP24XX_AUTO_DSS,
423 CORE_MOD, CM_AUTOIDLE1);
424 cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
425 OMAP24XX_AUTO_SSI |
426 OMAP24XX_AUTO_USB,
427 CORE_MOD, CM_AUTOIDLE2);
428 cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
429 OMAP24XX_AUTO_GPMC |
430 OMAP24XX_AUTO_SDMA,
431 CORE_MOD, CM_AUTOIDLE3);
432 cm_write_mod_reg(OMAP24XX_AUTO_PKA |
433 OMAP24XX_AUTO_AES |
434 OMAP24XX_AUTO_RNG |
435 OMAP24XX_AUTO_SHA |
436 OMAP24XX_AUTO_DES,
437 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
438
439 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
440
441 /* Put DPLL and both APLLs into autoidle mode */
442 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
443 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
444 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
445 PLL_MOD, CM_AUTOIDLE);
446
447 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
448 OMAP24XX_AUTO_WDT1 |
449 OMAP24XX_AUTO_MPU_WDT |
450 OMAP24XX_AUTO_GPIOS |
451 OMAP24XX_AUTO_32KSYNC |
452 OMAP24XX_AUTO_GPT1,
453 WKUP_MOD, CM_AUTOIDLE);
454
455 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
456 * stabilisation */
457 prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
458 OMAP2_PRCM_CLKSSETUP_OFFSET);
459
460 /* Configure automatic voltage transition */
461 prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
462 OMAP2_PRCM_VOLTSETUP_OFFSET);
463 prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
464 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
465 OMAP24XX_MEMRETCTRL |
466 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
467 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
468 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
469
470 /* Enable wake-up events */
471 prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
472 WKUP_MOD, PM_WKEN);
473}
474
Kevin Hilman7cc515f2009-06-10 09:02:25 -0700475static int __init omap2_pm_init(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700476{
477 u32 l;
478
479 if (!cpu_is_omap24xx())
480 return -ENODEV;
481
482 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
483 l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
484 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
485
Paul Walmsley369d5612010-01-26 20:13:01 -0700486 /* Look up important powerdomains */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700487
488 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
489 if (!mpu_pwrdm)
490 pr_err("PM: mpu_pwrdm not found\n");
491
492 core_pwrdm = pwrdm_lookup("core_pwrdm");
493 if (!core_pwrdm)
494 pr_err("PM: core_pwrdm not found\n");
495
Paul Walmsley369d5612010-01-26 20:13:01 -0700496 /* Look up important clockdomains */
497
498 mpu_clkdm = clkdm_lookup("mpu_clkdm");
499 if (!mpu_clkdm)
500 pr_err("PM: mpu_clkdm not found\n");
501
502 wkup_clkdm = clkdm_lookup("wkup_clkdm");
503 if (!wkup_clkdm)
504 pr_err("PM: wkup_clkdm not found\n");
505
Kevin Hilman8bd22942009-05-28 10:56:16 -0700506 dsp_clkdm = clkdm_lookup("dsp_clkdm");
507 if (!dsp_clkdm)
Paul Walmsley369d5612010-01-26 20:13:01 -0700508 pr_err("PM: dsp_clkdm not found\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700509
510 gfx_clkdm = clkdm_lookup("gfx_clkdm");
511 if (!gfx_clkdm)
512 pr_err("PM: gfx_clkdm not found\n");
513
514
515 osc_ck = clk_get(NULL, "osc_ck");
516 if (IS_ERR(osc_ck)) {
517 printk(KERN_ERR "could not get osc_ck\n");
518 return -ENODEV;
519 }
520
521 if (cpu_is_omap242x()) {
522 emul_ck = clk_get(NULL, "emul_ck");
523 if (IS_ERR(emul_ck)) {
524 printk(KERN_ERR "could not get emul_ck\n");
525 clk_put(osc_ck);
526 return -ENODEV;
527 }
528 }
529
530 prcm_setup_regs();
531
532 /* Hack to prevent MPU retention when STI console is enabled. */
533 {
534 const struct omap_sti_console_config *sti;
535
536 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
537 struct omap_sti_console_config);
538 if (sti != NULL && sti->enable)
539 sti_console_enabled = 1;
540 }
541
542 /*
543 * We copy the assembler sleep/wakeup routines to SRAM.
544 * These routines need to be in SRAM as that's the only
545 * memory the MPU can see when it wakes up.
546 */
547 if (cpu_is_omap24xx()) {
548 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
549 omap24xx_idle_loop_suspend_sz);
550
551 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
552 omap24xx_cpu_suspend_sz);
553 }
554
555 suspend_set_ops(&omap_pm_ops);
556 pm_idle = omap2_pm_idle;
557
558 return 0;
559}
560
561late_initcall(omap2_pm_init);