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Lennert Buytenhek01eb5692008-03-27 14:51:40 -04001/*
2 * arch/arm/plat-orion/irq.c
3 *
4 * Marvell Orion SoC IRQ handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
Andrew Lunn278b45b2012-06-27 13:40:04 +020014#include <linux/irqdomain.h>
Lennert Buytenhek01eb5692008-03-27 14:51:40 -040015#include <linux/io.h>
Andrew Lunn278b45b2012-06-27 13:40:04 +020016#include <linux/of_address.h>
17#include <linux/of_irq.h>
Sebastian Hesselbarthf28d7de2014-01-16 09:10:31 +010018#include <asm/exception.h>
Lennert Buytenhek6f088f12008-08-09 13:44:58 +020019#include <plat/irq.h>
Rob Herringce915742012-08-29 10:16:55 -050020#include <plat/orion-gpio.h>
Sebastian Hesselbarthf28d7de2014-01-16 09:10:31 +010021#include <mach/bridge-regs.h>
22
Lennert Buytenhek01eb5692008-03-27 14:51:40 -040023void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
24{
Thomas Gleixnere59347a2011-04-14 19:17:57 +020025 struct irq_chip_generic *gc;
26 struct irq_chip_type *ct;
Lennert Buytenhek01eb5692008-03-27 14:51:40 -040027
28 /*
29 * Mask all interrupts initially.
30 */
31 writel(0, maskaddr);
32
Thomas Gleixnere59347a2011-04-14 19:17:57 +020033 gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
34 handle_level_irq);
35 ct = gc->chip_types;
36 ct->chip.irq_mask = irq_gc_mask_clr_bit;
37 ct->chip.irq_unmask = irq_gc_mask_set_bit;
38 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
39 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
Lennert Buytenhek01eb5692008-03-27 14:51:40 -040040}