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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Definitions for IBM 750FXGX Eval (Chestnut)
3 *
4 * Author: <source@mvista.com>
5 *
6 * Based on Artesyn Katana code done by Tim Montgomery <timm@artesyncp.com>
7 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
8 * Based on code done by Mark A. Greer <mgreer@mvista.com>
9 *
10 * <2004> (c) MontaVista Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16/*
17 * This is the CPU physical memory map (windows must be at least 1MB and start
18 * on a boundary that is a multiple of the window size):
19 *
20 * Seems on the IBM 750FXGX Eval board, the MV64460 Registers can be in
21 * only 2 places per switch U17 0x14000000 or 0xf1000000 easily - chose to
22 * implement at 0xf1000000 only at this time
23 *
24 * 0xfff00000-0xffffffff - 8 Flash
25 * 0xffe00000-0xffefffff - BOOT SRAM
26 * 0xffd00000-0xffd00004 - CPLD
27 * 0xffc00000-0xffc0000f - UART
28 * 0xffb00000-0xffb07fff - FRAM
29 * 0xff840000-0xffafffff - *** HOLE ***
30 * 0xff800000-0xff83ffff - MV64460 Integrated SRAM
31 * 0xfe000000-0xff8fffff - *** HOLE ***
32 * 0xfc000000-0xfdffffff - 32bit Flash
33 * 0xf1010000-0xfbffffff - *** HOLE ***
34 * 0xf1000000-0xf100ffff - MV64460 Registers
35 */
36
37#ifndef __PPC_PLATFORMS_CHESTNUT_H__
38#define __PPC_PLATFORMS_CHESTNUT_H__
39
40#define CHESTNUT_BOOT_8BIT_BASE 0xfff00000
41#define CHESTNUT_BOOT_8BIT_SIZE_ACTUAL (1024*1024)
42#define CHESTNUT_BOOT_SRAM_BASE 0xffe00000
43#define CHESTNUT_BOOT_SRAM_SIZE_ACTUAL (1024*1024)
44#define CHESTNUT_CPLD_BASE 0xffd00000
45#define CHESTNUT_CPLD_SIZE_ACTUAL 5
46#define CHESTNUT_CPLD_REG3 (CHESTNUT_CPLD_BASE+3)
47#define CHESTNUT_UART_BASE 0xffc00000
48#define CHESTNUT_UART_SIZE_ACTUAL 16
49#define CHESTNUT_FRAM_BASE 0xffb00000
50#define CHESTNUT_FRAM_SIZE_ACTUAL (32*1024)
51#define CHESTNUT_INTERNAL_SRAM_BASE 0xff800000
52#define CHESTNUT_32BIT_BASE 0xfc000000
53#define CHESTNUT_32BIT_SIZE (32*1024*1024)
54
55#define CHESTNUT_BOOT_8BIT_SIZE max(MV64360_WINDOW_SIZE_MIN, \
56 CHESTNUT_BOOT_8BIT_SIZE_ACTUAL)
57#define CHESTNUT_BOOT_SRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
58 CHESTNUT_BOOT_SRAM_SIZE_ACTUAL)
59#define CHESTNUT_CPLD_SIZE max(MV64360_WINDOW_SIZE_MIN, \
60 CHESTNUT_CPLD_SIZE_ACTUAL)
61#define CHESTNUT_UART_SIZE max(MV64360_WINDOW_SIZE_MIN, \
62 CHESTNUT_UART_SIZE_ACTUAL)
63#define CHESTNUT_FRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
64 CHESTNUT_FRAM_SIZE_ACTUAL)
65
66#define CHESTNUT_BUS_SPEED 200000000
67#define CHESTNUT_PIBS_DATABASE 0xf0000 /* from PIBS src code */
68
69#define KATANA_ETH0_PHY_ADDR 12
70#define KATANA_ETH1_PHY_ADDR 11
71#define KATANA_ETH2_PHY_ADDR 4
72
73#define CHESTNUT_ETH_TX_QUEUE_SIZE 800
74#define CHESTNUT_ETH_RX_QUEUE_SIZE 400
75
76/*
77 * PCI windows
78 */
79
80#define CHESTNUT_PCI0_MEM_PROC_ADDR 0x80000000
81#define CHESTNUT_PCI0_MEM_PCI_HI_ADDR 0x00000000
82#define CHESTNUT_PCI0_MEM_PCI_LO_ADDR 0x80000000
83#define CHESTNUT_PCI0_MEM_SIZE 0x10000000
84#define CHESTNUT_PCI0_IO_PROC_ADDR 0xa0000000
85#define CHESTNUT_PCI0_IO_PCI_ADDR 0x00000000
86#define CHESTNUT_PCI0_IO_SIZE 0x01000000
87
88/*
89 * Board-specific IRQ info
90 */
91#define CHESTNUT_PCI_SLOT0_IRQ (64 + 31)
92#define CHESTNUT_PCI_SLOT1_IRQ (64 + 30)
93#define CHESTNUT_PCI_SLOT2_IRQ (64 + 29)
94#define CHESTNUT_PCI_SLOT3_IRQ (64 + 28)
95
96/* serial port definitions */
97#define CHESTNUT_UART0_IO_BASE (CHESTNUT_UART_BASE + 8)
98#define CHESTNUT_UART1_IO_BASE CHESTNUT_UART_BASE
99
100#define UART0_INT (64 + 25)
101#define UART1_INT (64 + 26)
102
103#ifdef CONFIG_SERIAL_MANY_PORTS
104#define RS_TABLE_SIZE 64
105#else
106#define RS_TABLE_SIZE 2
107#endif
108
109/* Rate for the 3.6864 Mhz clock for the onboard serial chip */
110#define BASE_BAUD (3686400 / 16)
111
112#ifdef CONFIG_SERIAL_DETECT_IRQ
113#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
114#else
115#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
116#endif
117
118#define STD_UART_OP(num) \
119 { 0, BASE_BAUD, 0, UART##num##_INT, STD_COM_FLAGS, \
120 iomem_base: (u8 *)CHESTNUT_UART##num##_IO_BASE, \
121 io_type: SERIAL_IO_MEM},
122
123#define SERIAL_PORT_DFNS \
124 STD_UART_OP(0) \
125 STD_UART_OP(1)
126
127#endif /* __PPC_PLATFORMS_CHESTNUT_H__ */