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Thomas Petazzoni9ae6f742012-06-13 19:01:28 +02001/*
2 * Device Tree Include file for Marvell Armada 370 family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * Contains definitions specific to the Armada 370 SoC that are not
15 * common to all Armada SoCs.
16 */
17
18/include/ "armada-370-xp.dtsi"
Gregory CLEMENT74898362013-04-12 16:29:10 +020019/include/ "skeleton.dtsi"
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020020
21/ {
22 model = "Marvell Armada 370 family SoC";
23 compatible = "marvell,armada370", "marvell,armada-370-xp";
24
Thomas Petazzoni397d59f2012-09-19 22:53:01 +020025 aliases {
26 gpio0 = &gpio0;
27 gpio1 = &gpio1;
28 gpio2 = &gpio2;
29 };
30
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020031 soc {
Thomas Petazzoni8eed4812013-05-16 17:55:16 +020032 ranges = <0 0xd0000000 0x0100000 /* internal registers */
33 0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020034 internal-regs {
35 system-controller@18200 {
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020036 compatible = "marvell,armada-370-xp-system-controller";
Gregory CLEMENT82a68262013-04-12 16:29:08 +020037 reg = <0x18200 0x100>;
Thomas Petazzonifa1b21d2012-12-21 15:49:05 +010038 };
39
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020040 L2: l2-cache {
41 compatible = "marvell,aurora-outer-cache";
Gregory CLEMENT489e1382013-05-20 16:13:27 +020042 reg = <0x08000 0x1000>;
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020043 cache-id-part = <0x100>;
44 wt-override;
Thomas Petazzonifa1b21d2012-12-21 15:49:05 +010045 };
Ryan Press879d68a2013-03-26 16:32:31 -070046
Thomas Petazzonibe3cd262013-04-09 23:26:18 +020047 interrupt-controller@20000 {
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020048 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
Ryan Press879d68a2013-03-26 16:32:31 -070049 };
Thomas Petazzoni397d59f2012-09-19 22:53:01 +020050
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020051 pinctrl {
52 compatible = "marvell,mv88f6710-pinctrl";
53 reg = <0x18000 0x38>;
Thomas Petazzoni397d59f2012-09-19 22:53:01 +020054
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020055 sdio_pins1: sdio-pins1 {
56 marvell,pins = "mpp9", "mpp11", "mpp12",
57 "mpp13", "mpp14", "mpp15";
58 marvell,function = "sd0";
59 };
Thomas Petazzoni397d59f2012-09-19 22:53:01 +020060
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020061 sdio_pins2: sdio-pins2 {
62 marvell,pins = "mpp47", "mpp48", "mpp49",
63 "mpp50", "mpp51", "mpp52";
64 marvell,function = "sd0";
65 };
Gregory CLEMENT9d202782012-11-17 15:22:24 +010066
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020067 sdio_pins3: sdio-pins3 {
68 marvell,pins = "mpp48", "mpp49", "mpp50",
69 "mpp51", "mpp52", "mpp53";
70 marvell,function = "sd0";
71 };
Thomas Petazzoni0122eee2012-11-20 16:03:12 +010072 };
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020073
74 gpio0: gpio@18100 {
75 compatible = "marvell,orion-gpio";
76 reg = <0x18100 0x40>;
77 ngpios = <32>;
78 gpio-controller;
79 #gpio-cells = <2>;
80 interrupt-controller;
81 #interrupts-cells = <2>;
82 interrupts = <82>, <83>, <84>, <85>;
Thomas Petazzoni0122eee2012-11-20 16:03:12 +010083 };
Thomas Petazzoni0122eee2012-11-20 16:03:12 +010084
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020085 gpio1: gpio@18140 {
86 compatible = "marvell,orion-gpio";
87 reg = <0x18140 0x40>;
88 ngpios = <32>;
89 gpio-controller;
90 #gpio-cells = <2>;
91 interrupt-controller;
92 #interrupts-cells = <2>;
93 interrupts = <87>, <88>, <89>, <90>;
Thomas Petazzoni0122eee2012-11-20 16:03:12 +010094 };
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020095
96 gpio2: gpio@18180 {
97 compatible = "marvell,orion-gpio";
98 reg = <0x18180 0x40>;
99 ngpios = <2>;
100 gpio-controller;
101 #gpio-cells = <2>;
102 interrupt-controller;
103 #interrupts-cells = <2>;
104 interrupts = <91>;
Thomas Petazzoni0122eee2012-11-20 16:03:12 +0100105 };
Ezequiel Garciab2bb8062013-01-23 12:26:30 -0300106
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200107 coreclk: mvebu-sar@18230 {
108 compatible = "marvell,armada-370-core-clock";
109 reg = <0x18230 0x08>;
110 #clock-cells = <1>;
111 };
Ezequiel Garciab2bb8062013-01-23 12:26:30 -0300112
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200113 gateclk: clock-gating-control@18220 {
114 compatible = "marvell,armada-370-gating-clock";
115 reg = <0x18220 0x4>;
116 clocks = <&coreclk 0>;
117 #clock-cells = <1>;
118 };
Ezequiel Garciab2bb8062013-01-23 12:26:30 -0300119
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200120 xor@60800 {
121 compatible = "marvell,orion-xor";
122 reg = <0x60800 0x100
123 0x60A00 0x100>;
124 status = "okay";
Thomas Petazzonia09a0b72013-04-09 23:06:33 +0200125
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200126 xor00 {
127 interrupts = <51>;
128 dmacap,memcpy;
129 dmacap,xor;
130 };
131 xor01 {
132 interrupts = <52>;
133 dmacap,memcpy;
134 dmacap,xor;
135 dmacap,memset;
136 };
137 };
Thomas Petazzonia09a0b72013-04-09 23:06:33 +0200138
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200139 xor@60900 {
140 compatible = "marvell,orion-xor";
141 reg = <0x60900 0x100
142 0x60b00 0x100>;
143 status = "okay";
Thomas Petazzonia09a0b72013-04-09 23:06:33 +0200144
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200145 xor10 {
146 interrupts = <94>;
147 dmacap,memcpy;
148 dmacap,xor;
149 };
150 xor11 {
151 interrupts = <95>;
152 dmacap,memcpy;
153 dmacap,xor;
154 dmacap,memset;
155 };
156 };
Thomas Petazzonia09a0b72013-04-09 23:06:33 +0200157
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200158 usb@50000 {
159 clocks = <&coreclk 0>;
160 };
Thomas Petazzonia09a0b72013-04-09 23:06:33 +0200161
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200162 usb@51000 {
163 clocks = <&coreclk 0>;
164 };
Thomas Petazzonia09a0b72013-04-09 23:06:33 +0200165
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200166 thermal@18300 {
167 compatible = "marvell,armada370-thermal";
168 reg = <0x18300 0x4
169 0x18304 0x4>;
170 status = "okay";
171 };
Thomas Petazzonia09a0b72013-04-09 23:06:33 +0200172
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200173 pcie-controller {
174 compatible = "marvell,armada-370-pcie";
175 status = "disabled";
Thomas Petazzonia09a0b72013-04-09 23:06:33 +0200176 device_type = "pci";
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200177
Thomas Petazzonia09a0b72013-04-09 23:06:33 +0200178 #address-cells = <3>;
179 #size-cells = <2>;
Thomas Petazzonia09a0b72013-04-09 23:06:33 +0200180
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200181 bus-range = <0x00 0xff>;
182
183 reg = <0x40000 0x2000>, <0x80000 0x2000>;
184
185 reg-names = "pcie0.0", "pcie1.0";
186
187 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
188 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
189 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
190 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
191
192 pcie@1,0 {
193 device_type = "pci";
194 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
195 reg = <0x0800 0 0 0 0>;
196 #address-cells = <3>;
197 #size-cells = <2>;
198 #interrupt-cells = <1>;
199 ranges;
200 interrupt-map-mask = <0 0 0 0>;
201 interrupt-map = <0 0 0 0 &mpic 58>;
202 marvell,pcie-port = <0>;
203 marvell,pcie-lane = <0>;
204 clocks = <&gateclk 5>;
205 status = "disabled";
206 };
207
208 pcie@2,0 {
209 device_type = "pci";
210 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
211 reg = <0x1000 0 0 0 0>;
212 #address-cells = <3>;
213 #size-cells = <2>;
214 #interrupt-cells = <1>;
215 ranges;
216 interrupt-map-mask = <0 0 0 0>;
217 interrupt-map = <0 0 0 0 &mpic 62>;
218 marvell,pcie-port = <1>;
219 marvell,pcie-lane = <0>;
220 clocks = <&gateclk 9>;
221 status = "disabled";
222 };
Thomas Petazzonia09a0b72013-04-09 23:06:33 +0200223 };
224 };
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200225 };
226};