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Thara Gopinathfbc319f2010-12-10 22:51:05 +05301/**
2 * OMAP and TWL PMIC specific intializations.
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated.
5 * Thara Gopinath
6 * Copyright (C) 2009 Texas Instruments Incorporated.
7 * Nishanth Menon
8 * Copyright (C) 2009 Nokia Corporation
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
Thara Gopinath7bc3ed92010-12-10 23:15:16 +053019#include <linux/i2c/twl.h>
Thara Gopinathfbc319f2010-12-10 22:51:05 +053020
Tony Lindgrene4c060d2012-10-05 13:25:59 -070021#include "soc.h"
Paul Walmsleye1d6f472011-02-25 15:54:33 -070022#include "voltage.h"
Thara Gopinathfbc319f2010-12-10 22:51:05 +053023
Nishanth Menondda0aea2011-01-03 12:58:30 -060024#include "pm.h"
25
Thara Gopinathfbc319f2010-12-10 22:51:05 +053026#define OMAP3_SRI2C_SLAVE_ADDR 0x12
27#define OMAP3_VDD_MPU_SR_CONTROL_REG 0x00
28#define OMAP3_VDD_CORE_SR_CONTROL_REG 0x01
29#define OMAP3_VP_CONFIG_ERROROFFSET 0x00
30#define OMAP3_VP_VSTEPMIN_VSTEPMIN 0x1
31#define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04
32#define OMAP3_VP_VLIMITTO_TIMEOUT_US 200
33
Thara Gopinath7bc3ed92010-12-10 23:15:16 +053034#define OMAP4_SRI2C_SLAVE_ADDR 0x12
35#define OMAP4_VDD_MPU_SR_VOLT_REG 0x55
Nishanth Menonee7fbba2011-05-18 00:17:34 -050036#define OMAP4_VDD_MPU_SR_CMD_REG 0x56
Thara Gopinath7bc3ed92010-12-10 23:15:16 +053037#define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B
Nishanth Menonee7fbba2011-05-18 00:17:34 -050038#define OMAP4_VDD_IVA_SR_CMD_REG 0x5C
Thara Gopinath7bc3ed92010-12-10 23:15:16 +053039#define OMAP4_VDD_CORE_SR_VOLT_REG 0x61
Nishanth Menonee7fbba2011-05-18 00:17:34 -050040#define OMAP4_VDD_CORE_SR_CMD_REG 0x62
Thara Gopinath7bc3ed92010-12-10 23:15:16 +053041
42#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
43#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
44#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
45#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
46
Thara Gopinath7bc3ed92010-12-10 23:15:16 +053047static bool is_offset_valid;
48static u8 smps_offset;
Thara Gopinath40713182011-02-15 13:28:58 +053049/*
50 * Flag to ensure Smartreflex bit in TWL
51 * being cleared in board file is not overwritten.
52 */
53static bool __initdata twl_sr_enable_autoinit;
Thara Gopinath7bc3ed92010-12-10 23:15:16 +053054
Thara Gopinath40713182011-02-15 13:28:58 +053055#define TWL4030_DCDC_GLOBAL_CFG 0x06
Thara Gopinath7bc3ed92010-12-10 23:15:16 +053056#define REG_SMPS_OFFSET 0xE0
Thara Gopinath40713182011-02-15 13:28:58 +053057#define SMARTREFLEX_ENABLE BIT(3)
Thara Gopinath7bc3ed92010-12-10 23:15:16 +053058
Nishanth Menonc84ff1c2011-01-03 12:58:29 -060059static unsigned long twl4030_vsel_to_uv(const u8 vsel)
Thara Gopinathfbc319f2010-12-10 22:51:05 +053060{
61 return (((vsel * 125) + 6000)) * 100;
62}
63
Nishanth Menonc84ff1c2011-01-03 12:58:29 -060064static u8 twl4030_uv_to_vsel(unsigned long uv)
Thara Gopinathfbc319f2010-12-10 22:51:05 +053065{
66 return DIV_ROUND_UP(uv - 600000, 12500);
67}
68
Nishanth Menonc84ff1c2011-01-03 12:58:29 -060069static unsigned long twl6030_vsel_to_uv(const u8 vsel)
Thara Gopinath7bc3ed92010-12-10 23:15:16 +053070{
71 /*
72 * In TWL6030 depending on the value of SMPS_OFFSET
73 * efuse register the voltage range supported in
74 * standard mode can be either between 0.6V - 1.3V or
75 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
76 * is programmed to all 0's where as starting from
77 * TWL6030 ES1.1 the efuse is programmed to 1
78 */
79 if (!is_offset_valid) {
80 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
81 REG_SMPS_OFFSET);
82 is_offset_valid = true;
83 }
84
Nishanth Menon2aed5b92011-05-18 00:17:32 -050085 if (!vsel)
86 return 0;
Thara Gopinath7bc3ed92010-12-10 23:15:16 +053087 /*
88 * There is no specific formula for voltage to vsel
89 * conversion above 1.3V. There are special hardcoded
90 * values for voltages above 1.3V. Currently we are
91 * hardcoding only for 1.35 V which is used for 1GH OPP for
92 * OMAP4430.
93 */
94 if (vsel == 0x3A)
95 return 1350000;
96
97 if (smps_offset & 0x8)
Patrick Titiano58e241f2011-05-18 00:17:30 -050098 return ((((vsel - 1) * 1266) + 70900)) * 10;
Thara Gopinath7bc3ed92010-12-10 23:15:16 +053099 else
Patrick Titiano58e241f2011-05-18 00:17:30 -0500100 return ((((vsel - 1) * 1266) + 60770)) * 10;
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530101}
102
Nishanth Menonc84ff1c2011-01-03 12:58:29 -0600103static u8 twl6030_uv_to_vsel(unsigned long uv)
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530104{
105 /*
106 * In TWL6030 depending on the value of SMPS_OFFSET
107 * efuse register the voltage range supported in
108 * standard mode can be either between 0.6V - 1.3V or
109 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
110 * is programmed to all 0's where as starting from
111 * TWL6030 ES1.1 the efuse is programmed to 1
112 */
113 if (!is_offset_valid) {
114 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
115 REG_SMPS_OFFSET);
116 is_offset_valid = true;
117 }
118
Nishanth Menon2aed5b92011-05-18 00:17:32 -0500119 if (!uv)
120 return 0x00;
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530121 /*
122 * There is no specific formula for voltage to vsel
123 * conversion above 1.3V. There are special hardcoded
124 * values for voltages above 1.3V. Currently we are
125 * hardcoding only for 1.35 V which is used for 1GH OPP for
126 * OMAP4430.
127 */
Nishanth Menon36649422011-05-18 00:17:31 -0500128 if (uv > twl6030_vsel_to_uv(0x39)) {
129 if (uv == 1350000)
130 return 0x3A;
131 pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
132 __func__, uv, twl6030_vsel_to_uv(0x39));
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530133 return 0x3A;
Nishanth Menon36649422011-05-18 00:17:31 -0500134 }
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530135
136 if (smps_offset & 0x8)
Patrick Titiano58e241f2011-05-18 00:17:30 -0500137 return DIV_ROUND_UP(uv - 709000, 12660) + 1;
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530138 else
Patrick Titiano58e241f2011-05-18 00:17:30 -0500139 return DIV_ROUND_UP(uv - 607700, 12660) + 1;
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530140}
141
Kevin Hilmance8ebe02011-03-30 11:01:10 -0700142static struct omap_voltdm_pmic omap3_mpu_pmic = {
Thara Gopinathfbc319f2010-12-10 22:51:05 +0530143 .slew_rate = 4000,
144 .step_size = 12500,
Thara Gopinathfbc319f2010-12-10 22:51:05 +0530145 .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
146 .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
147 .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
Tero Kristo5a84dc52012-09-25 19:33:42 +0300148 .vddmin = 600000,
149 .vddmax = 1450000,
Thara Gopinathfbc319f2010-12-10 22:51:05 +0530150 .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
151 .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
Kevin Hilmane74e4402011-03-22 14:12:37 -0700152 .volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG,
Kevin Hilmanf5395482011-03-30 16:36:30 -0700153 .i2c_high_speed = true,
Thara Gopinathfbc319f2010-12-10 22:51:05 +0530154 .vsel_to_uv = twl4030_vsel_to_uv,
155 .uv_to_vsel = twl4030_uv_to_vsel,
156};
157
Kevin Hilmance8ebe02011-03-30 11:01:10 -0700158static struct omap_voltdm_pmic omap3_core_pmic = {
Thara Gopinathfbc319f2010-12-10 22:51:05 +0530159 .slew_rate = 4000,
160 .step_size = 12500,
Thara Gopinathfbc319f2010-12-10 22:51:05 +0530161 .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
162 .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
163 .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
Tero Kristo5a84dc52012-09-25 19:33:42 +0300164 .vddmin = 600000,
165 .vddmax = 1450000,
Thara Gopinathfbc319f2010-12-10 22:51:05 +0530166 .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
167 .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
Kevin Hilmane74e4402011-03-22 14:12:37 -0700168 .volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG,
Kevin Hilmanf5395482011-03-30 16:36:30 -0700169 .i2c_high_speed = true,
Thara Gopinathfbc319f2010-12-10 22:51:05 +0530170 .vsel_to_uv = twl4030_vsel_to_uv,
171 .uv_to_vsel = twl4030_uv_to_vsel,
172};
173
Kevin Hilmance8ebe02011-03-30 11:01:10 -0700174static struct omap_voltdm_pmic omap4_mpu_pmic = {
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530175 .slew_rate = 4000,
Patrick Titiano58e241f2011-05-18 00:17:30 -0500176 .step_size = 12660,
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530177 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
178 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
179 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
Tero Kristo5a84dc52012-09-25 19:33:42 +0300180 .vddmin = 0,
181 .vddmax = 2100000,
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530182 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
183 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
Kevin Hilmane74e4402011-03-22 14:12:37 -0700184 .volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG,
Nishanth Menonee7fbba2011-05-18 00:17:34 -0500185 .cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG,
Kevin Hilmanf5395482011-03-30 16:36:30 -0700186 .i2c_high_speed = true,
Tero Kristo00bd2282012-09-25 19:33:48 +0300187 .i2c_pad_load = 3,
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530188 .vsel_to_uv = twl6030_vsel_to_uv,
189 .uv_to_vsel = twl6030_uv_to_vsel,
190};
191
Kevin Hilmance8ebe02011-03-30 11:01:10 -0700192static struct omap_voltdm_pmic omap4_iva_pmic = {
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530193 .slew_rate = 4000,
Patrick Titiano58e241f2011-05-18 00:17:30 -0500194 .step_size = 12660,
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530195 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
196 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
197 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
Tero Kristo5a84dc52012-09-25 19:33:42 +0300198 .vddmin = 0,
199 .vddmax = 2100000,
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530200 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
201 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
Kevin Hilmane74e4402011-03-22 14:12:37 -0700202 .volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG,
Nishanth Menonee7fbba2011-05-18 00:17:34 -0500203 .cmd_reg_addr = OMAP4_VDD_IVA_SR_CMD_REG,
Kevin Hilmanf5395482011-03-30 16:36:30 -0700204 .i2c_high_speed = true,
Tero Kristo00bd2282012-09-25 19:33:48 +0300205 .i2c_pad_load = 3,
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530206 .vsel_to_uv = twl6030_vsel_to_uv,
207 .uv_to_vsel = twl6030_uv_to_vsel,
208};
209
Kevin Hilmance8ebe02011-03-30 11:01:10 -0700210static struct omap_voltdm_pmic omap4_core_pmic = {
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530211 .slew_rate = 4000,
Patrick Titiano58e241f2011-05-18 00:17:30 -0500212 .step_size = 12660,
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530213 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
214 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
215 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
Tero Kristo5a84dc52012-09-25 19:33:42 +0300216 .vddmin = 0,
217 .vddmax = 2100000,
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530218 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
219 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
Kevin Hilmane74e4402011-03-22 14:12:37 -0700220 .volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG,
Nishanth Menonee7fbba2011-05-18 00:17:34 -0500221 .cmd_reg_addr = OMAP4_VDD_CORE_SR_CMD_REG,
Tero Kristo83b5b552012-09-25 19:33:49 +0300222 .i2c_high_speed = true,
Tero Kristo00bd2282012-09-25 19:33:48 +0300223 .i2c_pad_load = 3,
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530224 .vsel_to_uv = twl6030_vsel_to_uv,
225 .uv_to_vsel = twl6030_uv_to_vsel,
226};
227
228int __init omap4_twl_init(void)
229{
230 struct voltagedomain *voltdm;
231
232 if (!cpu_is_omap44xx())
233 return -ENODEV;
234
Kevin Hilman81a60482011-03-16 14:25:45 -0700235 voltdm = voltdm_lookup("mpu");
Kevin Hilmance8ebe02011-03-30 11:01:10 -0700236 omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530237
Kevin Hilman81a60482011-03-16 14:25:45 -0700238 voltdm = voltdm_lookup("iva");
Kevin Hilmance8ebe02011-03-30 11:01:10 -0700239 omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530240
Kevin Hilman81a60482011-03-16 14:25:45 -0700241 voltdm = voltdm_lookup("core");
Kevin Hilmance8ebe02011-03-30 11:01:10 -0700242 omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
Thara Gopinath7bc3ed92010-12-10 23:15:16 +0530243
244 return 0;
245}
246
Thara Gopinathfbc319f2010-12-10 22:51:05 +0530247int __init omap3_twl_init(void)
248{
249 struct voltagedomain *voltdm;
250
251 if (!cpu_is_omap34xx())
252 return -ENODEV;
253
Thara Gopinath40713182011-02-15 13:28:58 +0530254 /*
255 * The smartreflex bit on twl4030 specifies if the setting of voltage
256 * is done over the I2C_SR path. Since this setting is independent of
257 * the actual usage of smartreflex AVS module, we enable TWL SR bit
258 * by default irrespective of whether smartreflex AVS module is enabled
259 * on the OMAP side or not. This is because without this bit enabled,
260 * the voltage scaling through vp forceupdate/bypass mechanism of
261 * voltage scaling will not function on TWL over I2C_SR.
262 */
263 if (!twl_sr_enable_autoinit)
264 omap3_twl_set_sr_bit(true);
265
Kevin Hilman280a7272011-03-23 11:18:08 -0700266 voltdm = voltdm_lookup("mpu_iva");
Kevin Hilmance8ebe02011-03-30 11:01:10 -0700267 omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
Thara Gopinathfbc319f2010-12-10 22:51:05 +0530268
Kevin Hilman81a60482011-03-16 14:25:45 -0700269 voltdm = voltdm_lookup("core");
Kevin Hilmance8ebe02011-03-30 11:01:10 -0700270 omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
Thara Gopinathfbc319f2010-12-10 22:51:05 +0530271
272 return 0;
273}
Thara Gopinath40713182011-02-15 13:28:58 +0530274
275/**
276 * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
277 * @enable: enable SR mode in twl or not
278 *
279 * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
280 * voltage scaling through OMAP SR works. Else, the smartreflex bit
281 * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
282 * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
283 * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
284 * in those scenarios this bit is to be cleared (enable = false).
285 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300286 * Returns 0 on success, error is returned if I2C read/write fails.
Thara Gopinath40713182011-02-15 13:28:58 +0530287 */
288int __init omap3_twl_set_sr_bit(bool enable)
289{
290 u8 temp;
291 int ret;
292 if (twl_sr_enable_autoinit)
293 pr_warning("%s: unexpected multiple calls\n", __func__);
294
Peter Ujfalusi5f9403d2012-12-16 11:29:59 -0800295 ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
296 TWL4030_DCDC_GLOBAL_CFG);
Thara Gopinath40713182011-02-15 13:28:58 +0530297 if (ret)
298 goto err;
299
300 if (enable)
301 temp |= SMARTREFLEX_ENABLE;
302 else
303 temp &= ~SMARTREFLEX_ENABLE;
304
Peter Ujfalusi5f9403d2012-12-16 11:29:59 -0800305 ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
306 TWL4030_DCDC_GLOBAL_CFG);
Thara Gopinath40713182011-02-15 13:28:58 +0530307 if (!ret) {
308 twl_sr_enable_autoinit = true;
309 return 0;
310 }
311err:
312 pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
313 return ret;
314}