Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-integrator/pci_v3.c |
| 3 | * |
| 4 | * PCI functions for V3 host PCI bridge |
| 5 | * |
| 6 | * Copyright (C) 1999 ARM Limited |
| 7 | * Copyright (C) 2000-2001 Deep Blue Solutions Ltd |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include <linux/kernel.h> |
| 24 | #include <linux/pci.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | #include <linux/ioport.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/spinlock.h> |
| 28 | #include <linux/init.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 29 | #include <linux/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 31 | #include <mach/hardware.h> |
Russell King | a285edc | 2010-01-14 19:59:37 +0000 | [diff] [blame] | 32 | #include <mach/platform.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | #include <asm/irq.h> |
Alexey Dobriyan | d43c36d | 2009-10-07 17:09:06 +0400 | [diff] [blame] | 34 | #include <asm/signal.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #include <asm/system.h> |
| 36 | #include <asm/mach/pci.h> |
Russell King | c6af66b | 2007-05-17 10:16:55 +0100 | [diff] [blame] | 37 | #include <asm/irq_regs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | |
| 39 | #include <asm/hardware/pci_v3.h> |
| 40 | |
| 41 | /* |
| 42 | * The V3 PCI interface chip in Integrator provides several windows from |
| 43 | * local bus memory into the PCI memory areas. Unfortunately, there |
| 44 | * are not really enough windows for our usage, therefore we reuse |
| 45 | * one of the windows for access to PCI configuration space. The |
| 46 | * memory map is as follows: |
| 47 | * |
| 48 | * Local Bus Memory Usage |
| 49 | * |
| 50 | * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable |
| 51 | * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable |
| 52 | * 60000000 - 60FFFFFF PCI IO. 16M |
| 53 | * 61000000 - 61FFFFFF PCI Configuration. 16M |
| 54 | * |
| 55 | * There are three V3 windows, each described by a pair of V3 registers. |
| 56 | * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. |
| 57 | * Base0 and Base1 can be used for any type of PCI memory access. Base2 |
| 58 | * can be used either for PCI I/O or for I20 accesses. By default, uHAL |
| 59 | * uses this only for PCI IO space. |
| 60 | * |
| 61 | * Normally these spaces are mapped using the following base registers: |
| 62 | * |
| 63 | * Usage Local Bus Memory Base/Map registers used |
| 64 | * |
| 65 | * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 |
| 66 | * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 |
| 67 | * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 |
| 68 | * Cfg 61000000 - 61FFFFFF |
| 69 | * |
| 70 | * This means that I20 and PCI configuration space accesses will fail. |
| 71 | * When PCI configuration accesses are needed (via the uHAL PCI |
| 72 | * configuration space primitives) we must remap the spaces as follows: |
| 73 | * |
| 74 | * Usage Local Bus Memory Base/Map registers used |
| 75 | * |
| 76 | * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 |
| 77 | * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 |
| 78 | * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 |
| 79 | * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 |
| 80 | * |
| 81 | * To make this work, the code depends on overlapping windows working. |
| 82 | * The V3 chip translates an address by checking its range within |
| 83 | * each of the BASE/MAP pairs in turn (in ascending register number |
| 84 | * order). It will use the first matching pair. So, for example, |
| 85 | * if the same address is mapped by both LB_BASE0/LB_MAP0 and |
| 86 | * LB_BASE1/LB_MAP1, the V3 will use the translation from |
| 87 | * LB_BASE0/LB_MAP0. |
| 88 | * |
| 89 | * To allow PCI Configuration space access, the code enlarges the |
| 90 | * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes |
| 91 | * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can |
| 92 | * be remapped for use by configuration cycles. |
| 93 | * |
| 94 | * At the end of the PCI Configuration space accesses, |
| 95 | * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window |
| 96 | * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to |
| 97 | * reveal the now restored LB_BASE1/LB_MAP1 window. |
| 98 | * |
| 99 | * NOTE: We do not set up I2O mapping. I suspect that this is only |
| 100 | * for an intelligent (target) device. Using I2O disables most of |
| 101 | * the mappings into PCI memory. |
| 102 | */ |
| 103 | |
| 104 | // V3 access routines |
| 105 | #define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o)) |
| 106 | #define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o))) |
| 107 | |
| 108 | #define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o)) |
| 109 | #define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o))) |
| 110 | |
| 111 | #define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o)) |
| 112 | #define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o))) |
| 113 | |
| 114 | /*============================================================================ |
| 115 | * |
| 116 | * routine: uHALir_PCIMakeConfigAddress() |
| 117 | * |
| 118 | * parameters: bus = which bus |
| 119 | * device = which device |
| 120 | * function = which function |
| 121 | * offset = configuration space register we are interested in |
| 122 | * |
| 123 | * description: this routine will generate a platform dependent config |
| 124 | * address. |
| 125 | * |
| 126 | * calls: none |
| 127 | * |
| 128 | * returns: configuration address to play on the PCI bus |
| 129 | * |
| 130 | * To generate the appropriate PCI configuration cycles in the PCI |
| 131 | * configuration address space, you present the V3 with the following pattern |
| 132 | * (which is very nearly a type 1 (except that the lower two bits are 00 and |
| 133 | * not 01). In order for this mapping to work you need to set up one of |
| 134 | * the local to PCI aperatures to 16Mbytes in length translating to |
| 135 | * PCI configuration space starting at 0x0000.0000. |
| 136 | * |
| 137 | * PCI configuration cycles look like this: |
| 138 | * |
| 139 | * Type 0: |
| 140 | * |
| 141 | * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 |
| 142 | * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 |
| 143 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 144 | * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| |
| 145 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 146 | * |
| 147 | * 31:11 Device select bit. |
| 148 | * 10:8 Function number |
| 149 | * 7:2 Register number |
| 150 | * |
| 151 | * Type 1: |
| 152 | * |
| 153 | * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 |
| 154 | * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 |
| 155 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 156 | * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| |
| 157 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 158 | * |
| 159 | * 31:24 reserved |
| 160 | * 23:16 bus number (8 bits = 128 possible buses) |
| 161 | * 15:11 Device number (5 bits) |
| 162 | * 10:8 function number |
| 163 | * 7:2 register number |
| 164 | * |
| 165 | */ |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 166 | static DEFINE_RAW_SPINLOCK(v3_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | |
| 168 | #define PCI_BUS_NONMEM_START 0x00000000 |
| 169 | #define PCI_BUS_NONMEM_SIZE SZ_256M |
| 170 | |
| 171 | #define PCI_BUS_PREMEM_START PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE |
| 172 | #define PCI_BUS_PREMEM_SIZE SZ_256M |
| 173 | |
| 174 | #if PCI_BUS_NONMEM_START & 0x000fffff |
| 175 | #error PCI_BUS_NONMEM_START must be megabyte aligned |
| 176 | #endif |
| 177 | #if PCI_BUS_PREMEM_START & 0x000fffff |
| 178 | #error PCI_BUS_PREMEM_START must be megabyte aligned |
| 179 | #endif |
| 180 | |
| 181 | #undef V3_LB_BASE_PREFETCH |
| 182 | #define V3_LB_BASE_PREFETCH 0 |
| 183 | |
| 184 | static unsigned long v3_open_config_window(struct pci_bus *bus, |
| 185 | unsigned int devfn, int offset) |
| 186 | { |
| 187 | unsigned int address, mapaddress, busnr; |
| 188 | |
| 189 | busnr = bus->number; |
| 190 | |
| 191 | /* |
| 192 | * Trap out illegal values |
| 193 | */ |
| 194 | if (offset > 255) |
| 195 | BUG(); |
| 196 | if (busnr > 255) |
| 197 | BUG(); |
| 198 | if (devfn > 255) |
| 199 | BUG(); |
| 200 | |
| 201 | if (busnr == 0) { |
| 202 | int slot = PCI_SLOT(devfn); |
| 203 | |
| 204 | /* |
| 205 | * local bus segment so need a type 0 config cycle |
| 206 | * |
| 207 | * build the PCI configuration "address" with one-hot in |
| 208 | * A31-A11 |
| 209 | * |
| 210 | * mapaddress: |
| 211 | * 3:1 = config cycle (101) |
| 212 | * 0 = PCI A1 & A0 are 0 (0) |
| 213 | */ |
| 214 | address = PCI_FUNC(devfn) << 8; |
| 215 | mapaddress = V3_LB_MAP_TYPE_CONFIG; |
| 216 | |
| 217 | if (slot > 12) |
| 218 | /* |
| 219 | * high order bits are handled by the MAP register |
| 220 | */ |
| 221 | mapaddress |= 1 << (slot - 5); |
| 222 | else |
| 223 | /* |
| 224 | * low order bits handled directly in the address |
| 225 | */ |
| 226 | address |= 1 << (slot + 11); |
| 227 | } else { |
| 228 | /* |
| 229 | * not the local bus segment so need a type 1 config cycle |
| 230 | * |
| 231 | * address: |
| 232 | * 23:16 = bus number |
| 233 | * 15:11 = slot number (7:3 of devfn) |
| 234 | * 10:8 = func number (2:0 of devfn) |
| 235 | * |
| 236 | * mapaddress: |
| 237 | * 3:1 = config cycle (101) |
| 238 | * 0 = PCI A1 & A0 from host bus (1) |
| 239 | */ |
| 240 | mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; |
| 241 | address = (busnr << 16) | (devfn << 8); |
| 242 | } |
| 243 | |
| 244 | /* |
| 245 | * Set up base0 to see all 512Mbytes of memory space (not |
| 246 | * prefetchable), this frees up base1 for re-use by |
| 247 | * configuration memory |
| 248 | */ |
| 249 | v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | |
| 250 | V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); |
| 251 | |
| 252 | /* |
| 253 | * Set up base1/map1 to point into configuration space. |
| 254 | */ |
| 255 | v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) | |
| 256 | V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); |
| 257 | v3_writew(V3_LB_MAP1, mapaddress); |
| 258 | |
| 259 | return PCI_CONFIG_VADDR + address + offset; |
| 260 | } |
| 261 | |
| 262 | static void v3_close_config_window(void) |
| 263 | { |
| 264 | /* |
| 265 | * Reassign base1 for use by prefetchable PCI memory |
| 266 | */ |
| 267 | v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | |
| 268 | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | |
| 269 | V3_LB_BASE_ENABLE); |
| 270 | v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | |
| 271 | V3_LB_MAP_TYPE_MEM_MULTIPLE); |
| 272 | |
| 273 | /* |
| 274 | * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) |
| 275 | */ |
| 276 | v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | |
| 277 | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); |
| 278 | } |
| 279 | |
| 280 | static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where, |
| 281 | int size, u32 *val) |
| 282 | { |
| 283 | unsigned long addr; |
| 284 | unsigned long flags; |
| 285 | u32 v; |
| 286 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 287 | raw_spin_lock_irqsave(&v3_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 288 | addr = v3_open_config_window(bus, devfn, where); |
| 289 | |
| 290 | switch (size) { |
| 291 | case 1: |
| 292 | v = __raw_readb(addr); |
| 293 | break; |
| 294 | |
| 295 | case 2: |
| 296 | v = __raw_readw(addr); |
| 297 | break; |
| 298 | |
| 299 | default: |
| 300 | v = __raw_readl(addr); |
| 301 | break; |
| 302 | } |
| 303 | |
| 304 | v3_close_config_window(); |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 305 | raw_spin_unlock_irqrestore(&v3_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 306 | |
| 307 | *val = v; |
| 308 | return PCIBIOS_SUCCESSFUL; |
| 309 | } |
| 310 | |
| 311 | static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, |
| 312 | int size, u32 val) |
| 313 | { |
| 314 | unsigned long addr; |
| 315 | unsigned long flags; |
| 316 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 317 | raw_spin_lock_irqsave(&v3_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 318 | addr = v3_open_config_window(bus, devfn, where); |
| 319 | |
| 320 | switch (size) { |
| 321 | case 1: |
| 322 | __raw_writeb((u8)val, addr); |
| 323 | __raw_readb(addr); |
| 324 | break; |
| 325 | |
| 326 | case 2: |
| 327 | __raw_writew((u16)val, addr); |
| 328 | __raw_readw(addr); |
| 329 | break; |
| 330 | |
| 331 | case 4: |
| 332 | __raw_writel(val, addr); |
| 333 | __raw_readl(addr); |
| 334 | break; |
| 335 | } |
| 336 | |
| 337 | v3_close_config_window(); |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 338 | raw_spin_unlock_irqrestore(&v3_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 339 | |
| 340 | return PCIBIOS_SUCCESSFUL; |
| 341 | } |
| 342 | |
| 343 | static struct pci_ops pci_v3_ops = { |
| 344 | .read = v3_read_config, |
| 345 | .write = v3_write_config, |
| 346 | }; |
| 347 | |
| 348 | static struct resource non_mem = { |
| 349 | .name = "PCI non-prefetchable", |
| 350 | .start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START, |
| 351 | .end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1, |
| 352 | .flags = IORESOURCE_MEM, |
| 353 | }; |
| 354 | |
| 355 | static struct resource pre_mem = { |
| 356 | .name = "PCI prefetchable", |
| 357 | .start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START, |
| 358 | .end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1, |
| 359 | .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, |
| 360 | }; |
| 361 | |
| 362 | static int __init pci_v3_setup_resources(struct resource **resource) |
| 363 | { |
| 364 | if (request_resource(&iomem_resource, &non_mem)) { |
| 365 | printk(KERN_ERR "PCI: unable to allocate non-prefetchable " |
| 366 | "memory region\n"); |
| 367 | return -EBUSY; |
| 368 | } |
| 369 | if (request_resource(&iomem_resource, &pre_mem)) { |
| 370 | release_resource(&non_mem); |
| 371 | printk(KERN_ERR "PCI: unable to allocate prefetchable " |
| 372 | "memory region\n"); |
| 373 | return -EBUSY; |
| 374 | } |
| 375 | |
| 376 | /* |
| 377 | * bus->resource[0] is the IO resource for this bus |
| 378 | * bus->resource[1] is the mem resource for this bus |
| 379 | * bus->resource[2] is the prefetch mem resource for this bus |
| 380 | */ |
| 381 | resource[0] = &ioport_resource; |
| 382 | resource[1] = &non_mem; |
| 383 | resource[2] = &pre_mem; |
| 384 | |
| 385 | return 1; |
| 386 | } |
| 387 | |
| 388 | /* |
| 389 | * These don't seem to be implemented on the Integrator I have, which |
| 390 | * means I can't get additional information on the reason for the pm2fb |
| 391 | * problems. I suppose I'll just have to mind-meld with the machine. ;) |
| 392 | */ |
Russell King | b830b9b | 2010-01-17 20:45:12 +0000 | [diff] [blame] | 393 | #define SC_PCI IO_ADDRESS(INTEGRATOR_SC_PCIENABLE) |
| 394 | #define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20) |
| 395 | #define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 396 | |
| 397 | static int |
| 398 | v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) |
| 399 | { |
| 400 | unsigned long pc = instruction_pointer(regs); |
| 401 | unsigned long instr = *(unsigned long *)pc; |
| 402 | #if 0 |
| 403 | char buf[128]; |
| 404 | |
| 405 | sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n", |
| 406 | addr, fsr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255, |
| 407 | v3_readb(V3_LB_ISTAT)); |
| 408 | printk(KERN_DEBUG "%s", buf); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 409 | #endif |
| 410 | |
| 411 | v3_writeb(V3_LB_ISTAT, 0); |
| 412 | __raw_writel(3, SC_PCI); |
| 413 | |
| 414 | /* |
| 415 | * If the instruction being executed was a read, |
| 416 | * make it look like it read all-ones. |
| 417 | */ |
| 418 | if ((instr & 0x0c100000) == 0x04100000) { |
| 419 | int reg = (instr >> 12) & 15; |
| 420 | unsigned long val; |
| 421 | |
| 422 | if (instr & 0x00400000) |
| 423 | val = 255; |
| 424 | else |
| 425 | val = -1; |
| 426 | |
| 427 | regs->uregs[reg] = val; |
| 428 | regs->ARM_pc += 4; |
| 429 | return 0; |
| 430 | } |
| 431 | |
| 432 | if ((instr & 0x0e100090) == 0x00100090) { |
| 433 | int reg = (instr >> 12) & 15; |
| 434 | |
| 435 | regs->uregs[reg] = -1; |
| 436 | regs->ARM_pc += 4; |
| 437 | return 0; |
| 438 | } |
| 439 | |
| 440 | return 1; |
| 441 | } |
| 442 | |
Jeff Garzik | e8f2af1 | 2007-10-26 05:40:25 -0400 | [diff] [blame] | 443 | static irqreturn_t v3_irq(int dummy, void *devid) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | { |
| 445 | #ifdef CONFIG_DEBUG_LL |
Linus Torvalds | 0cd61b6 | 2006-10-06 10:53:39 -0700 | [diff] [blame] | 446 | struct pt_regs *regs = get_irq_regs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | unsigned long pc = instruction_pointer(regs); |
| 448 | unsigned long instr = *(unsigned long *)pc; |
| 449 | char buf[128]; |
Russell King | 7c28472 | 2008-05-23 19:35:52 +0100 | [diff] [blame] | 450 | extern void printascii(const char *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 451 | |
Jeff Garzik | e8f2af1 | 2007-10-26 05:40:25 -0400 | [diff] [blame] | 452 | sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x " |
| 453 | "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr, |
| 454 | __raw_readl(SC_LBFADDR), |
| 455 | __raw_readl(SC_LBFCODE) & 255, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | v3_readb(V3_LB_ISTAT)); |
| 457 | printascii(buf); |
| 458 | #endif |
| 459 | |
| 460 | v3_writew(V3_PCI_STAT, 0xf000); |
| 461 | v3_writeb(V3_LB_ISTAT, 0); |
| 462 | __raw_writel(3, SC_PCI); |
| 463 | |
| 464 | #ifdef CONFIG_DEBUG_LL |
| 465 | /* |
| 466 | * If the instruction being executed was a read, |
| 467 | * make it look like it read all-ones. |
| 468 | */ |
| 469 | if ((instr & 0x0c100000) == 0x04100000) { |
| 470 | int reg = (instr >> 16) & 15; |
| 471 | sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]); |
| 472 | printascii(buf); |
| 473 | } |
| 474 | #endif |
| 475 | return IRQ_HANDLED; |
| 476 | } |
| 477 | |
| 478 | int __init pci_v3_setup(int nr, struct pci_sys_data *sys) |
| 479 | { |
| 480 | int ret = 0; |
| 481 | |
| 482 | if (nr == 0) { |
| 483 | sys->mem_offset = PHYS_PCI_MEM_BASE; |
| 484 | ret = pci_v3_setup_resources(sys->resource); |
| 485 | } |
| 486 | |
| 487 | return ret; |
| 488 | } |
| 489 | |
Russell King | 7f8b717 | 2009-09-27 16:50:05 +0100 | [diff] [blame] | 490 | struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | { |
| 492 | return pci_scan_bus(sys->busnr, &pci_v3_ops, sys); |
| 493 | } |
| 494 | |
| 495 | /* |
| 496 | * V3_LB_BASE? - local bus address |
| 497 | * V3_LB_MAP? - pci bus address |
| 498 | */ |
| 499 | void __init pci_v3_preinit(void) |
| 500 | { |
| 501 | unsigned long flags; |
| 502 | unsigned int temp; |
| 503 | int ret; |
| 504 | |
Rob Herring | c9d95fb | 2011-06-28 21:16:13 -0500 | [diff] [blame] | 505 | pcibios_min_io = 0x6000; |
| 506 | pcibios_min_mem = 0x00100000; |
| 507 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | /* |
| 509 | * Hook in our fault handler for PCI errors |
| 510 | */ |
Kirill A. Shutemov | 6338a6a | 2010-07-22 13:18:19 +0100 | [diff] [blame] | 511 | hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch"); |
| 512 | hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch"); |
| 513 | hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); |
| 514 | hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 515 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 516 | raw_spin_lock_irqsave(&v3_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 517 | |
| 518 | /* |
| 519 | * Unlock V3 registers, but only if they were previously locked. |
| 520 | */ |
| 521 | if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK) |
| 522 | v3_writew(V3_SYSTEM, 0xa05f); |
| 523 | |
| 524 | /* |
| 525 | * Setup window 0 - PCI non-prefetchable memory |
| 526 | * Local: 0x40000000 Bus: 0x00000000 Size: 256MB |
| 527 | */ |
| 528 | v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | |
| 529 | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); |
| 530 | v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | |
| 531 | V3_LB_MAP_TYPE_MEM); |
| 532 | |
| 533 | /* |
| 534 | * Setup window 1 - PCI prefetchable memory |
| 535 | * Local: 0x50000000 Bus: 0x10000000 Size: 256MB |
| 536 | */ |
| 537 | v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | |
| 538 | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | |
| 539 | V3_LB_BASE_ENABLE); |
| 540 | v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | |
| 541 | V3_LB_MAP_TYPE_MEM_MULTIPLE); |
| 542 | |
| 543 | /* |
| 544 | * Setup window 2 - PCI IO |
| 545 | */ |
| 546 | v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) | |
| 547 | V3_LB_BASE_ENABLE); |
| 548 | v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0)); |
| 549 | |
| 550 | /* |
| 551 | * Disable PCI to host IO cycles |
| 552 | */ |
| 553 | temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN; |
| 554 | temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS; |
| 555 | v3_writew(V3_PCI_CFG, temp); |
| 556 | |
| 557 | printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n", |
| 558 | v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY)); |
| 559 | |
| 560 | /* |
| 561 | * Set the V3 FIFO such that writes have higher priority than |
| 562 | * reads, and local bus write causes local bus read fifo flush. |
| 563 | * Same for PCI. |
| 564 | */ |
| 565 | v3_writew(V3_FIFO_PRIORITY, 0x0a0a); |
| 566 | |
| 567 | /* |
| 568 | * Re-lock the system register. |
| 569 | */ |
| 570 | temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK; |
| 571 | v3_writew(V3_SYSTEM, temp); |
| 572 | |
| 573 | /* |
| 574 | * Clear any error conditions, and enable write errors. |
| 575 | */ |
| 576 | v3_writeb(V3_LB_ISTAT, 0); |
| 577 | v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10)); |
| 578 | v3_writeb(V3_LB_IMASK, 0x28); |
| 579 | __raw_writel(3, SC_PCI); |
| 580 | |
| 581 | /* |
| 582 | * Grab the PCI error interrupt. |
| 583 | */ |
| 584 | ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); |
| 585 | if (ret) |
| 586 | printk(KERN_ERR "PCI: unable to grab PCI error " |
| 587 | "interrupt: %d\n", ret); |
| 588 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 589 | raw_spin_unlock_irqrestore(&v3_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 590 | } |
| 591 | |
| 592 | void __init pci_v3_postinit(void) |
| 593 | { |
| 594 | unsigned int pci_cmd; |
| 595 | |
| 596 | pci_cmd = PCI_COMMAND_MEMORY | |
| 597 | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; |
| 598 | |
| 599 | v3_writew(V3_PCI_CMD, pci_cmd); |
| 600 | |
| 601 | v3_writeb(V3_LB_ISTAT, ~0x40); |
| 602 | v3_writeb(V3_LB_IMASK, 0x68); |
| 603 | |
| 604 | #if 0 |
| 605 | ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL); |
| 606 | if (ret) |
| 607 | printk(KERN_ERR "PCI: unable to grab local bus timeout " |
| 608 | "interrupt: %d\n", ret); |
| 609 | #endif |
Russell King | 863dab4 | 2006-08-28 12:47:05 +0100 | [diff] [blame] | 610 | |
| 611 | register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 612 | } |