Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 1 | /* |
Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * arch/arm/mach-at91/at91sam9261.c |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005 SAN People |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | |
Nicolas Pitre | c9dfafb | 2011-08-02 10:21:36 -0400 | [diff] [blame] | 15 | #include <asm/proc-fns.h> |
Russell King | 80b02c1 | 2009-01-08 10:01:47 +0000 | [diff] [blame] | 16 | #include <asm/irq.h> |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 17 | #include <asm/mach/arch.h> |
| 18 | #include <asm/mach/map.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 19 | #include <asm/system_misc.h> |
Nicolas Ferre | b319ff8 | 2009-06-26 15:37:01 +0100 | [diff] [blame] | 20 | #include <mach/cpu.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 21 | #include <mach/at91sam9261.h> |
Ludovic Desroches | 8fe82a5 | 2012-06-21 14:47:27 +0200 | [diff] [blame] | 22 | #include <mach/at91_aic.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 23 | #include <mach/at91_pmc.h> |
| 24 | #include <mach/at91_rstc.h> |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 25 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 26 | #include "soc.h" |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 27 | #include "generic.h" |
| 28 | #include "clock.h" |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 29 | #include "sam9_smc.h" |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 30 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 31 | /* -------------------------------------------------------------------- |
| 32 | * Clocks |
| 33 | * -------------------------------------------------------------------- */ |
| 34 | |
| 35 | /* |
| 36 | * The peripheral clocks. |
| 37 | */ |
| 38 | static struct clk pioA_clk = { |
| 39 | .name = "pioA_clk", |
| 40 | .pmc_mask = 1 << AT91SAM9261_ID_PIOA, |
| 41 | .type = CLK_TYPE_PERIPHERAL, |
| 42 | }; |
| 43 | static struct clk pioB_clk = { |
| 44 | .name = "pioB_clk", |
| 45 | .pmc_mask = 1 << AT91SAM9261_ID_PIOB, |
| 46 | .type = CLK_TYPE_PERIPHERAL, |
| 47 | }; |
| 48 | static struct clk pioC_clk = { |
| 49 | .name = "pioC_clk", |
| 50 | .pmc_mask = 1 << AT91SAM9261_ID_PIOC, |
| 51 | .type = CLK_TYPE_PERIPHERAL, |
| 52 | }; |
| 53 | static struct clk usart0_clk = { |
| 54 | .name = "usart0_clk", |
| 55 | .pmc_mask = 1 << AT91SAM9261_ID_US0, |
| 56 | .type = CLK_TYPE_PERIPHERAL, |
| 57 | }; |
| 58 | static struct clk usart1_clk = { |
| 59 | .name = "usart1_clk", |
| 60 | .pmc_mask = 1 << AT91SAM9261_ID_US1, |
| 61 | .type = CLK_TYPE_PERIPHERAL, |
| 62 | }; |
| 63 | static struct clk usart2_clk = { |
| 64 | .name = "usart2_clk", |
| 65 | .pmc_mask = 1 << AT91SAM9261_ID_US2, |
| 66 | .type = CLK_TYPE_PERIPHERAL, |
| 67 | }; |
| 68 | static struct clk mmc_clk = { |
| 69 | .name = "mci_clk", |
| 70 | .pmc_mask = 1 << AT91SAM9261_ID_MCI, |
| 71 | .type = CLK_TYPE_PERIPHERAL, |
| 72 | }; |
| 73 | static struct clk udc_clk = { |
| 74 | .name = "udc_clk", |
| 75 | .pmc_mask = 1 << AT91SAM9261_ID_UDP, |
| 76 | .type = CLK_TYPE_PERIPHERAL, |
| 77 | }; |
| 78 | static struct clk twi_clk = { |
| 79 | .name = "twi_clk", |
| 80 | .pmc_mask = 1 << AT91SAM9261_ID_TWI, |
| 81 | .type = CLK_TYPE_PERIPHERAL, |
| 82 | }; |
| 83 | static struct clk spi0_clk = { |
| 84 | .name = "spi0_clk", |
| 85 | .pmc_mask = 1 << AT91SAM9261_ID_SPI0, |
| 86 | .type = CLK_TYPE_PERIPHERAL, |
| 87 | }; |
| 88 | static struct clk spi1_clk = { |
| 89 | .name = "spi1_clk", |
| 90 | .pmc_mask = 1 << AT91SAM9261_ID_SPI1, |
| 91 | .type = CLK_TYPE_PERIPHERAL, |
| 92 | }; |
Andrew Victor | e8788ba | 2007-05-02 17:14:57 +0100 | [diff] [blame] | 93 | static struct clk ssc0_clk = { |
| 94 | .name = "ssc0_clk", |
| 95 | .pmc_mask = 1 << AT91SAM9261_ID_SSC0, |
| 96 | .type = CLK_TYPE_PERIPHERAL, |
| 97 | }; |
| 98 | static struct clk ssc1_clk = { |
| 99 | .name = "ssc1_clk", |
| 100 | .pmc_mask = 1 << AT91SAM9261_ID_SSC1, |
| 101 | .type = CLK_TYPE_PERIPHERAL, |
| 102 | }; |
| 103 | static struct clk ssc2_clk = { |
| 104 | .name = "ssc2_clk", |
| 105 | .pmc_mask = 1 << AT91SAM9261_ID_SSC2, |
| 106 | .type = CLK_TYPE_PERIPHERAL, |
| 107 | }; |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 108 | static struct clk tc0_clk = { |
| 109 | .name = "tc0_clk", |
| 110 | .pmc_mask = 1 << AT91SAM9261_ID_TC0, |
| 111 | .type = CLK_TYPE_PERIPHERAL, |
| 112 | }; |
| 113 | static struct clk tc1_clk = { |
| 114 | .name = "tc1_clk", |
| 115 | .pmc_mask = 1 << AT91SAM9261_ID_TC1, |
| 116 | .type = CLK_TYPE_PERIPHERAL, |
| 117 | }; |
| 118 | static struct clk tc2_clk = { |
| 119 | .name = "tc2_clk", |
| 120 | .pmc_mask = 1 << AT91SAM9261_ID_TC2, |
| 121 | .type = CLK_TYPE_PERIPHERAL, |
| 122 | }; |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 123 | static struct clk ohci_clk = { |
| 124 | .name = "ohci_clk", |
| 125 | .pmc_mask = 1 << AT91SAM9261_ID_UHP, |
| 126 | .type = CLK_TYPE_PERIPHERAL, |
| 127 | }; |
| 128 | static struct clk lcdc_clk = { |
| 129 | .name = "lcdc_clk", |
| 130 | .pmc_mask = 1 << AT91SAM9261_ID_LCDC, |
| 131 | .type = CLK_TYPE_PERIPHERAL, |
| 132 | }; |
| 133 | |
Jean-Christophe PLAGNIOL-VILLARD | 0af4316 | 2011-08-30 03:29:28 +0200 | [diff] [blame] | 134 | /* HClocks */ |
| 135 | static struct clk hck0 = { |
| 136 | .name = "hck0", |
| 137 | .pmc_mask = AT91_PMC_HCK0, |
| 138 | .type = CLK_TYPE_SYSTEM, |
| 139 | .id = 0, |
| 140 | }; |
| 141 | static struct clk hck1 = { |
| 142 | .name = "hck1", |
| 143 | .pmc_mask = AT91_PMC_HCK1, |
| 144 | .type = CLK_TYPE_SYSTEM, |
| 145 | .id = 1, |
| 146 | }; |
| 147 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 148 | static struct clk *periph_clocks[] __initdata = { |
| 149 | &pioA_clk, |
| 150 | &pioB_clk, |
| 151 | &pioC_clk, |
| 152 | &usart0_clk, |
| 153 | &usart1_clk, |
| 154 | &usart2_clk, |
| 155 | &mmc_clk, |
| 156 | &udc_clk, |
| 157 | &twi_clk, |
| 158 | &spi0_clk, |
| 159 | &spi1_clk, |
Andrew Victor | e8788ba | 2007-05-02 17:14:57 +0100 | [diff] [blame] | 160 | &ssc0_clk, |
| 161 | &ssc1_clk, |
| 162 | &ssc2_clk, |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 163 | &tc0_clk, |
| 164 | &tc1_clk, |
| 165 | &tc2_clk, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 166 | &ohci_clk, |
| 167 | &lcdc_clk, |
| 168 | // irq0 .. irq2 |
| 169 | }; |
| 170 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 171 | static struct clk_lookup periph_clocks_lookups[] = { |
| 172 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), |
| 173 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), |
| 174 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), |
| 175 | CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), |
Jean-Christophe PLAGNIOL-VILLARD | c0764b2 | 2011-08-23 16:35:31 +0200 | [diff] [blame] | 176 | CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 177 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), |
| 178 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), |
| 179 | CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 0af4316 | 2011-08-30 03:29:28 +0200 | [diff] [blame] | 180 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0), |
Bo Shen | 302090a | 2012-10-15 17:30:28 +0800 | [diff] [blame] | 181 | CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk), |
| 182 | CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 619d4a4 | 2011-11-13 13:00:58 +0800 | [diff] [blame] | 183 | CLKDEV_CON_ID("pioA", &pioA_clk), |
| 184 | CLKDEV_CON_ID("pioB", &pioB_clk), |
| 185 | CLKDEV_CON_ID("pioC", &pioC_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 186 | }; |
| 187 | |
| 188 | static struct clk_lookup usart_clocks_lookups[] = { |
| 189 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), |
| 190 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), |
| 191 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), |
| 192 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), |
| 193 | }; |
| 194 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 195 | /* |
| 196 | * The four programmable clocks. |
| 197 | * You must configure pin multiplexing to bring these signals out. |
| 198 | */ |
| 199 | static struct clk pck0 = { |
| 200 | .name = "pck0", |
| 201 | .pmc_mask = AT91_PMC_PCK0, |
| 202 | .type = CLK_TYPE_PROGRAMMABLE, |
| 203 | .id = 0, |
| 204 | }; |
| 205 | static struct clk pck1 = { |
| 206 | .name = "pck1", |
| 207 | .pmc_mask = AT91_PMC_PCK1, |
| 208 | .type = CLK_TYPE_PROGRAMMABLE, |
| 209 | .id = 1, |
| 210 | }; |
| 211 | static struct clk pck2 = { |
| 212 | .name = "pck2", |
| 213 | .pmc_mask = AT91_PMC_PCK2, |
| 214 | .type = CLK_TYPE_PROGRAMMABLE, |
| 215 | .id = 2, |
| 216 | }; |
| 217 | static struct clk pck3 = { |
| 218 | .name = "pck3", |
| 219 | .pmc_mask = AT91_PMC_PCK3, |
| 220 | .type = CLK_TYPE_PROGRAMMABLE, |
| 221 | .id = 3, |
| 222 | }; |
| 223 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 224 | static void __init at91sam9261_register_clocks(void) |
| 225 | { |
| 226 | int i; |
| 227 | |
| 228 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) |
| 229 | clk_register(periph_clocks[i]); |
| 230 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 231 | clkdev_add_table(periph_clocks_lookups, |
| 232 | ARRAY_SIZE(periph_clocks_lookups)); |
| 233 | clkdev_add_table(usart_clocks_lookups, |
| 234 | ARRAY_SIZE(usart_clocks_lookups)); |
| 235 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 236 | clk_register(&pck0); |
| 237 | clk_register(&pck1); |
| 238 | clk_register(&pck2); |
| 239 | clk_register(&pck3); |
| 240 | |
| 241 | clk_register(&hck0); |
| 242 | clk_register(&hck1); |
| 243 | } |
| 244 | |
| 245 | /* -------------------------------------------------------------------- |
| 246 | * GPIO |
| 247 | * -------------------------------------------------------------------- */ |
| 248 | |
Jean-Christophe PLAGNIOL-VILLARD | 1a2d915 | 2011-10-17 14:28:38 +0800 | [diff] [blame] | 249 | static struct at91_gpio_bank at91sam9261_gpio[] __initdata = { |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 250 | { |
| 251 | .id = AT91SAM9261_ID_PIOA, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 252 | .regbase = AT91SAM9261_BASE_PIOA, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 253 | }, { |
| 254 | .id = AT91SAM9261_ID_PIOB, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 255 | .regbase = AT91SAM9261_BASE_PIOB, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 256 | }, { |
| 257 | .id = AT91SAM9261_ID_PIOC, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 258 | .regbase = AT91SAM9261_BASE_PIOC, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 259 | } |
| 260 | }; |
| 261 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 262 | /* -------------------------------------------------------------------- |
| 263 | * AT91SAM9261 processor initialization |
| 264 | * -------------------------------------------------------------------- */ |
| 265 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 266 | static void __init at91sam9261_map_io(void) |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 267 | { |
Nicolas Ferre | b319ff8 | 2009-06-26 15:37:01 +0100 | [diff] [blame] | 268 | if (cpu_is_at91sam9g10()) |
Jean-Christophe PLAGNIOL-VILLARD | f0051d8 | 2011-05-10 03:20:09 +0800 | [diff] [blame] | 269 | at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE); |
Nicolas Ferre | b319ff8 | 2009-06-26 15:37:01 +0100 | [diff] [blame] | 270 | else |
Jean-Christophe PLAGNIOL-VILLARD | f0051d8 | 2011-05-10 03:20:09 +0800 | [diff] [blame] | 271 | at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE); |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 272 | } |
Nicolas Ferre | b319ff8 | 2009-06-26 15:37:01 +0100 | [diff] [blame] | 273 | |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 274 | static void __init at91sam9261_ioremap_registers(void) |
| 275 | { |
Jean-Christophe PLAGNIOL-VILLARD | f22deee | 2011-11-01 01:23:20 +0800 | [diff] [blame] | 276 | at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC); |
Jean-Christophe PLAGNIOL-VILLARD | e9f68b5 | 2011-11-18 01:25:52 +0800 | [diff] [blame] | 277 | at91_ioremap_rstc(AT91SAM9261_BASE_RSTC); |
Jean-Christophe PLAGNIOL-VILLARD | f363c40 | 2012-02-13 12:58:53 +0800 | [diff] [blame] | 278 | at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512); |
Jean-Christophe PLAGNIOL-VILLARD | 4ab0c599 | 2011-09-18 22:29:50 +0800 | [diff] [blame] | 279 | at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 280 | at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); |
Jean-Christophe PLAGNIOL-VILLARD | 4342d64 | 2011-11-27 23:15:50 +0800 | [diff] [blame] | 281 | at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX); |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 282 | } |
| 283 | |
Jean-Christophe PLAGNIOL-VILLARD | 4653937 | 2011-04-24 18:20:28 +0800 | [diff] [blame] | 284 | static void __init at91sam9261_initialize(void) |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 285 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0d78171 | 2012-02-05 20:25:32 +0800 | [diff] [blame] | 286 | arm_pm_idle = at91sam9_idle; |
Russell King | 1b2073e | 2011-11-03 09:53:29 +0000 | [diff] [blame] | 287 | arm_pm_restart = at91sam9_alt_restart; |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 288 | at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) |
| 289 | | (1 << AT91SAM9261_ID_IRQ2); |
| 290 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 291 | /* Register GPIO subsystem */ |
| 292 | at91_gpio_init(at91sam9261_gpio, 3); |
| 293 | } |
| 294 | |
| 295 | /* -------------------------------------------------------------------- |
| 296 | * Interrupt initialization |
| 297 | * -------------------------------------------------------------------- */ |
| 298 | |
| 299 | /* |
| 300 | * The default interrupt priority levels (0 = lowest, 7 = highest). |
| 301 | */ |
| 302 | static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { |
| 303 | 7, /* Advanced Interrupt Controller */ |
| 304 | 7, /* System Peripherals */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 305 | 1, /* Parallel IO Controller A */ |
| 306 | 1, /* Parallel IO Controller B */ |
| 307 | 1, /* Parallel IO Controller C */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 308 | 0, |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 309 | 5, /* USART 0 */ |
| 310 | 5, /* USART 1 */ |
| 311 | 5, /* USART 2 */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 312 | 0, /* Multimedia Card Interface */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 313 | 2, /* USB Device Port */ |
| 314 | 6, /* Two-Wire Interface */ |
| 315 | 5, /* Serial Peripheral Interface 0 */ |
| 316 | 5, /* Serial Peripheral Interface 1 */ |
| 317 | 4, /* Serial Synchronous Controller 0 */ |
| 318 | 4, /* Serial Synchronous Controller 1 */ |
| 319 | 4, /* Serial Synchronous Controller 2 */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 320 | 0, /* Timer Counter 0 */ |
| 321 | 0, /* Timer Counter 1 */ |
| 322 | 0, /* Timer Counter 2 */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 323 | 2, /* USB Host port */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 324 | 3, /* LCD Controller */ |
| 325 | 0, |
| 326 | 0, |
| 327 | 0, |
| 328 | 0, |
| 329 | 0, |
| 330 | 0, |
| 331 | 0, |
| 332 | 0, /* Advanced Interrupt Controller */ |
| 333 | 0, /* Advanced Interrupt Controller */ |
| 334 | 0, /* Advanced Interrupt Controller */ |
| 335 | }; |
| 336 | |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 337 | struct at91_init_soc __initdata at91sam9261_soc = { |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 338 | .map_io = at91sam9261_map_io, |
Jean-Christophe PLAGNIOL-VILLARD | 92100c1 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 339 | .default_irq_priority = at91sam9261_default_irq_priority, |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 340 | .ioremap_registers = at91sam9261_ioremap_registers, |
Jean-Christophe PLAGNIOL-VILLARD | 51ddec7 | 2011-04-24 18:15:34 +0800 | [diff] [blame] | 341 | .register_clocks = at91sam9261_register_clocks, |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 342 | .init = at91sam9261_initialize, |
| 343 | }; |