Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-at91/at91sam9rl.c |
| 3 | * |
| 4 | * Copyright (C) 2005 SAN People |
| 5 | * Copyright (C) 2007 Atmel Corporation |
| 6 | * |
| 7 | * This file is subject to the terms and conditions of the GNU General Public |
| 8 | * License. See the file COPYING in the main directory of this archive for |
| 9 | * more details. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/module.h> |
| 13 | |
Nicolas Pitre | c9dfafb | 2011-08-02 10:21:36 -0400 | [diff] [blame] | 14 | #include <asm/proc-fns.h> |
Russell King | 80b02c1 | 2009-01-08 10:01:47 +0000 | [diff] [blame] | 15 | #include <asm/irq.h> |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 16 | #include <asm/mach/arch.h> |
| 17 | #include <asm/mach/map.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 18 | #include <asm/system_misc.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 19 | #include <mach/cpu.h> |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 20 | #include <mach/at91_dbgu.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 21 | #include <mach/at91sam9rl.h> |
Ludovic Desroches | 8fe82a5 | 2012-06-21 14:47:27 +0200 | [diff] [blame] | 22 | #include <mach/at91_aic.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 23 | #include <mach/at91_pmc.h> |
| 24 | #include <mach/at91_rstc.h> |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 25 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 26 | #include "soc.h" |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 27 | #include "generic.h" |
| 28 | #include "clock.h" |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 29 | #include "sam9_smc.h" |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 30 | |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 31 | /* -------------------------------------------------------------------- |
| 32 | * Clocks |
| 33 | * -------------------------------------------------------------------- */ |
| 34 | |
| 35 | /* |
| 36 | * The peripheral clocks. |
| 37 | */ |
| 38 | static struct clk pioA_clk = { |
| 39 | .name = "pioA_clk", |
| 40 | .pmc_mask = 1 << AT91SAM9RL_ID_PIOA, |
| 41 | .type = CLK_TYPE_PERIPHERAL, |
| 42 | }; |
| 43 | static struct clk pioB_clk = { |
| 44 | .name = "pioB_clk", |
| 45 | .pmc_mask = 1 << AT91SAM9RL_ID_PIOB, |
| 46 | .type = CLK_TYPE_PERIPHERAL, |
| 47 | }; |
| 48 | static struct clk pioC_clk = { |
| 49 | .name = "pioC_clk", |
| 50 | .pmc_mask = 1 << AT91SAM9RL_ID_PIOC, |
| 51 | .type = CLK_TYPE_PERIPHERAL, |
| 52 | }; |
| 53 | static struct clk pioD_clk = { |
| 54 | .name = "pioD_clk", |
| 55 | .pmc_mask = 1 << AT91SAM9RL_ID_PIOD, |
| 56 | .type = CLK_TYPE_PERIPHERAL, |
| 57 | }; |
| 58 | static struct clk usart0_clk = { |
| 59 | .name = "usart0_clk", |
| 60 | .pmc_mask = 1 << AT91SAM9RL_ID_US0, |
| 61 | .type = CLK_TYPE_PERIPHERAL, |
| 62 | }; |
| 63 | static struct clk usart1_clk = { |
| 64 | .name = "usart1_clk", |
| 65 | .pmc_mask = 1 << AT91SAM9RL_ID_US1, |
| 66 | .type = CLK_TYPE_PERIPHERAL, |
| 67 | }; |
| 68 | static struct clk usart2_clk = { |
| 69 | .name = "usart2_clk", |
| 70 | .pmc_mask = 1 << AT91SAM9RL_ID_US2, |
| 71 | .type = CLK_TYPE_PERIPHERAL, |
| 72 | }; |
| 73 | static struct clk usart3_clk = { |
| 74 | .name = "usart3_clk", |
| 75 | .pmc_mask = 1 << AT91SAM9RL_ID_US3, |
| 76 | .type = CLK_TYPE_PERIPHERAL, |
| 77 | }; |
| 78 | static struct clk mmc_clk = { |
| 79 | .name = "mci_clk", |
| 80 | .pmc_mask = 1 << AT91SAM9RL_ID_MCI, |
| 81 | .type = CLK_TYPE_PERIPHERAL, |
| 82 | }; |
| 83 | static struct clk twi0_clk = { |
| 84 | .name = "twi0_clk", |
| 85 | .pmc_mask = 1 << AT91SAM9RL_ID_TWI0, |
| 86 | .type = CLK_TYPE_PERIPHERAL, |
| 87 | }; |
| 88 | static struct clk twi1_clk = { |
| 89 | .name = "twi1_clk", |
| 90 | .pmc_mask = 1 << AT91SAM9RL_ID_TWI1, |
| 91 | .type = CLK_TYPE_PERIPHERAL, |
| 92 | }; |
| 93 | static struct clk spi_clk = { |
| 94 | .name = "spi_clk", |
| 95 | .pmc_mask = 1 << AT91SAM9RL_ID_SPI, |
| 96 | .type = CLK_TYPE_PERIPHERAL, |
| 97 | }; |
| 98 | static struct clk ssc0_clk = { |
| 99 | .name = "ssc0_clk", |
| 100 | .pmc_mask = 1 << AT91SAM9RL_ID_SSC0, |
| 101 | .type = CLK_TYPE_PERIPHERAL, |
| 102 | }; |
| 103 | static struct clk ssc1_clk = { |
| 104 | .name = "ssc1_clk", |
| 105 | .pmc_mask = 1 << AT91SAM9RL_ID_SSC1, |
| 106 | .type = CLK_TYPE_PERIPHERAL, |
| 107 | }; |
| 108 | static struct clk tc0_clk = { |
| 109 | .name = "tc0_clk", |
| 110 | .pmc_mask = 1 << AT91SAM9RL_ID_TC0, |
| 111 | .type = CLK_TYPE_PERIPHERAL, |
| 112 | }; |
| 113 | static struct clk tc1_clk = { |
| 114 | .name = "tc1_clk", |
| 115 | .pmc_mask = 1 << AT91SAM9RL_ID_TC1, |
| 116 | .type = CLK_TYPE_PERIPHERAL, |
| 117 | }; |
| 118 | static struct clk tc2_clk = { |
| 119 | .name = "tc2_clk", |
| 120 | .pmc_mask = 1 << AT91SAM9RL_ID_TC2, |
| 121 | .type = CLK_TYPE_PERIPHERAL, |
| 122 | }; |
Andrew Victor | bb1ad68 | 2008-09-18 19:42:37 +0100 | [diff] [blame] | 123 | static struct clk pwm_clk = { |
| 124 | .name = "pwm_clk", |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 125 | .pmc_mask = 1 << AT91SAM9RL_ID_PWMC, |
| 126 | .type = CLK_TYPE_PERIPHERAL, |
| 127 | }; |
| 128 | static struct clk tsc_clk = { |
| 129 | .name = "tsc_clk", |
| 130 | .pmc_mask = 1 << AT91SAM9RL_ID_TSC, |
| 131 | .type = CLK_TYPE_PERIPHERAL, |
| 132 | }; |
| 133 | static struct clk dma_clk = { |
| 134 | .name = "dma_clk", |
| 135 | .pmc_mask = 1 << AT91SAM9RL_ID_DMA, |
| 136 | .type = CLK_TYPE_PERIPHERAL, |
| 137 | }; |
| 138 | static struct clk udphs_clk = { |
| 139 | .name = "udphs_clk", |
| 140 | .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS, |
| 141 | .type = CLK_TYPE_PERIPHERAL, |
| 142 | }; |
| 143 | static struct clk lcdc_clk = { |
| 144 | .name = "lcdc_clk", |
| 145 | .pmc_mask = 1 << AT91SAM9RL_ID_LCDC, |
| 146 | .type = CLK_TYPE_PERIPHERAL, |
| 147 | }; |
| 148 | static struct clk ac97_clk = { |
| 149 | .name = "ac97_clk", |
| 150 | .pmc_mask = 1 << AT91SAM9RL_ID_AC97C, |
| 151 | .type = CLK_TYPE_PERIPHERAL, |
| 152 | }; |
| 153 | |
| 154 | static struct clk *periph_clocks[] __initdata = { |
| 155 | &pioA_clk, |
| 156 | &pioB_clk, |
| 157 | &pioC_clk, |
| 158 | &pioD_clk, |
| 159 | &usart0_clk, |
| 160 | &usart1_clk, |
| 161 | &usart2_clk, |
| 162 | &usart3_clk, |
| 163 | &mmc_clk, |
| 164 | &twi0_clk, |
| 165 | &twi1_clk, |
| 166 | &spi_clk, |
| 167 | &ssc0_clk, |
| 168 | &ssc1_clk, |
| 169 | &tc0_clk, |
| 170 | &tc1_clk, |
| 171 | &tc2_clk, |
Andrew Victor | bb1ad68 | 2008-09-18 19:42:37 +0100 | [diff] [blame] | 172 | &pwm_clk, |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 173 | &tsc_clk, |
| 174 | &dma_clk, |
| 175 | &udphs_clk, |
| 176 | &lcdc_clk, |
| 177 | &ac97_clk, |
| 178 | // irq0 |
| 179 | }; |
| 180 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 181 | static struct clk_lookup periph_clocks_lookups[] = { |
Jean-Christophe PLAGNIOL-VILLARD | 9d87159 | 2011-06-21 14:24:33 +0800 | [diff] [blame] | 182 | CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), |
| 183 | CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 184 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), |
| 185 | CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), |
| 186 | CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), |
| 187 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), |
| 188 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), |
Nikolaus Voss | fac368a | 2011-11-08 11:49:46 +0100 | [diff] [blame] | 189 | CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk), |
| 190 | CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 619d4a4 | 2011-11-13 13:00:58 +0800 | [diff] [blame] | 191 | CLKDEV_CON_ID("pioA", &pioA_clk), |
| 192 | CLKDEV_CON_ID("pioB", &pioB_clk), |
| 193 | CLKDEV_CON_ID("pioC", &pioC_clk), |
| 194 | CLKDEV_CON_ID("pioD", &pioD_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 195 | }; |
| 196 | |
| 197 | static struct clk_lookup usart_clocks_lookups[] = { |
| 198 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), |
| 199 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), |
| 200 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), |
| 201 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), |
| 202 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk), |
| 203 | }; |
| 204 | |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 205 | /* |
| 206 | * The two programmable clocks. |
| 207 | * You must configure pin multiplexing to bring these signals out. |
| 208 | */ |
| 209 | static struct clk pck0 = { |
| 210 | .name = "pck0", |
| 211 | .pmc_mask = AT91_PMC_PCK0, |
| 212 | .type = CLK_TYPE_PROGRAMMABLE, |
| 213 | .id = 0, |
| 214 | }; |
| 215 | static struct clk pck1 = { |
| 216 | .name = "pck1", |
| 217 | .pmc_mask = AT91_PMC_PCK1, |
| 218 | .type = CLK_TYPE_PROGRAMMABLE, |
| 219 | .id = 1, |
| 220 | }; |
| 221 | |
| 222 | static void __init at91sam9rl_register_clocks(void) |
| 223 | { |
| 224 | int i; |
| 225 | |
| 226 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) |
| 227 | clk_register(periph_clocks[i]); |
| 228 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 229 | clkdev_add_table(periph_clocks_lookups, |
| 230 | ARRAY_SIZE(periph_clocks_lookups)); |
| 231 | clkdev_add_table(usart_clocks_lookups, |
| 232 | ARRAY_SIZE(usart_clocks_lookups)); |
| 233 | |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 234 | clk_register(&pck0); |
| 235 | clk_register(&pck1); |
| 236 | } |
| 237 | |
| 238 | /* -------------------------------------------------------------------- |
| 239 | * GPIO |
| 240 | * -------------------------------------------------------------------- */ |
| 241 | |
Jean-Christophe PLAGNIOL-VILLARD | 1a2d915 | 2011-10-17 14:28:38 +0800 | [diff] [blame] | 242 | static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = { |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 243 | { |
| 244 | .id = AT91SAM9RL_ID_PIOA, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 245 | .regbase = AT91SAM9RL_BASE_PIOA, |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 246 | }, { |
| 247 | .id = AT91SAM9RL_ID_PIOB, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 248 | .regbase = AT91SAM9RL_BASE_PIOB, |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 249 | }, { |
| 250 | .id = AT91SAM9RL_ID_PIOC, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 251 | .regbase = AT91SAM9RL_BASE_PIOC, |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 252 | }, { |
| 253 | .id = AT91SAM9RL_ID_PIOD, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 254 | .regbase = AT91SAM9RL_BASE_PIOD, |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 255 | } |
| 256 | }; |
| 257 | |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 258 | /* -------------------------------------------------------------------- |
| 259 | * AT91SAM9RL processor initialization |
| 260 | * -------------------------------------------------------------------- */ |
| 261 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 262 | static void __init at91sam9rl_map_io(void) |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 263 | { |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 264 | unsigned long sram_size; |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 265 | |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 266 | switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) { |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 267 | case AT91_CIDR_SRAMSIZ_32K: |
| 268 | sram_size = 2 * SZ_16K; |
| 269 | break; |
| 270 | case AT91_CIDR_SRAMSIZ_16K: |
| 271 | default: |
| 272 | sram_size = SZ_16K; |
| 273 | } |
| 274 | |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 275 | /* Map SRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | f0051d8 | 2011-05-10 03:20:09 +0800 | [diff] [blame] | 276 | at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size); |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 277 | } |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 278 | |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 279 | static void __init at91sam9rl_ioremap_registers(void) |
| 280 | { |
Jean-Christophe PLAGNIOL-VILLARD | f22deee | 2011-11-01 01:23:20 +0800 | [diff] [blame] | 281 | at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); |
Jean-Christophe PLAGNIOL-VILLARD | e9f68b5 | 2011-11-18 01:25:52 +0800 | [diff] [blame] | 282 | at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC); |
Jean-Christophe PLAGNIOL-VILLARD | f363c40 | 2012-02-13 12:58:53 +0800 | [diff] [blame] | 283 | at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512); |
Jean-Christophe PLAGNIOL-VILLARD | 4ab0c599 | 2011-09-18 22:29:50 +0800 | [diff] [blame] | 284 | at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 285 | at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); |
Jean-Christophe PLAGNIOL-VILLARD | 4342d64 | 2011-11-27 23:15:50 +0800 | [diff] [blame] | 286 | at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX); |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 287 | } |
| 288 | |
Jean-Christophe PLAGNIOL-VILLARD | 4653937 | 2011-04-24 18:20:28 +0800 | [diff] [blame] | 289 | static void __init at91sam9rl_initialize(void) |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 290 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0d78171 | 2012-02-05 20:25:32 +0800 | [diff] [blame] | 291 | arm_pm_idle = at91sam9_idle; |
Russell King | 1b2073e | 2011-11-03 09:53:29 +0000 | [diff] [blame] | 292 | arm_pm_restart = at91sam9_alt_restart; |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 293 | at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); |
| 294 | |
Andrew Victor | 877d772 | 2007-05-11 20:49:56 +0100 | [diff] [blame] | 295 | /* Register GPIO subsystem */ |
| 296 | at91_gpio_init(at91sam9rl_gpio, 4); |
| 297 | } |
| 298 | |
| 299 | /* -------------------------------------------------------------------- |
| 300 | * Interrupt initialization |
| 301 | * -------------------------------------------------------------------- */ |
| 302 | |
| 303 | /* |
| 304 | * The default interrupt priority levels (0 = lowest, 7 = highest). |
| 305 | */ |
| 306 | static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { |
| 307 | 7, /* Advanced Interrupt Controller */ |
| 308 | 7, /* System Peripherals */ |
| 309 | 1, /* Parallel IO Controller A */ |
| 310 | 1, /* Parallel IO Controller B */ |
| 311 | 1, /* Parallel IO Controller C */ |
| 312 | 1, /* Parallel IO Controller D */ |
| 313 | 5, /* USART 0 */ |
| 314 | 5, /* USART 1 */ |
| 315 | 5, /* USART 2 */ |
| 316 | 5, /* USART 3 */ |
| 317 | 0, /* Multimedia Card Interface */ |
| 318 | 6, /* Two-Wire Interface 0 */ |
| 319 | 6, /* Two-Wire Interface 1 */ |
| 320 | 5, /* Serial Peripheral Interface */ |
| 321 | 4, /* Serial Synchronous Controller 0 */ |
| 322 | 4, /* Serial Synchronous Controller 1 */ |
| 323 | 0, /* Timer Counter 0 */ |
| 324 | 0, /* Timer Counter 1 */ |
| 325 | 0, /* Timer Counter 2 */ |
| 326 | 0, |
| 327 | 0, /* Touch Screen Controller */ |
| 328 | 0, /* DMA Controller */ |
| 329 | 2, /* USB Device High speed port */ |
| 330 | 2, /* LCD Controller */ |
| 331 | 6, /* AC97 Controller */ |
| 332 | 0, |
| 333 | 0, |
| 334 | 0, |
| 335 | 0, |
| 336 | 0, |
| 337 | 0, |
| 338 | 0, /* Advanced Interrupt Controller */ |
| 339 | }; |
| 340 | |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 341 | struct at91_init_soc __initdata at91sam9rl_soc = { |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 342 | .map_io = at91sam9rl_map_io, |
Jean-Christophe PLAGNIOL-VILLARD | 92100c1 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 343 | .default_irq_priority = at91sam9rl_default_irq_priority, |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 344 | .ioremap_registers = at91sam9rl_ioremap_registers, |
Jean-Christophe PLAGNIOL-VILLARD | 51ddec7 | 2011-04-24 18:15:34 +0800 | [diff] [blame] | 345 | .register_clocks = at91sam9rl_register_clocks, |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 346 | .init = at91sam9rl_initialize, |
| 347 | }; |