Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 1 | /* |
| 2 | * sound/soc/omap/mcbsp.h |
| 3 | * |
| 4 | * OMAP Multi-Channel Buffered Serial Port |
| 5 | * |
| 6 | * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com> |
| 7 | * Peter Ujfalusi <peter.ujfalusi@ti.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | */ |
| 24 | #ifndef __ASOC_MCBSP_H |
| 25 | #define __ASOC_MCBSP_H |
| 26 | |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 27 | #include "omap-pcm.h" |
| 28 | |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 29 | /* McBSP register numbers. Register address offset = num * reg_step */ |
| 30 | enum { |
| 31 | /* Common registers */ |
| 32 | OMAP_MCBSP_REG_SPCR2 = 4, |
| 33 | OMAP_MCBSP_REG_SPCR1, |
| 34 | OMAP_MCBSP_REG_RCR2, |
| 35 | OMAP_MCBSP_REG_RCR1, |
| 36 | OMAP_MCBSP_REG_XCR2, |
| 37 | OMAP_MCBSP_REG_XCR1, |
| 38 | OMAP_MCBSP_REG_SRGR2, |
| 39 | OMAP_MCBSP_REG_SRGR1, |
| 40 | OMAP_MCBSP_REG_MCR2, |
| 41 | OMAP_MCBSP_REG_MCR1, |
| 42 | OMAP_MCBSP_REG_RCERA, |
| 43 | OMAP_MCBSP_REG_RCERB, |
| 44 | OMAP_MCBSP_REG_XCERA, |
| 45 | OMAP_MCBSP_REG_XCERB, |
| 46 | OMAP_MCBSP_REG_PCR0, |
| 47 | OMAP_MCBSP_REG_RCERC, |
| 48 | OMAP_MCBSP_REG_RCERD, |
| 49 | OMAP_MCBSP_REG_XCERC, |
| 50 | OMAP_MCBSP_REG_XCERD, |
| 51 | OMAP_MCBSP_REG_RCERE, |
| 52 | OMAP_MCBSP_REG_RCERF, |
| 53 | OMAP_MCBSP_REG_XCERE, |
| 54 | OMAP_MCBSP_REG_XCERF, |
| 55 | OMAP_MCBSP_REG_RCERG, |
| 56 | OMAP_MCBSP_REG_RCERH, |
| 57 | OMAP_MCBSP_REG_XCERG, |
| 58 | OMAP_MCBSP_REG_XCERH, |
| 59 | |
| 60 | /* OMAP1-OMAP2420 registers */ |
| 61 | OMAP_MCBSP_REG_DRR2 = 0, |
| 62 | OMAP_MCBSP_REG_DRR1, |
| 63 | OMAP_MCBSP_REG_DXR2, |
| 64 | OMAP_MCBSP_REG_DXR1, |
| 65 | |
| 66 | /* OMAP2430 and onwards */ |
| 67 | OMAP_MCBSP_REG_DRR = 0, |
| 68 | OMAP_MCBSP_REG_DXR = 2, |
| 69 | OMAP_MCBSP_REG_SYSCON = 35, |
| 70 | OMAP_MCBSP_REG_THRSH2, |
| 71 | OMAP_MCBSP_REG_THRSH1, |
| 72 | OMAP_MCBSP_REG_IRQST = 40, |
| 73 | OMAP_MCBSP_REG_IRQEN, |
| 74 | OMAP_MCBSP_REG_WAKEUPEN, |
| 75 | OMAP_MCBSP_REG_XCCR, |
| 76 | OMAP_MCBSP_REG_RCCR, |
| 77 | OMAP_MCBSP_REG_XBUFFSTAT, |
| 78 | OMAP_MCBSP_REG_RBUFFSTAT, |
| 79 | OMAP_MCBSP_REG_SSELCR, |
| 80 | }; |
| 81 | |
| 82 | /* OMAP3 sidetone control registers */ |
| 83 | #define OMAP_ST_REG_REV 0x00 |
| 84 | #define OMAP_ST_REG_SYSCONFIG 0x10 |
| 85 | #define OMAP_ST_REG_IRQSTATUS 0x18 |
| 86 | #define OMAP_ST_REG_IRQENABLE 0x1C |
| 87 | #define OMAP_ST_REG_SGAINCR 0x24 |
| 88 | #define OMAP_ST_REG_SFIRCR 0x28 |
| 89 | #define OMAP_ST_REG_SSELCR 0x2C |
| 90 | |
| 91 | /************************** McBSP SPCR1 bit definitions ***********************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 92 | #define RRST BIT(0) |
| 93 | #define RRDY BIT(1) |
| 94 | #define RFULL BIT(2) |
| 95 | #define RSYNC_ERR BIT(3) |
| 96 | #define RINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */ |
| 97 | #define ABIS BIT(6) |
| 98 | #define DXENA BIT(7) |
| 99 | #define CLKSTP(value) (((value) & 0x3) << 11) /* bits 11:12 */ |
| 100 | #define RJUST(value) (((value) & 0x3) << 13) /* bits 13:14 */ |
| 101 | #define ALB BIT(15) |
| 102 | #define DLB BIT(15) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 103 | |
| 104 | /************************** McBSP SPCR2 bit definitions ***********************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 105 | #define XRST BIT(0) |
| 106 | #define XRDY BIT(1) |
| 107 | #define XEMPTY BIT(2) |
| 108 | #define XSYNC_ERR BIT(3) |
| 109 | #define XINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */ |
| 110 | #define GRST BIT(6) |
| 111 | #define FRST BIT(7) |
| 112 | #define SOFT BIT(8) |
| 113 | #define FREE BIT(9) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 114 | |
| 115 | /************************** McBSP PCR bit definitions *************************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 116 | #define CLKRP BIT(0) |
| 117 | #define CLKXP BIT(1) |
| 118 | #define FSRP BIT(2) |
| 119 | #define FSXP BIT(3) |
| 120 | #define DR_STAT BIT(4) |
| 121 | #define DX_STAT BIT(5) |
| 122 | #define CLKS_STAT BIT(6) |
| 123 | #define SCLKME BIT(7) |
| 124 | #define CLKRM BIT(8) |
| 125 | #define CLKXM BIT(9) |
| 126 | #define FSRM BIT(10) |
| 127 | #define FSXM BIT(11) |
| 128 | #define RIOEN BIT(12) |
| 129 | #define XIOEN BIT(13) |
| 130 | #define IDLE_EN BIT(14) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 131 | |
| 132 | /************************** McBSP RCR1 bit definitions ************************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 133 | #define RWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */ |
| 134 | #define RFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 135 | |
| 136 | /************************** McBSP XCR1 bit definitions ************************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 137 | #define XWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */ |
| 138 | #define XFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 139 | |
| 140 | /*************************** McBSP RCR2 bit definitions ***********************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 141 | #define RDATDLY(value) ((value) & 0x3) /* Bits 0:1 */ |
| 142 | #define RFIG BIT(2) |
| 143 | #define RCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */ |
| 144 | #define RWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */ |
| 145 | #define RFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ |
| 146 | #define RPHASE BIT(15) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 147 | |
| 148 | /*************************** McBSP XCR2 bit definitions ***********************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 149 | #define XDATDLY(value) ((value) & 0x3) /* Bits 0:1 */ |
| 150 | #define XFIG BIT(2) |
| 151 | #define XCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */ |
| 152 | #define XWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */ |
| 153 | #define XFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ |
| 154 | #define XPHASE BIT(15) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 155 | |
| 156 | /************************* McBSP SRGR1 bit definitions ************************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 157 | #define CLKGDV(value) ((value) & 0x7f) /* Bits 0:7 */ |
| 158 | #define FWID(value) (((value) & 0xff) << 8) /* Bits 8:15 */ |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 159 | |
| 160 | /************************* McBSP SRGR2 bit definitions ************************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 161 | #define FPER(value) ((value) & 0x0fff) /* Bits 0:11 */ |
| 162 | #define FSGM BIT(12) |
| 163 | #define CLKSM BIT(13) |
| 164 | #define CLKSP BIT(14) |
| 165 | #define GSYNC BIT(15) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 166 | |
| 167 | /************************* McBSP MCR1 bit definitions *************************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 168 | #define RMCM BIT(0) |
| 169 | #define RCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */ |
| 170 | #define RPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */ |
| 171 | #define RPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */ |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 172 | |
| 173 | /************************* McBSP MCR2 bit definitions *************************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 174 | #define XMCM(value) ((value) & 0x3) /* Bits 0:1 */ |
| 175 | #define XCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */ |
| 176 | #define XPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */ |
| 177 | #define XPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */ |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 178 | |
| 179 | /*********************** McBSP XCCR bit definitions *************************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 180 | #define XDISABLE BIT(0) |
| 181 | #define XDMAEN BIT(3) |
| 182 | #define DILB BIT(5) |
| 183 | #define XFULL_CYCLE BIT(11) |
| 184 | #define DXENDLY(value) (((value) & 0x3) << 12) /* Bits 12:13 */ |
| 185 | #define PPCONNECT BIT(14) |
| 186 | #define EXTCLKGATE BIT(15) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 187 | |
| 188 | /********************** McBSP RCCR bit definitions *************************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 189 | #define RDISABLE BIT(0) |
| 190 | #define RDMAEN BIT(3) |
| 191 | #define RFULL_CYCLE BIT(11) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 192 | |
| 193 | /********************** McBSP SYSCONFIG bit definitions ********************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 194 | #define SOFTRST BIT(1) |
| 195 | #define ENAWAKEUP BIT(2) |
| 196 | #define SIDLEMODE(value) (((value) & 0x3) << 3) |
| 197 | #define CLOCKACTIVITY(value) (((value) & 0x3) << 8) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 198 | |
| 199 | /********************** McBSP SSELCR bit definitions ***********************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 200 | #define SIDETONEEN BIT(10) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 201 | |
| 202 | /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 203 | #define ST_AUTOIDLE BIT(0) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 204 | |
| 205 | /********************** McBSP Sidetone SGAINCR bit definitions *************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 206 | #define ST_CH0GAIN(value) ((value) & 0xffff) /* Bits 0:15 */ |
| 207 | #define ST_CH1GAIN(value) (((value) & 0xffff) << 16) /* Bits 16:31 */ |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 208 | |
| 209 | /********************** McBSP Sidetone SFIRCR bit definitions **************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 210 | #define ST_FIRCOEFF(value) ((value) & 0xffff) /* Bits 0:15 */ |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 211 | |
| 212 | /********************** McBSP Sidetone SSELCR bit definitions **************/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 213 | #define ST_SIDETONEEN BIT(0) |
| 214 | #define ST_COEFFWREN BIT(1) |
| 215 | #define ST_COEFFWRDONE BIT(2) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 216 | |
| 217 | /********************** McBSP DMA operating modes **************************/ |
| 218 | #define MCBSP_DMA_MODE_ELEMENT 0 |
| 219 | #define MCBSP_DMA_MODE_THRESHOLD 1 |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 220 | |
Peter Ujfalusi | 35d210f | 2012-03-19 17:05:39 +0200 | [diff] [blame] | 221 | /********************** McBSP WAKEUPEN/IRQST/IRQEN bit definitions *********/ |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 222 | #define RSYNCERREN BIT(0) |
| 223 | #define RFSREN BIT(1) |
| 224 | #define REOFEN BIT(2) |
| 225 | #define RRDYEN BIT(3) |
Peter Ujfalusi | 35d210f | 2012-03-19 17:05:39 +0200 | [diff] [blame] | 226 | #define RUNDFLEN BIT(4) |
| 227 | #define ROVFLEN BIT(5) |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 228 | #define XSYNCERREN BIT(7) |
| 229 | #define XFSXEN BIT(8) |
| 230 | #define XEOFEN BIT(9) |
| 231 | #define XRDYEN BIT(10) |
Peter Ujfalusi | 35d210f | 2012-03-19 17:05:39 +0200 | [diff] [blame] | 232 | #define XUNDFLEN BIT(11) |
| 233 | #define XOVFLEN BIT(12) |
Peter Ujfalusi | 81da6a9 | 2012-02-13 15:36:49 +0200 | [diff] [blame] | 234 | #define XEMPTYEOFEN BIT(14) |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 235 | |
Peter Ujfalusi | cd1f08c | 2012-03-08 11:01:37 +0200 | [diff] [blame] | 236 | /* Clock signal muxing options */ |
| 237 | #define CLKR_SRC_CLKR 0 /* CLKR signal is from the CLKR pin */ |
| 238 | #define CLKR_SRC_CLKX 1 /* CLKR signal is from the CLKX pin */ |
| 239 | #define FSR_SRC_FSR 2 /* FSR signal is from the FSR pin */ |
| 240 | #define FSR_SRC_FSX 3 /* FSR signal is from the FSX pin */ |
Peter Ujfalusi | 33cec39 | 2012-03-08 10:40:08 +0200 | [diff] [blame] | 241 | |
| 242 | /* McBSP functional clock sources */ |
| 243 | #define MCBSP_CLKS_PRCM_SRC 0 |
| 244 | #define MCBSP_CLKS_PAD_SRC 1 |
| 245 | |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 246 | /* we don't do multichannel for now */ |
| 247 | struct omap_mcbsp_reg_cfg { |
| 248 | u16 spcr2; |
| 249 | u16 spcr1; |
| 250 | u16 rcr2; |
| 251 | u16 rcr1; |
| 252 | u16 xcr2; |
| 253 | u16 xcr1; |
| 254 | u16 srgr2; |
| 255 | u16 srgr1; |
| 256 | u16 mcr2; |
| 257 | u16 mcr1; |
| 258 | u16 pcr0; |
| 259 | u16 rcerc; |
| 260 | u16 rcerd; |
| 261 | u16 xcerc; |
| 262 | u16 xcerd; |
| 263 | u16 rcere; |
| 264 | u16 rcerf; |
| 265 | u16 xcere; |
| 266 | u16 xcerf; |
| 267 | u16 rcerg; |
| 268 | u16 rcerh; |
| 269 | u16 xcerg; |
| 270 | u16 xcerh; |
| 271 | u16 xccr; |
| 272 | u16 rccr; |
| 273 | }; |
| 274 | |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 275 | struct omap_mcbsp_st_data { |
| 276 | void __iomem *io_base_st; |
| 277 | bool running; |
| 278 | bool enabled; |
| 279 | s16 taps[128]; /* Sidetone filter coefficients */ |
| 280 | int nr_taps; /* Number of filter coefficients in use */ |
| 281 | s16 ch0gain; |
| 282 | s16 ch1gain; |
| 283 | }; |
| 284 | |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 285 | struct omap_mcbsp { |
| 286 | struct device *dev; |
Peter Ujfalusi | 256d9c2 | 2012-02-14 15:23:15 +0200 | [diff] [blame] | 287 | struct clk *fclk; |
| 288 | spinlock_t lock; |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 289 | unsigned long phys_base; |
| 290 | unsigned long phys_dma_base; |
| 291 | void __iomem *io_base; |
| 292 | u8 id; |
Peter Ujfalusi | 256d9c2 | 2012-02-14 15:23:15 +0200 | [diff] [blame] | 293 | /* |
| 294 | * Flags indicating is the bus already activated and configured by |
| 295 | * another substream |
| 296 | */ |
| 297 | int active; |
| 298 | int configured; |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 299 | u8 free; |
| 300 | |
Peter Ujfalusi | 35d210f | 2012-03-19 17:05:39 +0200 | [diff] [blame] | 301 | int irq; |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 302 | int rx_irq; |
| 303 | int tx_irq; |
| 304 | |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 305 | /* Protect the field .free, while checking if the mcbsp is in use */ |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 306 | struct omap_mcbsp_platform_data *pdata; |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 307 | struct omap_mcbsp_st_data *st_data; |
Peter Ujfalusi | 256d9c2 | 2012-02-14 15:23:15 +0200 | [diff] [blame] | 308 | struct omap_mcbsp_reg_cfg cfg_regs; |
| 309 | struct omap_pcm_dma_data dma_data[2]; |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 310 | int dma_op_mode; |
| 311 | u16 max_tx_thres; |
| 312 | u16 max_rx_thres; |
| 313 | void *reg_cache; |
| 314 | int reg_cache_size; |
Peter Ujfalusi | 256d9c2 | 2012-02-14 15:23:15 +0200 | [diff] [blame] | 315 | |
| 316 | unsigned int fmt; |
| 317 | unsigned int in_freq; |
| 318 | int clk_div; |
| 319 | int wlen; |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 320 | }; |
| 321 | |
| 322 | void omap_mcbsp_config(struct omap_mcbsp *mcbsp, |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 323 | const struct omap_mcbsp_reg_cfg *config); |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 324 | void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold); |
| 325 | void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold); |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 326 | u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp); |
| 327 | u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp); |
| 328 | int omap_mcbsp_get_dma_op_mode(struct omap_mcbsp *mcbsp); |
| 329 | int omap_mcbsp_request(struct omap_mcbsp *mcbsp); |
| 330 | void omap_mcbsp_free(struct omap_mcbsp *mcbsp); |
| 331 | void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx); |
| 332 | void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx); |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 333 | |
| 334 | /* McBSP functional clock source changing function */ |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 335 | int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id); |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 336 | |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 337 | /* Sidetone specific API */ |
Peter Ujfalusi | 45656b4 | 2012-02-14 18:20:58 +0200 | [diff] [blame] | 338 | int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain); |
| 339 | int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain); |
| 340 | int omap_st_enable(struct omap_mcbsp *mcbsp); |
| 341 | int omap_st_disable(struct omap_mcbsp *mcbsp); |
| 342 | int omap_st_is_enabled(struct omap_mcbsp *mcbsp); |
| 343 | |
Peter Ujfalusi | 2ee6595 | 2012-02-14 14:52:42 +0200 | [diff] [blame] | 344 | int __devinit omap_mcbsp_init(struct platform_device *pdev); |
| 345 | void __devexit omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp); |
Peter Ujfalusi | 219f431 | 2012-02-03 13:11:47 +0200 | [diff] [blame] | 346 | |
| 347 | #endif /* __ASOC_MCBSP_H */ |