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Chris Leechc13c8262006-05-23 17:18:44 -07001#
2# DMA engine configuration
3#
4
Shannon Nelson2ed6dc32007-10-16 01:27:42 -07005menuconfig DMADEVICES
Haavard Skinnemoen6d4f5872007-11-28 16:21:43 -08006 bool "DMA Engine support"
Dan Williams04ce9ab2009-06-03 14:22:28 -07007 depends on HAS_DMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -07008 help
Haavard Skinnemoen6d4f5872007-11-28 16:21:43 -08009 DMA engines can do asynchronous data transfers without
10 involving the host CPU. Currently, this framework can be
11 used to offload memory copies in the network stack and
Dan Williams9c402f42008-06-27 01:21:11 -070012 RAID operations in the MD driver. This menu only presents
13 DMA Device drivers supported by the configured arch, it may
14 be empty in some cases.
Chris Leechc13c8262006-05-23 17:18:44 -070015
Linus Walleij6c664a82010-02-09 22:34:54 +010016config DMADEVICES_DEBUG
17 bool "DMA Engine debugging"
18 depends on DMADEVICES != n
19 help
20 This is an option for use by developers; most people should
21 say N here. This enables DMA engine core and driver debugging.
22
23config DMADEVICES_VDEBUG
24 bool "DMA Engine verbose debugging"
25 depends on DMADEVICES_DEBUG != n
26 help
27 This is an option for use by developers; most people should
28 say N here. This enables deeper (more verbose) debugging of
29 the DMA engine core and drivers.
30
31
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070032if DMADEVICES
Chris Leechdb217332006-06-17 21:24:58 -070033
Chris Leech0bbd5f42006-05-23 17:35:34 -070034comment "DMA Devices"
35
Vinod Koulb3c567e2010-07-21 13:28:10 +053036config INTEL_MID_DMAC
37 tristate "Intel MID DMA support for Peripheral DMA controllers"
38 depends on PCI && X86
39 select DMA_ENGINE
40 default n
41 help
42 Enable support for the Intel(R) MID DMA engine present
43 in Intel MID chipsets.
44
45 Say Y here if you have such a chipset.
46
47 If unsure, say N.
48
Dan Williams5fc6d892010-10-07 16:44:50 -070049config ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williams138f4c32009-09-08 17:42:51 -070050 bool
51
Linus Walleije8689e62010-09-28 15:57:37 +020052config AMBA_PL08X
53 bool "ARM PrimeCell PL080 or PL081 support"
54 depends on ARM_AMBA && EXPERIMENTAL
55 select DMA_ENGINE
56 help
57 Platform has a PL08x DMAC device
58 which can provide DMA engine support
59
Chris Leech0bbd5f42006-05-23 17:35:34 -070060config INTEL_IOATDMA
61 tristate "Intel I/OAT DMA support"
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070062 depends on PCI && X86
63 select DMA_ENGINE
64 select DCA
Dan Williams7b3cc2b2009-11-19 17:10:37 -070065 select ASYNC_TX_DISABLE_PQ_VAL_DMA
66 select ASYNC_TX_DISABLE_XOR_VAL_DMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070067 help
68 Enable support for the Intel(R) I/OAT DMA engine present
69 in recent Intel Xeon chipsets.
70
71 Say Y here if you have such a chipset.
72
73 If unsure, say N.
Dan Williamsc2110922007-01-02 13:52:26 -070074
75config INTEL_IOP_ADMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070076 tristate "Intel IOP ADMA support"
77 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070078 select DMA_ENGINE
Dan Williams5fc6d892010-10-07 16:44:50 -070079 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070080 help
81 Enable support for the Intel(R) IOP Series RAID engines.
Dan Williamsc2110922007-01-02 13:52:26 -070082
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070083config DW_DMAC
84 tristate "Synopsys DesignWare AHB DMA support"
Viresh Kumarf44ad7e2011-03-03 15:47:14 +053085 depends on HAVE_CLK
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070086 select DMA_ENGINE
87 default y if CPU_AT32AP7000
88 help
89 Support the Synopsys DesignWare AHB DMA controller. This
90 can be integrated in chips such as the Atmel AT32ap7000.
91
Nicolas Ferredc78baa2009-07-03 19:24:33 +020092config AT_HDMAC
93 tristate "Atmel AHB DMA support"
Yegor Yefremovcd3abf92009-10-23 11:27:59 +010094 depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
Nicolas Ferredc78baa2009-07-03 19:24:33 +020095 select DMA_ENGINE
96 help
97 Support the Atmel AHB DMA controller. This can be integrated in
98 chips such as the Atmel AT91SAM9RL.
99
Zhang Wei173acc72008-03-01 07:42:48 -0700100config FSL_DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -0700101 tristate "Freescale Elo and Elo Plus DMA support"
102 depends on FSL_SOC
Zhang Wei173acc72008-03-01 07:42:48 -0700103 select DMA_ENGINE
Dan Williams5fc6d892010-10-07 16:44:50 -0700104 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
Zhang Wei173acc72008-03-01 07:42:48 -0700105 ---help---
Timur Tabi77cd62e2008-09-26 17:00:11 -0700106 Enable support for the Freescale Elo and Elo Plus DMA controllers.
107 The Elo is the DMA controller on some 82xx and 83xx parts, and the
108 Elo Plus is the DMA controller on 85xx and 86xx parts.
Zhang Wei173acc72008-03-01 07:42:48 -0700109
Piotr Ziecik0fb6f732010-02-05 03:42:52 +0000110config MPC512X_DMA
111 tristate "Freescale MPC512x built-in DMA engine support"
Ilya Yanokba2eea22010-10-27 01:52:57 +0200112 depends on PPC_MPC512x || PPC_MPC831x
Piotr Ziecik0fb6f732010-02-05 03:42:52 +0000113 select DMA_ENGINE
114 ---help---
115 Enable support for the Freescale MPC512x built-in DMA engine.
116
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700117config MV_XOR
118 bool "Marvell XOR engine support"
119 depends on PLAT_ORION
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700120 select DMA_ENGINE
Dan Williams5fc6d892010-10-07 16:44:50 -0700121 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700122 ---help---
123 Enable support for the Marvell XOR engine.
124
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700125config MX3_IPU
126 bool "MX3x Image Processing Unit support"
127 depends on ARCH_MX3
128 select DMA_ENGINE
129 default y
130 help
131 If you plan to use the Image Processing unit in the i.MX3x, say
132 Y here. If unsure, select Y.
133
134config MX3_IPU_IRQS
135 int "Number of dynamically mapped interrupts for IPU"
136 depends on MX3_IPU
137 range 2 137
138 default 4
139 help
140 Out of 137 interrupt sources on i.MX31 IPU only very few are used.
141 To avoid bloating the irq_desc[] array we allocate a sufficient
142 number of IRQ slots and map them dynamically to specific sources.
143
Atsushi Nemotoea76f0b2009-04-23 00:40:30 +0900144config TXX9_DMAC
145 tristate "Toshiba TXx9 SoC DMA support"
146 depends on MACH_TX49XX || MACH_TX39XX
147 select DMA_ENGINE
148 help
149 Support the TXx9 SoC internal DMA controller. This can be
150 integrated in chips such as the Toshiba TX4927/38/39.
151
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000152config SH_DMAE
153 tristate "Renesas SuperH DMAC support"
Magnus Damm927a7c92010-03-19 04:47:19 +0000154 depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000155 depends on !SH_DMA_API
156 select DMA_ENGINE
157 help
158 Enable support for the Renesas SuperH DMA controllers.
159
Linus Walleij61f135b2009-11-19 19:49:17 +0100160config COH901318
161 bool "ST-Ericsson COH901318 DMA support"
162 select DMA_ENGINE
163 depends on ARCH_U300
164 help
165 Enable support for ST-Ericsson COH 901 318 DMA.
166
Linus Walleij8d318a52010-03-30 15:33:42 +0200167config STE_DMA40
168 bool "ST-Ericsson DMA40 support"
169 depends on ARCH_U8500
170 select DMA_ENGINE
171 help
172 Support for ST-Ericsson DMA40 controller
173
Anatolij Gustschin12458ea2009-12-11 21:24:44 -0700174config AMCC_PPC440SPE_ADMA
175 tristate "AMCC PPC440SPe ADMA support"
176 depends on 440SPe || 440SP
177 select DMA_ENGINE
178 select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
Dan Williams5fc6d892010-10-07 16:44:50 -0700179 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
Anatolij Gustschin12458ea2009-12-11 21:24:44 -0700180 help
181 Enable support for the AMCC PPC440SPe RAID engines.
182
Richard Röjforsde5d4452010-03-25 19:44:21 +0100183config TIMB_DMA
184 tristate "Timberdale FPGA DMA support"
185 depends on MFD_TIMBERDALE || HAS_IOMEM
186 select DMA_ENGINE
187 help
188 Enable support for the Timberdale FPGA DMA engine.
189
Anatolij Gustschin12458ea2009-12-11 21:24:44 -0700190config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
191 bool
192
Jassi Brarb3040e42010-05-23 20:28:19 -0700193config PL330_DMA
194 tristate "DMA API Driver for PL330"
195 select DMA_ENGINE
196 depends on PL330
197 help
198 Select if your platform has one or more PL330 DMACs.
199 You need to provide platform specific settings via
200 platform_data for a dma-pl330 device.
201
Yong Wang0c42bd02010-07-30 16:23:03 +0800202config PCH_DMA
Tomoya MORINAGA2cdf2452011-01-05 17:43:52 +0900203 tristate "Intel EG20T PCH / OKI SEMICONDUCTOR ML7213 IOH DMA support"
Yong Wang0c42bd02010-07-30 16:23:03 +0800204 depends on PCI && X86
205 select DMA_ENGINE
206 help
Tomoya MORINAGA2cdf2452011-01-05 17:43:52 +0900207 Enable support for Intel EG20T PCH DMA engine.
208
209 This driver also can be used for OKI SEMICONDUCTOR ML7213 IOH(Input/
210 Output Hub) which is for IVI(In-Vehicle Infotainment) use.
211 ML7213 is companion chip for Intel Atom E6xx series.
212 ML7213 is completely compatible for Intel EG20T PCH.
Yong Wang0c42bd02010-07-30 16:23:03 +0800213
Sascha Hauer1ec1e822010-09-30 13:56:34 +0000214config IMX_SDMA
215 tristate "i.MX SDMA support"
216 depends on ARCH_MX25 || ARCH_MX3 || ARCH_MX5
217 select DMA_ENGINE
218 help
219 Support the i.MX SDMA engine. This engine is integrated into
220 Freescale i.MX25/31/35/51 chips.
221
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200222config IMX_DMA
223 tristate "i.MX DMA support"
Uwe Kleine-König5b9a4f92011-03-22 10:35:17 +0100224 depends on IMX_HAVE_DMA_V1
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200225 select DMA_ENGINE
226 help
227 Support the i.MX DMA engine. This engine is integrated into
228 Freescale i.MX1/21/27 chips.
229
Shawn Guoa580b8c2011-02-27 00:47:42 +0800230config MXS_DMA
231 bool "MXS DMA support"
232 depends on SOC_IMX23 || SOC_IMX28
233 select DMA_ENGINE
234 help
235 Support the MXS DMA engine. This engine including APBH-DMA
236 and APBX-DMA is integrated into Freescale i.MX23/28 chips.
237
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700238config DMA_ENGINE
239 bool
240
241comment "DMA Clients"
242 depends on DMA_ENGINE
243
244config NET_DMA
245 bool "Network: TCP receive copy offload"
246 depends on DMA_ENGINE && NET
Dan Williams9c402f42008-06-27 01:21:11 -0700247 default (INTEL_IOATDMA || FSL_DMA)
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700248 help
249 This enables the use of DMA engines in the network stack to
250 offload receive copy-to-user operations, freeing CPU cycles.
Dan Williams9c402f42008-06-27 01:21:11 -0700251
252 Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
253 say N.
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700254
Dan Williams729b5d12009-03-25 09:13:25 -0700255config ASYNC_TX_DMA
256 bool "Async_tx: Offload support for the async_tx api"
Dan Williams9a8de632009-09-08 15:06:10 -0700257 depends on DMA_ENGINE
Dan Williams729b5d12009-03-25 09:13:25 -0700258 help
259 This allows the async_tx api to take advantage of offload engines for
260 memcpy, memset, xor, and raid6 p+q operations. If your platform has
261 a dma engine that can perform raid operations and you have enabled
262 MD_RAID456 say Y.
263
264 If unsure, say N.
265
Haavard Skinnemoen4a776f02008-07-08 11:58:45 -0700266config DMATEST
267 tristate "DMA Test client"
268 depends on DMA_ENGINE
269 help
270 Simple DMA test client. Say N unless you're debugging a
271 DMA Device driver.
272
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700273endif