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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04002 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
Alan Coxab771632008-10-27 15:09:10 +000017 * Copyright (C) 2003 Red Hat Inc
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040018 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
Alan Coxd96212e2005-12-08 19:19:50 +000040 * Documentation
Lucas De Marchi25985ed2011-03-30 22:57:33 -030041 * Publicly available from Intel web site. Errata documentation
42 * is also publicly available. As an aide to anyone hacking on this
Alan2c5ff672006-12-04 16:33:20 +000043 * driver the list of errata that are relevant is below, going back to
Alan Coxd96212e2005-12-08 19:19:50 +000044 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
Thomas Weber88393162010-03-16 11:47:56 +010046 * The chipsets all follow very much the same design. The original Triton
Lucas De Marchi25985ed2011-03-30 22:57:33 -030047 * series chipsets do _not_ support independent device timings, but this
Alan Coxd96212e2005-12-08 19:19:50 +000048 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
Lucas De Marchi25985ed2011-03-30 22:57:33 -030050 * driver supports only the chips with independent timing (that is those
Alan Coxd96212e2005-12-08 19:19:50 +000051 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
Alan Coxc611bed2009-05-06 17:08:44 +010075 * ICH7 errata #16 - MWDMA1 timings are incorrect
Alan Coxd96212e2005-12-08 19:19:50 +000076 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 */
85
86#include <linux/kernel.h>
87#include <linux/module.h>
88#include <linux/pci.h>
89#include <linux/init.h>
90#include <linux/blkdev.h>
91#include <linux/delay.h>
Jeff Garzik6248e642005-10-30 06:42:18 -050092#include <linux/device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090093#include <linux/gfp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070094#include <scsi/scsi_host.h>
95#include <linux/libata.h>
Tejun Heob8b275e2007-07-10 15:55:43 +090096#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070097
98#define DRV_NAME "ata_piix"
Alan Coxc611bed2009-05-06 17:08:44 +010099#define DRV_VERSION "2.13"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
101enum {
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
Tejun Heoc7290722008-01-18 18:36:30 +0900105 PIIX_SIDPR_BAR = 5,
106 PIIX_SIDPR_LEN = 16,
107 PIIX_SIDPR_IDX = 0,
108 PIIX_SIDPR_DATA = 4,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109
Tejun Heoff0fc142005-12-18 17:17:07 +0900110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
Tejun Heoc7290722008-01-18 18:36:30 +0900111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112
Tejun Heo800b3992006-12-03 21:34:13 +0900113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
Tejun Heob3362f82006-11-10 18:08:10 +0900115
Ming Lei5e5a4f52011-10-07 11:50:22 +0800116 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
117
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
Tejun Heod33f58b2006-03-01 01:25:39 +0900121 /* constants for mapping table */
122 P0 = 0, /* port 0 */
123 P1 = 1, /* port 1 */
124 P2 = 2, /* port 2 */
125 P3 = 3, /* port 3 */
126 IDE = -1, /* IDE */
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300127 NA = -2, /* not available */
Tejun Heod33f58b2006-03-01 01:25:39 +0900128 RV = -3, /* reserved */
129
Greg Felix7b6dbd62005-07-28 15:54:15 -0400130 PIIX_AHCI_DEVICE = 6,
Tejun Heob8b275e2007-07-10 15:55:43 +0900131
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134};
135
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900136enum piix_controller_ids {
137 /* controller IDs */
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
Alan Coxc611bed2009-05-06 17:08:44 +0100143 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900144 ich5_sata,
145 ich6_sata,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900146 ich6m_sata,
147 ich8_sata,
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900148 ich8_2port_sata,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900149 ich8m_apple_sata, /* locks up on second port enable */
150 tolapai_sata,
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
Ming Lei5e5a4f52011-10-07 11:50:22 +0800152 ich8_sata_snb,
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900153};
154
Tejun Heod33f58b2006-03-01 01:25:39 +0900155struct piix_map_db {
156 const u32 mask;
Jeff Garzik73291a12006-07-11 13:11:17 -0400157 const u16 port_enable;
Tejun Heod33f58b2006-03-01 01:25:39 +0900158 const int map[][4];
159};
160
Tejun Heod96715c2006-06-29 01:58:28 +0900161struct piix_host_priv {
162 const int *map;
Tejun Heo2852bcf2009-01-02 12:04:48 +0900163 u32 saved_iocfg;
Tejun Heoc7290722008-01-18 18:36:30 +0900164 void __iomem *sidpr;
Tejun Heod96715c2006-06-29 01:58:28 +0900165};
166
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167static unsigned int in_module_init = 1;
168
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500169static const struct pci_device_id piix_pci_tbl[] = {
Aland2cdfc02007-01-10 17:13:38 +0000170 /* Intel PIIX3 for the 430HX etc */
171 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
Tejun Heo25f98132008-01-07 19:38:53 +0900172 /* VMware ICH4 */
173 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400174 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
175 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
176 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400177 /* Intel PIIX4 */
178 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
179 /* Intel PIIX4 */
180 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
181 /* Intel PIIX */
182 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
183 /* Intel ICH (i810, i815, i840) UDMA 66*/
184 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
185 /* Intel ICH0 : UDMA 33*/
186 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
187 /* Intel ICH2M */
188 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
189 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
190 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191 /* Intel ICH3M */
192 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 /* Intel ICH3 (E7500/1) UDMA 100 */
194 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Ben Hutchings4bb969d2010-10-10 22:42:21 +0100195 /* Intel ICH4-L */
196 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400197 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
198 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 /* Intel ICH5 */
Christian Lamparter2eb829e2007-08-10 13:59:51 -0700201 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400202 /* C-ICH (i810E2) */
203 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik85cd7252006-08-31 00:03:49 -0400204 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400205 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* ICH6 (and 6) (i915) UDMA 100 */
207 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* ICH7/7-R (i945, i975) UDMA 100*/
Alan Coxc611bed2009-05-06 17:08:44 +0100209 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
210 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
Christian Lamparterc1e6f282007-07-03 10:19:20 -0400211 /* ICH8 Mobile PATA Controller */
212 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213
Alan Cox7654db12009-05-06 17:10:17 +0100214 /* SATA ports */
Jeff Garzik4fca3772011-02-15 01:13:24 -0500215
Tejun Heo1d076e52006-03-01 01:25:39 +0900216 /* 82801EB (ICH5) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900218 /* 82801EB (ICH5) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900220 /* 6300ESB (ICH5 variant with broken PCS present bits) */
Tejun Heo5e56a372006-11-10 18:08:10 +0900221 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900222 /* 6300ESB pretending RAID */
Tejun Heo5e56a372006-11-10 18:08:10 +0900223 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900224 /* 82801FB/FW (ICH6/ICH6W) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900226 /* 82801FR/FRW (ICH6R/ICH6RW) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900227 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo5016d7d2008-03-26 15:46:58 +0900228 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
229 * Attach iff the controller is in IDE mode. */
230 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900231 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900232 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900233 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900234 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900235 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800236 /* Enterprise Southbridge 2 (631xESB/632xESB) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900237 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800238 /* SATA Controller 1 IDE (ICH8) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900239 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800240 /* SATA Controller 2 IDE (ICH8) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900241 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900242 /* Mobile SATA Controller IDE (ICH8M), Apple */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900243 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
Tejun Heo23cf2962008-05-29 22:04:22 +0900244 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
Tejun Heo487eff62008-07-29 15:06:26 +0900245 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
Tejun Heo23cf2962008-05-29 22:04:22 +0900246 /* Mobile SATA Controller IDE (ICH8M) */
247 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800248 /* SATA Controller IDE (ICH9) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900249 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800250 /* SATA Controller IDE (ICH9) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900251 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800252 /* SATA Controller IDE (ICH9) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900253 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800254 /* SATA Controller IDE (ICH9M) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900255 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800256 /* SATA Controller IDE (ICH9M) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900257 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800258 /* SATA Controller IDE (ICH9M) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900259 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700260 /* SATA Controller IDE (Tolapai) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900261 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800262 /* SATA Controller IDE (ICH10) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900263 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800264 /* SATA Controller IDE (ICH10) */
265 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* SATA Controller IDE (ICH10) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900267 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800268 /* SATA Controller IDE (ICH10) */
269 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Seth Heasleyc6c6a1a2008-08-11 17:03:18 -0700270 /* SATA Controller IDE (PCH) */
271 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
272 /* SATA Controller IDE (PCH) */
Seth Heasley0395e612008-08-27 16:40:06 -0700273 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
274 /* SATA Controller IDE (PCH) */
Seth Heasleyc6c6a1a2008-08-11 17:03:18 -0700275 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
276 /* SATA Controller IDE (PCH) */
Seth Heasley0395e612008-08-27 16:40:06 -0700277 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
278 /* SATA Controller IDE (PCH) */
Seth Heasleyc6c6a1a2008-08-11 17:03:18 -0700279 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (PCH) */
281 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Seth Heasley88e82012010-01-12 17:01:28 -0800282 /* SATA Controller IDE (CPT) */
Ming Lei5e5a4f52011-10-07 11:50:22 +0800283 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
Seth Heasley88e82012010-01-12 17:01:28 -0800284 /* SATA Controller IDE (CPT) */
Ming Lei5e5a4f52011-10-07 11:50:22 +0800285 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
Seth Heasley88e82012010-01-12 17:01:28 -0800286 /* SATA Controller IDE (CPT) */
287 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
288 /* SATA Controller IDE (CPT) */
289 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Seth Heasley238e1492010-09-09 09:42:40 -0700290 /* SATA Controller IDE (PBG) */
Ming Lei5e5a4f52011-10-07 11:50:22 +0800291 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
Seth Heasley238e1492010-09-09 09:42:40 -0700292 /* SATA Controller IDE (PBG) */
293 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Seth Heasley4a836c72011-04-20 08:43:37 -0700294 /* SATA Controller IDE (Panther Point) */
Ming Lei5e5a4f52011-10-07 11:50:22 +0800295 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
Seth Heasley4a836c72011-04-20 08:43:37 -0700296 /* SATA Controller IDE (Panther Point) */
Ming Lei5e5a4f52011-10-07 11:50:22 +0800297 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
Seth Heasley4a836c72011-04-20 08:43:37 -0700298 /* SATA Controller IDE (Panther Point) */
299 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
300 /* SATA Controller IDE (Panther Point) */
301 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Seth Heasley78140cf2012-01-23 16:29:50 -0800302 /* SATA Controller IDE (Lynx Point) */
303 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
304 /* SATA Controller IDE (Lynx Point) */
305 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
306 /* SATA Controller IDE (Lynx Point) */
307 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
308 /* SATA Controller IDE (Lynx Point) */
309 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
James Ralston389cd782012-08-09 09:34:20 -0700310 /* SATA Controller IDE (Lynx Point-LP) */
311 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
312 /* SATA Controller IDE (Lynx Point-LP) */
313 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
314 /* SATA Controller IDE (Lynx Point-LP) */
315 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
316 /* SATA Controller IDE (Lynx Point-LP) */
317 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Seth Heasley96d5d962012-02-21 10:45:26 -0800318 /* SATA Controller IDE (DH89xxCC) */
319 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 { } /* terminate list */
321};
322
Tejun Heod96715c2006-06-29 01:58:28 +0900323static const struct piix_map_db ich5_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900324 .mask = 0x7,
Jeff Garzikea35d292006-07-11 11:48:50 -0400325 .port_enable = 0x3,
Tejun Heod33f58b2006-03-01 01:25:39 +0900326 .map = {
327 /* PM PS SM SS MAP */
328 { P0, NA, P1, NA }, /* 000b */
329 { P1, NA, P0, NA }, /* 001b */
330 { RV, RV, RV, RV },
331 { RV, RV, RV, RV },
332 { P0, P1, IDE, IDE }, /* 100b */
333 { P1, P0, IDE, IDE }, /* 101b */
334 { IDE, IDE, P0, P1 }, /* 110b */
335 { IDE, IDE, P1, P0 }, /* 111b */
336 },
337};
338
Tejun Heod96715c2006-06-29 01:58:28 +0900339static const struct piix_map_db ich6_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900340 .mask = 0x3,
Jeff Garzikea35d292006-07-11 11:48:50 -0400341 .port_enable = 0xf,
Tejun Heod33f58b2006-03-01 01:25:39 +0900342 .map = {
343 /* PM PS SM SS MAP */
Tejun Heo79ea24e2006-03-31 20:01:50 +0900344 { P0, P2, P1, P3 }, /* 00b */
Tejun Heod33f58b2006-03-01 01:25:39 +0900345 { IDE, IDE, P1, P3 }, /* 01b */
346 { P0, P2, IDE, IDE }, /* 10b */
347 { RV, RV, RV, RV },
348 },
349};
350
Tejun Heod96715c2006-06-29 01:58:28 +0900351static const struct piix_map_db ich6m_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900352 .mask = 0x3,
Jeff Garzikea35d292006-07-11 11:48:50 -0400353 .port_enable = 0x5,
Tejun Heo67083742006-09-11 06:29:03 +0900354
355 /* Map 01b isn't specified in the doc but some notebooks use
Tejun Heoc6446a42006-10-09 13:23:58 +0900356 * it anyway. MAP 01b have been spotted on both ICH6M and
357 * ICH7M.
Tejun Heo67083742006-09-11 06:29:03 +0900358 */
359 .map = {
360 /* PM PS SM SS MAP */
Tejun Heoe04b3b92007-07-10 17:58:21 +0900361 { P0, P2, NA, NA }, /* 00b */
Tejun Heo67083742006-09-11 06:29:03 +0900362 { IDE, IDE, P1, P3 }, /* 01b */
363 { P0, P2, IDE, IDE }, /* 10b */
364 { RV, RV, RV, RV },
365 },
366};
367
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400368static const struct piix_map_db ich8_map_db = {
369 .mask = 0x3,
Tejun Heoa0ce9ac2007-11-19 12:06:37 +0900370 .port_enable = 0xf,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400371 .map = {
372 /* PM PS SM SS MAP */
Kristen Carlson Accardi158f30c82006-10-19 13:27:39 -0700373 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400374 { RV, RV, RV, RV },
Tejun Heoac2b0432007-08-07 02:43:27 +0900375 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400376 { RV, RV, RV, RV },
377 },
378};
379
Tejun Heo00242ec2007-11-19 11:24:25 +0900380static const struct piix_map_db ich8_2port_map_db = {
Jason Gastone2d352a2007-09-07 17:21:03 -0700381 .mask = 0x3,
382 .port_enable = 0x3,
383 .map = {
384 /* PM PS SM SS MAP */
385 { P0, NA, P1, NA }, /* 00b */
386 { RV, RV, RV, RV }, /* 01b */
387 { RV, RV, RV, RV }, /* 10b */
388 { RV, RV, RV, RV },
389 },
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700390};
391
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900392static const struct piix_map_db ich8m_apple_map_db = {
393 .mask = 0x3,
394 .port_enable = 0x1,
395 .map = {
396 /* PM PS SM SS MAP */
397 { P0, NA, NA, NA }, /* 00b */
398 { RV, RV, RV, RV },
399 { P0, P2, IDE, IDE }, /* 10b */
400 { RV, RV, RV, RV },
401 },
402};
403
Tejun Heo00242ec2007-11-19 11:24:25 +0900404static const struct piix_map_db tolapai_map_db = {
Jason Gaston8f73a682007-10-11 16:05:15 -0700405 .mask = 0x3,
406 .port_enable = 0x3,
407 .map = {
408 /* PM PS SM SS MAP */
409 { P0, NA, P1, NA }, /* 00b */
410 { RV, RV, RV, RV }, /* 01b */
411 { RV, RV, RV, RV }, /* 10b */
412 { RV, RV, RV, RV },
413 },
414};
415
Tejun Heod96715c2006-06-29 01:58:28 +0900416static const struct piix_map_db *piix_map_db_table[] = {
417 [ich5_sata] = &ich5_map_db,
Tejun Heod96715c2006-06-29 01:58:28 +0900418 [ich6_sata] = &ich6_map_db,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900419 [ich6m_sata] = &ich6m_map_db,
420 [ich8_sata] = &ich8_map_db,
Tejun Heo00242ec2007-11-19 11:24:25 +0900421 [ich8_2port_sata] = &ich8_2port_map_db,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900422 [ich8m_apple_sata] = &ich8m_apple_map_db,
423 [tolapai_sata] = &tolapai_map_db,
Ming Lei5e5a4f52011-10-07 11:50:22 +0800424 [ich8_sata_snb] = &ich8_map_db,
Tejun Heod96715c2006-06-29 01:58:28 +0900425};
426
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427static struct pci_bits piix_enable_bits[] = {
428 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
429 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
430};
431
432MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
433MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
434MODULE_LICENSE("GPL");
435MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
436MODULE_VERSION(DRV_VERSION);
437
Alan Coxfc085152006-10-10 14:28:11 -0700438struct ich_laptop {
439 u16 device;
440 u16 subvendor;
441 u16 subdevice;
442};
443
444/*
445 * List of laptops that use short cables rather than 80 wire
446 */
447
448static const struct ich_laptop ich_laptop[] = {
449 /* devid, subvendor, subdev */
450 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
Alan Cox2655e2c2007-11-05 22:51:09 +0000451 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
J Jbabfb682007-01-09 02:26:30 +0900452 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
Steve Conklin60347342009-07-16 16:27:56 -0500453 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
Robin H\. Johnson12340102007-03-28 18:02:07 -0700454 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
Jeff Garzik54174db2007-09-29 04:01:43 -0400455 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200456 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
Herton Ronaldo Krzesinskid09addf2008-09-17 14:29:05 -0300457 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
Steve Conklin60347342009-07-16 16:27:56 -0500458 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
Tejun Heob33620f2007-05-22 11:34:22 +0200459 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
Colin Ian Kinge1fefea2008-06-03 18:59:02 +0200460 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
461 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
Dan McGee01ce2602008-04-20 22:03:27 -0500462 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
Alan Cox124a6ee2009-05-06 17:09:41 +0100463 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
Alan Coxfc085152006-10-10 14:28:11 -0700464 /* end marker */
465 { 0, }
466};
467
Ming Lei5e5a4f52011-10-07 11:50:22 +0800468static int piix_port_start(struct ata_port *ap)
469{
470 if (!(ap->flags & PIIX_FLAG_PIO16))
471 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
472
473 return ata_bmdma_port_start(ap);
474}
475
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476/**
Alan Coxeb4a2c72007-04-11 00:04:20 +0100477 * ich_pata_cable_detect - Probe host controller cable detect info
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478 * @ap: Port for which cable detect info is desired
479 *
480 * Read 80c cable indicator from ATA PCI device's PCI config
481 * register. This register is normally set by firmware (BIOS).
482 *
483 * LOCKING:
484 * None (inherited from caller).
485 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400486
Alan Coxeb4a2c72007-04-11 00:04:20 +0100487static int ich_pata_cable_detect(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488{
Jeff Garzikcca39742006-08-24 03:19:22 -0400489 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Tejun Heo2852bcf2009-01-02 12:04:48 +0900490 struct piix_host_priv *hpriv = ap->host->private_data;
Alan Coxfc085152006-10-10 14:28:11 -0700491 const struct ich_laptop *lap = &ich_laptop[0];
Tejun Heo2852bcf2009-01-02 12:04:48 +0900492 u8 mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493
Alan Coxfc085152006-10-10 14:28:11 -0700494 /* Check for specials - Acer Aspire 5602WLMi */
495 while (lap->device) {
496 if (lap->device == pdev->device &&
497 lap->subvendor == pdev->subsystem_vendor &&
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400498 lap->subdevice == pdev->subsystem_device)
Alan Coxeb4a2c72007-04-11 00:04:20 +0100499 return ATA_CBL_PATA40_SHORT;
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400500
Alan Coxfc085152006-10-10 14:28:11 -0700501 lap++;
502 }
503
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504 /* check BIOS cable detect results */
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900505 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
Tejun Heo2852bcf2009-01-02 12:04:48 +0900506 if ((hpriv->saved_iocfg & mask) == 0)
Alan Coxeb4a2c72007-04-11 00:04:20 +0100507 return ATA_CBL_PATA40;
508 return ATA_CBL_PATA80;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509}
510
511/**
Tejun Heoccc46722006-05-31 18:28:14 +0900512 * piix_pata_prereset - prereset for PATA host controller
Tejun Heocc0680a2007-08-06 18:36:23 +0900513 * @link: Target link
Tejun Heod4b2bab2007-02-02 16:50:52 +0900514 * @deadline: deadline jiffies for the operation
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516 * LOCKING:
517 * None (inherited from caller).
518 */
Tejun Heocc0680a2007-08-06 18:36:23 +0900519static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520{
Tejun Heocc0680a2007-08-06 18:36:23 +0900521 struct ata_port *ap = link->ap;
Jeff Garzikcca39742006-08-24 03:19:22 -0400522 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523
Alan Coxc9619222006-09-26 17:53:38 +0100524 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
525 return -ENOENT;
Tejun Heo9363c382008-04-07 22:47:16 +0900526 return ata_sff_prereset(link, deadline);
Tejun Heoccc46722006-05-31 18:28:14 +0900527}
528
Bartlomiej Zolnierkiewicz60c3be32009-08-30 14:56:30 +0200529static DEFINE_SPINLOCK(piix_lock);
530
Bartlomiej Zolnierkiewicz6a94a742011-10-13 15:39:10 +0200531static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
532 u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533{
Jeff Garzikcca39742006-08-24 03:19:22 -0400534 struct pci_dev *dev = to_pci_dev(ap->host->dev);
Bartlomiej Zolnierkiewicz60c3be32009-08-30 14:56:30 +0200535 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536 unsigned int is_slave = (adev->devno != 0);
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900537 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538 unsigned int slave_port = 0x44;
539 u16 master_data;
540 u8 slave_data;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400541 u8 udma_enable;
542 int control = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400543
Jeff Garzik669a5db2006-08-29 18:12:40 -0400544 /*
545 * See Intel Document 298600-004 for the timing programing rules
546 * for ICH controllers.
547 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700548
549 static const /* ISP RTC */
550 u8 timings[][2] = { { 0, 0 },
551 { 0, 0 },
552 { 1, 0 },
553 { 2, 1 },
554 { 2, 3 }, };
555
Jeff Garzik669a5db2006-08-29 18:12:40 -0400556 if (pio >= 2)
557 control |= 1; /* TIME1 enable */
558 if (ata_pio_need_iordy(adev))
559 control |= 2; /* IE enable */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400560 /* Intel specifies that the PPE functionality is for disk only */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400561 if (adev->class == ATA_DEV_ATA)
562 control |= 4; /* PPE enable */
Bartlomiej Zolnierkiewicz6a94a742011-10-13 15:39:10 +0200563 /*
564 * If the drive MWDMA is faster than it can do PIO then
565 * we must force PIO into PIO0
566 */
567 if (adev->pio_mode < XFER_PIO_0 + pio)
568 /* Enable DMA timing only */
569 control |= 8; /* PIO cycles in PIO0 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400570
Bartlomiej Zolnierkiewicz60c3be32009-08-30 14:56:30 +0200571 spin_lock_irqsave(&piix_lock, flags);
572
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200573 /* PIO configuration clears DTE unconditionally. It will be
574 * programmed in set_dmamode which is guaranteed to be called
575 * after set_piomode if any DMA mode is available.
576 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577 pci_read_config_word(dev, master_port, &master_data);
578 if (is_slave) {
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200579 /* clear TIME1|IE1|PPE1|DTE1 */
580 master_data &= 0xff0f;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400581 /* enable PPE1, IE1 and TIME1 as needed */
582 master_data |= (control << 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583 pci_read_config_byte(dev, slave_port, &slave_data);
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900584 slave_data &= (ap->port_no ? 0x0f : 0xf0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400585 /* Load the timing nibble for this slave */
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200586 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
587 << (ap->port_no ? 4 : 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588 } else {
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200589 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
590 master_data &= 0xccf0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400591 /* Enable PPE, IE and TIME as appropriate */
592 master_data |= control;
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200593 /* load ISP and RCT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594 master_data |=
595 (timings[pio][0] << 12) |
596 (timings[pio][1] << 8);
597 }
Bartlomiej Zolnierkiewiczce986692011-10-13 15:28:30 +0200598
599 /* Enable SITRE (separate slave timing register) */
600 master_data |= 0x4000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601 pci_write_config_word(dev, master_port, master_data);
602 if (is_slave)
603 pci_write_config_byte(dev, slave_port, slave_data);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400604
605 /* Ensure the UDMA bit is off - it will be turned back on if
606 UDMA is selected */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400607
Jeff Garzik669a5db2006-08-29 18:12:40 -0400608 if (ap->udma_mask) {
609 pci_read_config_byte(dev, 0x48, &udma_enable);
610 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
611 pci_write_config_byte(dev, 0x48, udma_enable);
612 }
Bartlomiej Zolnierkiewicz60c3be32009-08-30 14:56:30 +0200613
614 spin_unlock_irqrestore(&piix_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615}
616
617/**
Bartlomiej Zolnierkiewicz6a94a742011-10-13 15:39:10 +0200618 * piix_set_piomode - Initialize host controller PATA PIO timings
619 * @ap: Port whose timings we are configuring
620 * @adev: Drive in question
621 *
622 * Set PIO mode for device, in host controller PCI config space.
623 *
624 * LOCKING:
625 * None (inherited from caller).
626 */
627
628static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
629{
630 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
631}
632
633/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400634 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
Linus Torvalds1da177e2005-04-16 15:20:36 -0700635 * @ap: Port whose timings we are configuring
Jeff Garzik669a5db2006-08-29 18:12:40 -0400636 * @adev: Drive in question
Hennec32a8fd2006-09-25 22:00:46 +0200637 * @isich: set if the chip is an ICH device
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638 *
639 * Set UDMA mode for device, in host controller PCI config space.
640 *
641 * LOCKING:
642 * None (inherited from caller).
643 */
644
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400645static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646{
Jeff Garzikcca39742006-08-24 03:19:22 -0400647 struct pci_dev *dev = to_pci_dev(ap->host->dev);
Bartlomiej Zolnierkiewicz60c3be32009-08-30 14:56:30 +0200648 unsigned long flags;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400649 u8 speed = adev->dma_mode;
650 int devid = adev->devno + 2 * ap->port_no;
Andrew Mortondedf61db2007-01-10 17:20:34 -0800651 u8 udma_enable = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400652
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 if (speed >= XFER_UDMA_0) {
Bartlomiej Zolnierkiewicz6a94a742011-10-13 15:39:10 +0200654 unsigned int udma = speed - XFER_UDMA_0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400655 u16 udma_timing;
656 u16 ideconf;
657 int u_clock, u_speed;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400658
Bartlomiej Zolnierkiewicz6a94a742011-10-13 15:39:10 +0200659 spin_lock_irqsave(&piix_lock, flags);
660
661 pci_read_config_byte(dev, 0x48, &udma_enable);
662
Jeff Garzik669a5db2006-08-29 18:12:40 -0400663 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400664 * UDMA is handled by a combination of clock switching and
Jeff Garzik85cd7252006-08-31 00:03:49 -0400665 * selection of dividers
666 *
Jeff Garzik669a5db2006-08-29 18:12:40 -0400667 * Handy rule: Odd modes are UDMATIMx 01, even are 02
Jeff Garzik85cd7252006-08-31 00:03:49 -0400668 * except UDMA0 which is 00
Jeff Garzik669a5db2006-08-29 18:12:40 -0400669 */
670 u_speed = min(2 - (udma & 1), udma);
671 if (udma == 5)
672 u_clock = 0x1000; /* 100Mhz */
673 else if (udma > 2)
674 u_clock = 1; /* 66Mhz */
675 else
676 u_clock = 0; /* 33Mhz */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400677
Jeff Garzik669a5db2006-08-29 18:12:40 -0400678 udma_enable |= (1 << devid);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400679
Jeff Garzik669a5db2006-08-29 18:12:40 -0400680 /* Load the CT/RP selection */
681 pci_read_config_word(dev, 0x4A, &udma_timing);
682 udma_timing &= ~(3 << (4 * devid));
683 udma_timing |= u_speed << (4 * devid);
684 pci_write_config_word(dev, 0x4A, udma_timing);
685
Jeff Garzik85cd7252006-08-31 00:03:49 -0400686 if (isich) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400687 /* Select a 33/66/100Mhz clock */
688 pci_read_config_word(dev, 0x54, &ideconf);
689 ideconf &= ~(0x1001 << devid);
690 ideconf |= u_clock << devid;
691 /* For ICH or later we should set bit 10 for better
692 performance (WR_PingPong_En) */
693 pci_write_config_word(dev, 0x54, ideconf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694 }
Bartlomiej Zolnierkiewicz6a94a742011-10-13 15:39:10 +0200695
696 pci_write_config_byte(dev, 0x48, udma_enable);
697
698 spin_unlock_irqrestore(&piix_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699 } else {
Bartlomiej Zolnierkiewicz6a94a742011-10-13 15:39:10 +0200700 /* MWDMA is driven by the PIO timings. */
701 unsigned int mwdma = speed - XFER_MW_DMA_0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400702 const unsigned int needed_pio[3] = {
703 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
704 };
705 int pio = needed_pio[mwdma] - XFER_PIO_0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400706
Bartlomiej Zolnierkiewicz6a94a742011-10-13 15:39:10 +0200707 /* XFER_PIO_0 is never used currently */
708 piix_set_timings(ap, adev, pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700709 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400710}
711
712/**
713 * piix_set_dmamode - Initialize host controller PATA DMA timings
714 * @ap: Port whose timings we are configuring
715 * @adev: um
716 *
717 * Set MW/UDMA mode for device, in host controller PCI config space.
718 *
719 * LOCKING:
720 * None (inherited from caller).
721 */
722
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400723static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400724{
725 do_pata_set_dmamode(ap, adev, 0);
726}
727
728/**
729 * ich_set_dmamode - Initialize host controller PATA DMA timings
730 * @ap: Port whose timings we are configuring
731 * @adev: um
732 *
733 * Set MW/UDMA mode for device, in host controller PCI config space.
734 *
735 * LOCKING:
736 * None (inherited from caller).
737 */
738
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400739static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400740{
741 do_pata_set_dmamode(ap, adev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742}
743
Tejun Heoc7290722008-01-18 18:36:30 +0900744/*
745 * Serial ATA Index/Data Pair Superset Registers access
746 *
747 * Beginning from ICH8, there's a sane way to access SCRs using index
Tejun Heobe77e432008-07-31 17:02:44 +0900748 * and data register pair located at BAR5 which means that we have
749 * separate SCRs for master and slave. This is handled using libata
750 * slave_link facility.
Tejun Heoc7290722008-01-18 18:36:30 +0900751 */
752static const int piix_sidx_map[] = {
753 [SCR_STATUS] = 0,
754 [SCR_ERROR] = 2,
755 [SCR_CONTROL] = 1,
756};
757
Tejun Heobe77e432008-07-31 17:02:44 +0900758static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
Tejun Heoc7290722008-01-18 18:36:30 +0900759{
Tejun Heobe77e432008-07-31 17:02:44 +0900760 struct ata_port *ap = link->ap;
Tejun Heoc7290722008-01-18 18:36:30 +0900761 struct piix_host_priv *hpriv = ap->host->private_data;
762
Tejun Heobe77e432008-07-31 17:02:44 +0900763 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
Tejun Heoc7290722008-01-18 18:36:30 +0900764 hpriv->sidpr + PIIX_SIDPR_IDX);
765}
766
Tejun Heo82ef04f2008-07-31 17:02:40 +0900767static int piix_sidpr_scr_read(struct ata_link *link,
768 unsigned int reg, u32 *val)
Tejun Heoc7290722008-01-18 18:36:30 +0900769{
Tejun Heobe77e432008-07-31 17:02:44 +0900770 struct piix_host_priv *hpriv = link->ap->host->private_data;
Tejun Heoc7290722008-01-18 18:36:30 +0900771
772 if (reg >= ARRAY_SIZE(piix_sidx_map))
773 return -EINVAL;
774
Tejun Heobe77e432008-07-31 17:02:44 +0900775 piix_sidpr_sel(link, reg);
776 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
Tejun Heoc7290722008-01-18 18:36:30 +0900777 return 0;
778}
779
Tejun Heo82ef04f2008-07-31 17:02:40 +0900780static int piix_sidpr_scr_write(struct ata_link *link,
781 unsigned int reg, u32 val)
Tejun Heoc7290722008-01-18 18:36:30 +0900782{
Tejun Heobe77e432008-07-31 17:02:44 +0900783 struct piix_host_priv *hpriv = link->ap->host->private_data;
Tejun Heo82ef04f2008-07-31 17:02:40 +0900784
Tejun Heoc7290722008-01-18 18:36:30 +0900785 if (reg >= ARRAY_SIZE(piix_sidx_map))
786 return -EINVAL;
787
Tejun Heobe77e432008-07-31 17:02:44 +0900788 piix_sidpr_sel(link, reg);
789 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
Tejun Heoc7290722008-01-18 18:36:30 +0900790 return 0;
791}
792
Tejun Heoa97c40062010-09-01 17:50:08 +0200793static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
794 unsigned hints)
795{
796 return sata_link_scr_lpm(link, policy, false);
797}
798
Tejun Heo27943622010-01-19 10:49:19 +0900799static bool piix_irq_check(struct ata_port *ap)
800{
801 if (unlikely(!ap->ioaddr.bmdma_addr))
802 return false;
803
804 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
805}
806
Tejun Heob8b275e2007-07-10 15:55:43 +0900807#ifdef CONFIG_PM
Tejun Heo8c3832e2007-07-27 14:53:28 +0900808static int piix_broken_suspend(void)
809{
Jeff Garzik18552562007-10-03 15:15:40 -0400810 static const struct dmi_system_id sysids[] = {
Tejun Heo8c3832e2007-07-27 14:53:28 +0900811 {
Tejun Heo4c74d4e2007-09-30 01:11:20 -0700812 .ident = "TECRA M3",
813 .matches = {
814 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
815 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
816 },
817 },
818 {
Peter Schwenke04d86d62007-11-30 15:28:29 +0900819 .ident = "TECRA M3",
820 .matches = {
821 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
822 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
823 },
824 },
825 {
Peter Schwenked1aa6902007-12-05 10:39:49 +0900826 .ident = "TECRA M4",
827 .matches = {
828 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
829 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
830 },
831 },
832 {
Tejun Heo040dee52008-06-13 18:05:02 +0900833 .ident = "TECRA M4",
834 .matches = {
835 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
836 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
837 },
838 },
839 {
Tejun Heo8c3832e2007-07-27 14:53:28 +0900840 .ident = "TECRA M5",
841 .matches = {
842 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
843 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
844 },
Tejun Heob8b275e2007-07-10 15:55:43 +0900845 },
Tejun Heo8c3832e2007-07-27 14:53:28 +0900846 {
Peter Schwenkeffe188d2008-01-17 23:08:55 +1000847 .ident = "TECRA M6",
848 .matches = {
849 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
850 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
851 },
852 },
853 {
Tejun Heo5c08ea02007-08-14 19:56:04 +0900854 .ident = "TECRA M7",
855 .matches = {
856 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
857 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
858 },
859 },
860 {
Peter Schwenke04d86d62007-11-30 15:28:29 +0900861 .ident = "TECRA A8",
862 .matches = {
863 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
864 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
865 },
866 },
867 {
Peter Schwenkeffe188d2008-01-17 23:08:55 +1000868 .ident = "Satellite R20",
869 .matches = {
870 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
871 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
872 },
873 },
874 {
Peter Schwenke04d86d62007-11-30 15:28:29 +0900875 .ident = "Satellite R25",
876 .matches = {
877 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
878 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
879 },
880 },
881 {
Tejun Heo3cc0b9d2007-08-25 08:31:02 +0900882 .ident = "Satellite U200",
883 .matches = {
884 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
885 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
886 },
887 },
888 {
Peter Schwenke04d86d62007-11-30 15:28:29 +0900889 .ident = "Satellite U200",
890 .matches = {
891 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
892 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
893 },
894 },
895 {
Yann Chachkoff62320e22007-11-07 12:02:27 +0900896 .ident = "Satellite Pro U200",
897 .matches = {
898 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
899 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
900 },
901 },
902 {
Tejun Heo8c3832e2007-07-27 14:53:28 +0900903 .ident = "Satellite U205",
904 .matches = {
905 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
906 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
907 },
Tejun Heob8b275e2007-07-10 15:55:43 +0900908 },
Tejun Heo8c3832e2007-07-27 14:53:28 +0900909 {
Tejun Heode753e52007-11-12 17:56:24 +0900910 .ident = "SATELLITE U205",
911 .matches = {
912 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
913 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
914 },
915 },
916 {
Benjamin Larssonb73fa462012-01-08 00:39:10 +0100917 .ident = "Satellite Pro A120",
918 .matches = {
919 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
920 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
921 },
922 },
923 {
Tejun Heo8c3832e2007-07-27 14:53:28 +0900924 .ident = "Portege M500",
925 .matches = {
926 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
927 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
928 },
Tejun Heob8b275e2007-07-10 15:55:43 +0900929 },
Tejun Heoc3f93b82009-03-31 10:44:34 +0900930 {
931 .ident = "VGN-BX297XP",
932 .matches = {
933 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
934 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
935 },
936 },
Jeff Garzik7d051542007-09-01 06:48:52 -0400937
938 { } /* terminate list */
Tejun Heo8c3832e2007-07-27 14:53:28 +0900939 };
Tejun Heo7abe79c2007-07-27 14:55:07 +0900940 static const char *oemstrs[] = {
941 "Tecra M3,",
942 };
943 int i;
Tejun Heo8c3832e2007-07-27 14:53:28 +0900944
945 if (dmi_check_system(sysids))
946 return 1;
947
Tejun Heo7abe79c2007-07-27 14:55:07 +0900948 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
949 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
950 return 1;
951
Tejun Heo1eedb4a2008-11-29 22:37:21 +0900952 /* TECRA M4 sometimes forgets its identify and reports bogus
953 * DMI information. As the bogus information is a bit
954 * generic, match as many entries as possible. This manual
955 * matching is necessary because dmi_system_id.matches is
956 * limited to four entries.
957 */
Jiri Slaby3c387732008-12-10 14:07:22 +0100958 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
959 dmi_match(DMI_PRODUCT_NAME, "000000") &&
960 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
961 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
962 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
963 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
964 dmi_match(DMI_BOARD_VERSION, "Version A0"))
Tejun Heo1eedb4a2008-11-29 22:37:21 +0900965 return 1;
966
Tejun Heo8c3832e2007-07-27 14:53:28 +0900967 return 0;
968}
Tejun Heob8b275e2007-07-10 15:55:43 +0900969
970static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
971{
972 struct ata_host *host = dev_get_drvdata(&pdev->dev);
973 unsigned long flags;
974 int rc = 0;
975
976 rc = ata_host_suspend(host, mesg);
977 if (rc)
978 return rc;
979
980 /* Some braindamaged ACPI suspend implementations expect the
981 * controller to be awake on entry; otherwise, it burns cpu
982 * cycles and power trying to do something to the sleeping
983 * beauty.
984 */
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100985 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
Tejun Heob8b275e2007-07-10 15:55:43 +0900986 pci_save_state(pdev);
987
988 /* mark its power state as "unknown", since we don't
989 * know if e.g. the BIOS will change its device state
990 * when we suspend.
991 */
992 if (pdev->current_state == PCI_D0)
993 pdev->current_state = PCI_UNKNOWN;
994
995 /* tell resume that it's waking up from broken suspend */
996 spin_lock_irqsave(&host->lock, flags);
997 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
998 spin_unlock_irqrestore(&host->lock, flags);
999 } else
1000 ata_pci_device_do_suspend(pdev, mesg);
1001
1002 return 0;
1003}
1004
1005static int piix_pci_device_resume(struct pci_dev *pdev)
1006{
1007 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1008 unsigned long flags;
1009 int rc;
1010
1011 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1012 spin_lock_irqsave(&host->lock, flags);
1013 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1014 spin_unlock_irqrestore(&host->lock, flags);
1015
1016 pci_set_power_state(pdev, PCI_D0);
1017 pci_restore_state(pdev);
1018
1019 /* PCI device wasn't disabled during suspend. Use
Tejun Heo0b62e132007-07-27 14:43:35 +09001020 * pci_reenable_device() to avoid affecting the enable
1021 * count.
Tejun Heob8b275e2007-07-10 15:55:43 +09001022 */
Tejun Heo0b62e132007-07-27 14:43:35 +09001023 rc = pci_reenable_device(pdev);
Tejun Heob8b275e2007-07-10 15:55:43 +09001024 if (rc)
Joe Perchesa44fec12011-04-15 15:51:58 -07001025 dev_err(&pdev->dev,
1026 "failed to enable device after resume (%d)\n",
1027 rc);
Tejun Heob8b275e2007-07-10 15:55:43 +09001028 } else
1029 rc = ata_pci_device_do_resume(pdev);
1030
1031 if (rc == 0)
1032 ata_host_resume(host);
1033
1034 return rc;
1035}
1036#endif
1037
Tejun Heo25f98132008-01-07 19:38:53 +09001038static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1039{
1040 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1041}
1042
Bartlomiej Zolnierkiewiczf295be22012-11-30 11:56:04 +01001043static struct scsi_host_template piix_sht = {
1044 ATA_BMDMA_SHT(DRV_NAME),
1045};
1046
1047static struct ata_port_operations piix_sata_ops = {
1048 .inherits = &ata_bmdma32_port_ops,
1049 .sff_irq_check = piix_irq_check,
1050 .port_start = piix_port_start,
1051};
1052
1053static struct ata_port_operations piix_pata_ops = {
1054 .inherits = &piix_sata_ops,
1055 .cable_detect = ata_cable_40wire,
1056 .set_piomode = piix_set_piomode,
1057 .set_dmamode = piix_set_dmamode,
1058 .prereset = piix_pata_prereset,
1059};
1060
1061static struct ata_port_operations piix_vmw_ops = {
1062 .inherits = &piix_pata_ops,
1063 .bmdma_status = piix_vmw_bmdma_status,
1064};
1065
1066static struct ata_port_operations ich_pata_ops = {
1067 .inherits = &piix_pata_ops,
1068 .cable_detect = ich_pata_cable_detect,
1069 .set_dmamode = ich_set_dmamode,
1070};
1071
1072static struct device_attribute *piix_sidpr_shost_attrs[] = {
1073 &dev_attr_link_power_management_policy,
1074 NULL
1075};
1076
1077static struct scsi_host_template piix_sidpr_sht = {
1078 ATA_BMDMA_SHT(DRV_NAME),
1079 .shost_attrs = piix_sidpr_shost_attrs,
1080};
1081
1082static struct ata_port_operations piix_sidpr_sata_ops = {
1083 .inherits = &piix_sata_ops,
1084 .hardreset = sata_std_hardreset,
1085 .scr_read = piix_sidpr_scr_read,
1086 .scr_write = piix_sidpr_scr_write,
1087 .set_lpm = piix_sidpr_set_lpm,
1088};
1089
1090static struct ata_port_info piix_port_info[] = {
1091 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
1092 {
1093 .flags = PIIX_PATA_FLAGS,
1094 .pio_mask = ATA_PIO4,
1095 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1096 .port_ops = &piix_pata_ops,
1097 },
1098
1099 [piix_pata_33] = /* PIIX4 at 33MHz */
1100 {
1101 .flags = PIIX_PATA_FLAGS,
1102 .pio_mask = ATA_PIO4,
1103 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1104 .udma_mask = ATA_UDMA2,
1105 .port_ops = &piix_pata_ops,
1106 },
1107
1108 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
1109 {
1110 .flags = PIIX_PATA_FLAGS,
1111 .pio_mask = ATA_PIO4,
1112 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
1113 .udma_mask = ATA_UDMA2,
1114 .port_ops = &ich_pata_ops,
1115 },
1116
1117 [ich_pata_66] = /* ICH controllers up to 66MHz */
1118 {
1119 .flags = PIIX_PATA_FLAGS,
1120 .pio_mask = ATA_PIO4,
1121 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
1122 .udma_mask = ATA_UDMA4,
1123 .port_ops = &ich_pata_ops,
1124 },
1125
1126 [ich_pata_100] =
1127 {
1128 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1129 .pio_mask = ATA_PIO4,
1130 .mwdma_mask = ATA_MWDMA12_ONLY,
1131 .udma_mask = ATA_UDMA5,
1132 .port_ops = &ich_pata_ops,
1133 },
1134
1135 [ich_pata_100_nomwdma1] =
1136 {
1137 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1138 .pio_mask = ATA_PIO4,
1139 .mwdma_mask = ATA_MWDMA2_ONLY,
1140 .udma_mask = ATA_UDMA5,
1141 .port_ops = &ich_pata_ops,
1142 },
1143
1144 [ich5_sata] =
1145 {
1146 .flags = PIIX_SATA_FLAGS,
1147 .pio_mask = ATA_PIO4,
1148 .mwdma_mask = ATA_MWDMA2,
1149 .udma_mask = ATA_UDMA6,
1150 .port_ops = &piix_sata_ops,
1151 },
1152
1153 [ich6_sata] =
1154 {
1155 .flags = PIIX_SATA_FLAGS,
1156 .pio_mask = ATA_PIO4,
1157 .mwdma_mask = ATA_MWDMA2,
1158 .udma_mask = ATA_UDMA6,
1159 .port_ops = &piix_sata_ops,
1160 },
1161
1162 [ich6m_sata] =
1163 {
1164 .flags = PIIX_SATA_FLAGS,
1165 .pio_mask = ATA_PIO4,
1166 .mwdma_mask = ATA_MWDMA2,
1167 .udma_mask = ATA_UDMA6,
1168 .port_ops = &piix_sata_ops,
1169 },
1170
1171 [ich8_sata] =
1172 {
1173 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1174 .pio_mask = ATA_PIO4,
1175 .mwdma_mask = ATA_MWDMA2,
1176 .udma_mask = ATA_UDMA6,
1177 .port_ops = &piix_sata_ops,
1178 },
1179
1180 [ich8_2port_sata] =
1181 {
1182 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1183 .pio_mask = ATA_PIO4,
1184 .mwdma_mask = ATA_MWDMA2,
1185 .udma_mask = ATA_UDMA6,
1186 .port_ops = &piix_sata_ops,
1187 },
1188
1189 [tolapai_sata] =
1190 {
1191 .flags = PIIX_SATA_FLAGS,
1192 .pio_mask = ATA_PIO4,
1193 .mwdma_mask = ATA_MWDMA2,
1194 .udma_mask = ATA_UDMA6,
1195 .port_ops = &piix_sata_ops,
1196 },
1197
1198 [ich8m_apple_sata] =
1199 {
1200 .flags = PIIX_SATA_FLAGS,
1201 .pio_mask = ATA_PIO4,
1202 .mwdma_mask = ATA_MWDMA2,
1203 .udma_mask = ATA_UDMA6,
1204 .port_ops = &piix_sata_ops,
1205 },
1206
1207 [piix_pata_vmw] =
1208 {
1209 .flags = PIIX_PATA_FLAGS,
1210 .pio_mask = ATA_PIO4,
1211 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1212 .udma_mask = ATA_UDMA2,
1213 .port_ops = &piix_vmw_ops,
1214 },
1215
1216 /*
1217 * some Sandybridge chipsets have broken 32 mode up to now,
1218 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
1219 */
1220 [ich8_sata_snb] =
1221 {
1222 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1223 .pio_mask = ATA_PIO4,
1224 .mwdma_mask = ATA_MWDMA2,
1225 .udma_mask = ATA_UDMA6,
1226 .port_ops = &piix_sata_ops,
1227 },
1228};
1229
Linus Torvalds1da177e2005-04-16 15:20:36 -07001230#define AHCI_PCI_BAR 5
1231#define AHCI_GLOBAL_CTL 0x04
1232#define AHCI_ENABLE (1 << 31)
1233static int piix_disable_ahci(struct pci_dev *pdev)
1234{
Jeff Garzikea6ba102005-08-30 05:18:18 -04001235 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001236 u32 tmp;
1237 int rc = 0;
1238
1239 /* BUG: pci_enable_device has not yet been called. This
1240 * works because this device is usually set up by BIOS.
1241 */
1242
Jeff Garzik374b1872005-08-30 05:42:52 -04001243 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1244 !pci_resource_len(pdev, AHCI_PCI_BAR))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245 return 0;
Greg Felix7b6dbd62005-07-28 15:54:15 -04001246
Jeff Garzik374b1872005-08-30 05:42:52 -04001247 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001248 if (!mmio)
1249 return -ENOMEM;
Greg Felix7b6dbd62005-07-28 15:54:15 -04001250
Alan Coxc47a6312007-11-19 14:28:28 +00001251 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252 if (tmp & AHCI_ENABLE) {
1253 tmp &= ~AHCI_ENABLE;
Alan Coxc47a6312007-11-19 14:28:28 +00001254 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255
Alan Coxc47a6312007-11-19 14:28:28 +00001256 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001257 if (tmp & AHCI_ENABLE)
1258 rc = -EIO;
1259 }
Greg Felix7b6dbd62005-07-28 15:54:15 -04001260
Jeff Garzik374b1872005-08-30 05:42:52 -04001261 pci_iounmap(pdev, mmio);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262 return rc;
1263}
1264
1265/**
Alan Coxc621b142005-12-08 19:22:28 +00001266 * piix_check_450nx_errata - Check for problem 450NX setup
Randy Dunlapc893a3a2006-01-28 13:15:32 -05001267 * @ata_dev: the PCI device to check
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001268 *
Alan Coxc621b142005-12-08 19:22:28 +00001269 * Check for the present of 450NX errata #19 and errata #25. If
1270 * they are found return an error code so we can turn off DMA
1271 */
1272
Greg Kroah-Hartman0ec24912012-12-21 13:19:58 -08001273static int piix_check_450nx_errata(struct pci_dev *ata_dev)
Alan Coxc621b142005-12-08 19:22:28 +00001274{
1275 struct pci_dev *pdev = NULL;
1276 u16 cfg;
Alan Coxc621b142005-12-08 19:22:28 +00001277 int no_piix_dma = 0;
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001278
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001279 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
Alan Coxc621b142005-12-08 19:22:28 +00001280 /* Look for 450NX PXB. Check for problem configurations
1281 A PCI quirk checks bit 6 already */
Alan Coxc621b142005-12-08 19:22:28 +00001282 pci_read_config_word(pdev, 0x41, &cfg);
1283 /* Only on the original revision: IDE DMA can hang */
Auke Kok44c10132007-06-08 15:46:36 -07001284 if (pdev->revision == 0x00)
Alan Coxc621b142005-12-08 19:22:28 +00001285 no_piix_dma = 1;
1286 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
Auke Kok44c10132007-06-08 15:46:36 -07001287 else if (cfg & (1<<14) && pdev->revision < 5)
Alan Coxc621b142005-12-08 19:22:28 +00001288 no_piix_dma = 2;
1289 }
Alan Cox31a34fe2006-05-22 22:58:14 +01001290 if (no_piix_dma)
Joe Perchesa44fec12011-04-15 15:51:58 -07001291 dev_warn(&ata_dev->dev,
1292 "450NX errata present, disabling IDE DMA%s\n",
1293 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1294 : "");
1295
Alan Coxc621b142005-12-08 19:22:28 +00001296 return no_piix_dma;
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001297}
Alan Coxc621b142005-12-08 19:22:28 +00001298
Greg Kroah-Hartman0ec24912012-12-21 13:19:58 -08001299static void piix_init_pcs(struct ata_host *host,
1300 const struct piix_map_db *map_db)
Jeff Garzikea35d292006-07-11 11:48:50 -04001301{
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001302 struct pci_dev *pdev = to_pci_dev(host->dev);
Jeff Garzikea35d292006-07-11 11:48:50 -04001303 u16 pcs, new_pcs;
1304
1305 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1306
1307 new_pcs = pcs | map_db->port_enable;
1308
1309 if (new_pcs != pcs) {
1310 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1311 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1312 msleep(150);
1313 }
1314}
1315
Greg Kroah-Hartman0ec24912012-12-21 13:19:58 -08001316static const int *piix_init_sata_map(struct pci_dev *pdev,
1317 struct ata_port_info *pinfo,
1318 const struct piix_map_db *map_db)
Tejun Heod33f58b2006-03-01 01:25:39 +09001319{
Al Virob4482a42007-10-14 19:35:40 +01001320 const int *map;
Tejun Heod33f58b2006-03-01 01:25:39 +09001321 int i, invalid_map = 0;
1322 u8 map_value;
1323
1324 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1325
1326 map = map_db->map[map_value & map_db->mask];
1327
Joe Perchesa44fec12011-04-15 15:51:58 -07001328 dev_info(&pdev->dev, "MAP [");
Tejun Heod33f58b2006-03-01 01:25:39 +09001329 for (i = 0; i < 4; i++) {
1330 switch (map[i]) {
1331 case RV:
1332 invalid_map = 1;
Joe Perchesa44fec12011-04-15 15:51:58 -07001333 pr_cont(" XX");
Tejun Heod33f58b2006-03-01 01:25:39 +09001334 break;
1335
1336 case NA:
Joe Perchesa44fec12011-04-15 15:51:58 -07001337 pr_cont(" --");
Tejun Heod33f58b2006-03-01 01:25:39 +09001338 break;
1339
1340 case IDE:
1341 WARN_ON((i & 1) || map[i + 1] != IDE);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001342 pinfo[i / 2] = piix_port_info[ich_pata_100];
Tejun Heod33f58b2006-03-01 01:25:39 +09001343 i++;
Joe Perchesa44fec12011-04-15 15:51:58 -07001344 pr_cont(" IDE IDE");
Tejun Heod33f58b2006-03-01 01:25:39 +09001345 break;
1346
1347 default:
Joe Perchesa44fec12011-04-15 15:51:58 -07001348 pr_cont(" P%d", map[i]);
Tejun Heod33f58b2006-03-01 01:25:39 +09001349 if (i & 1)
Jeff Garzikcca39742006-08-24 03:19:22 -04001350 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
Tejun Heod33f58b2006-03-01 01:25:39 +09001351 break;
1352 }
1353 }
Joe Perchesa44fec12011-04-15 15:51:58 -07001354 pr_cont(" ]\n");
Tejun Heod33f58b2006-03-01 01:25:39 +09001355
1356 if (invalid_map)
Joe Perchesa44fec12011-04-15 15:51:58 -07001357 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
Tejun Heod33f58b2006-03-01 01:25:39 +09001358
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001359 return map;
Tejun Heod33f58b2006-03-01 01:25:39 +09001360}
1361
Tejun Heoe9c16702009-03-03 13:52:16 +09001362static bool piix_no_sidpr(struct ata_host *host)
1363{
1364 struct pci_dev *pdev = to_pci_dev(host->dev);
1365
1366 /*
1367 * Samsung DB-P70 only has three ATA ports exposed and
1368 * curiously the unconnected first port reports link online
1369 * while not responding to SRST protocol causing excessive
1370 * detection delay.
1371 *
1372 * Unfortunately, the system doesn't carry enough DMI
1373 * information to identify the machine but does have subsystem
1374 * vendor and device set. As it's unclear whether the
1375 * subsystem vendor/device is used only for this specific
1376 * board, the port can't be disabled solely with the
1377 * information; however, turning off SIDPR access works around
1378 * the problem. Turn it off.
1379 *
1380 * This problem is reported in bnc#441240.
1381 *
1382 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1383 */
1384 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1385 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1386 pdev->subsystem_device == 0xb049) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001387 dev_warn(host->dev,
1388 "Samsung DB-P70 detected, disabling SIDPR\n");
Tejun Heoe9c16702009-03-03 13:52:16 +09001389 return true;
1390 }
1391
1392 return false;
1393}
1394
Greg Kroah-Hartman0ec24912012-12-21 13:19:58 -08001395static int piix_init_sidpr(struct ata_host *host)
Tejun Heoc7290722008-01-18 18:36:30 +09001396{
1397 struct pci_dev *pdev = to_pci_dev(host->dev);
1398 struct piix_host_priv *hpriv = host->private_data;
Tejun Heobe77e432008-07-31 17:02:44 +09001399 struct ata_link *link0 = &host->ports[0]->link;
Tejun Heocb6716c2008-05-01 10:03:08 +09001400 u32 scontrol;
Tejun Heobe77e432008-07-31 17:02:44 +09001401 int i, rc;
Tejun Heoc7290722008-01-18 18:36:30 +09001402
1403 /* check for availability */
1404 for (i = 0; i < 4; i++)
1405 if (hpriv->map[i] == IDE)
Tejun Heobe77e432008-07-31 17:02:44 +09001406 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001407
Tejun Heoe9c16702009-03-03 13:52:16 +09001408 /* is it blacklisted? */
1409 if (piix_no_sidpr(host))
1410 return 0;
1411
Tejun Heoc7290722008-01-18 18:36:30 +09001412 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
Tejun Heobe77e432008-07-31 17:02:44 +09001413 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001414
1415 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1416 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
Tejun Heobe77e432008-07-31 17:02:44 +09001417 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001418
1419 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
Tejun Heobe77e432008-07-31 17:02:44 +09001420 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001421
1422 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
Tejun Heocb6716c2008-05-01 10:03:08 +09001423
1424 /* SCR access via SIDPR doesn't work on some configurations.
1425 * Give it a test drive by inhibiting power save modes which
1426 * we'll do anyway.
1427 */
Tejun Heobe77e432008-07-31 17:02:44 +09001428 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
Tejun Heocb6716c2008-05-01 10:03:08 +09001429
1430 /* if IPM is already 3, SCR access is probably working. Don't
1431 * un-inhibit power save modes as BIOS might have inhibited
1432 * them for a reason.
1433 */
1434 if ((scontrol & 0xf00) != 0x300) {
1435 scontrol |= 0x300;
Tejun Heobe77e432008-07-31 17:02:44 +09001436 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1437 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
Tejun Heocb6716c2008-05-01 10:03:08 +09001438
1439 if ((scontrol & 0xf00) != 0x300) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001440 dev_info(host->dev,
1441 "SCR access via SIDPR is available but doesn't work\n");
Tejun Heobe77e432008-07-31 17:02:44 +09001442 return 0;
Tejun Heocb6716c2008-05-01 10:03:08 +09001443 }
1444 }
1445
Tejun Heobe77e432008-07-31 17:02:44 +09001446 /* okay, SCRs available, set ops and ask libata for slave_link */
1447 for (i = 0; i < 2; i++) {
1448 struct ata_port *ap = host->ports[i];
1449
1450 ap->ops = &piix_sidpr_sata_ops;
1451
1452 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1453 rc = ata_slave_link_init(ap);
1454 if (rc)
1455 return rc;
1456 }
1457 }
1458
1459 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001460}
1461
Tejun Heo2852bcf2009-01-02 12:04:48 +09001462static void piix_iocfg_bit18_quirk(struct ata_host *host)
Tejun Heo43a98f02007-08-23 10:15:18 +09001463{
Jeff Garzik18552562007-10-03 15:15:40 -04001464 static const struct dmi_system_id sysids[] = {
Tejun Heo43a98f02007-08-23 10:15:18 +09001465 {
1466 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1467 * isn't used to boot the system which
1468 * disables the channel.
1469 */
1470 .ident = "M570U",
1471 .matches = {
1472 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1473 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1474 },
1475 },
Jeff Garzik7d051542007-09-01 06:48:52 -04001476
1477 { } /* terminate list */
Tejun Heo43a98f02007-08-23 10:15:18 +09001478 };
Tejun Heo2852bcf2009-01-02 12:04:48 +09001479 struct pci_dev *pdev = to_pci_dev(host->dev);
1480 struct piix_host_priv *hpriv = host->private_data;
Tejun Heo43a98f02007-08-23 10:15:18 +09001481
1482 if (!dmi_check_system(sysids))
1483 return;
1484
1485 /* The datasheet says that bit 18 is NOOP but certain systems
1486 * seem to use it to disable a channel. Clear the bit on the
1487 * affected systems.
1488 */
Tejun Heo2852bcf2009-01-02 12:04:48 +09001489 if (hpriv->saved_iocfg & (1 << 18)) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001490 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
Tejun Heo2852bcf2009-01-02 12:04:48 +09001491 pci_write_config_dword(pdev, PIIX_IOCFG,
1492 hpriv->saved_iocfg & ~(1 << 18));
Tejun Heo43a98f02007-08-23 10:15:18 +09001493 }
1494}
1495
Rafael J. Wysocki5f451fe2009-01-19 20:59:22 +01001496static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1497{
1498 static const struct dmi_system_id broken_systems[] = {
1499 {
1500 .ident = "HP Compaq 2510p",
1501 .matches = {
1502 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1503 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1504 },
1505 /* PCI slot number of the controller */
1506 .driver_data = (void *)0x1FUL,
1507 },
Ville Syrjala65e31642009-05-19 01:37:44 +03001508 {
1509 .ident = "HP Compaq nc6000",
1510 .matches = {
1511 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1512 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1513 },
1514 /* PCI slot number of the controller */
1515 .driver_data = (void *)0x1FUL,
1516 },
Rafael J. Wysocki5f451fe2009-01-19 20:59:22 +01001517
1518 { } /* terminate list */
1519 };
1520 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1521
1522 if (dmi) {
1523 unsigned long slot = (unsigned long)dmi->driver_data;
1524 /* apply the quirk only to on-board controllers */
1525 return slot == PCI_SLOT(pdev->devfn);
1526 }
1527
1528 return false;
1529}
1530
Andy Whitcroftcd006082012-05-04 22:15:11 +01001531static int prefer_ms_hyperv = 1;
1532module_param(prefer_ms_hyperv, int, 0);
1533
1534static void piix_ignore_devices_quirk(struct ata_host *host)
1535{
1536#if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1537 static const struct dmi_system_id ignore_hyperv[] = {
1538 {
1539 /* On Hyper-V hypervisors the disks are exposed on
1540 * both the emulated SATA controller and on the
1541 * paravirtualised drivers. The CD/DVD devices
1542 * are only exposed on the emulated controller.
1543 * Request we ignore ATA devices on this host.
1544 */
1545 .ident = "Hyper-V Virtual Machine",
1546 .matches = {
1547 DMI_MATCH(DMI_SYS_VENDOR,
1548 "Microsoft Corporation"),
1549 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1550 },
1551 },
1552 { } /* terminate list */
1553 };
Olaf Heringd9904342012-09-18 17:48:01 +02001554 static const struct dmi_system_id allow_virtual_pc[] = {
1555 {
1556 /* In MS Virtual PC guests the DMI ident is nearly
1557 * identical to a Hyper-V guest. One difference is the
1558 * product version which is used here to identify
1559 * a Virtual PC guest. This entry allows ata_piix to
1560 * drive the emulated hardware.
1561 */
1562 .ident = "MS Virtual PC 2007",
1563 .matches = {
1564 DMI_MATCH(DMI_SYS_VENDOR,
1565 "Microsoft Corporation"),
1566 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1567 DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
1568 },
1569 },
1570 { } /* terminate list */
1571 };
1572 const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv);
1573 const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
Andy Whitcroftcd006082012-05-04 22:15:11 +01001574
Olaf Heringd9904342012-09-18 17:48:01 +02001575 if (ignore && !allow && prefer_ms_hyperv) {
Andy Whitcroftcd006082012-05-04 22:15:11 +01001576 host->flags |= ATA_HOST_IGNORE_ATA;
1577 dev_info(host->dev, "%s detected, ATA device ignore set\n",
Olaf Heringd9904342012-09-18 17:48:01 +02001578 ignore->ident);
Andy Whitcroftcd006082012-05-04 22:15:11 +01001579 }
1580#endif
1581}
1582
Alan Coxc621b142005-12-08 19:22:28 +00001583/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001584 * piix_init_one - Register PIIX ATA PCI device with kernel services
1585 * @pdev: PCI device to register
1586 * @ent: Entry in piix_pci_tbl matching with @pdev
1587 *
1588 * Called from kernel PCI layer. We probe for combined mode (sigh),
1589 * and then hand over control to libata, for it to do the rest.
1590 *
1591 * LOCKING:
1592 * Inherited from PCI layer (may sleep).
1593 *
1594 * RETURNS:
1595 * Zero on success, or -ERRNO value.
1596 */
1597
Greg Kroah-Hartman0ec24912012-12-21 13:19:58 -08001598static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001599{
Tejun Heo24dc5f32007-01-20 16:00:28 +09001600 struct device *dev = &pdev->dev;
Tejun Heod33f58b2006-03-01 01:25:39 +09001601 struct ata_port_info port_info[2];
Tejun Heo1626aeb2007-05-04 12:43:58 +02001602 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
Tejun Heoa97c40062010-09-01 17:50:08 +02001603 struct scsi_host_template *sht = &piix_sht;
Jeff Garzikcca39742006-08-24 03:19:22 -04001604 unsigned long port_flags;
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001605 struct ata_host *host;
1606 struct piix_host_priv *hpriv;
1607 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608
Joe Perches06296a12011-04-15 15:52:00 -07001609 ata_print_version_once(&pdev->dev, DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001610
Alan Cox347979a2009-05-06 17:10:08 +01001611 /* no hotplugging support for later devices (FIXME) */
1612 if (!in_module_init && ent->driver_data >= ich5_sata)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613 return -ENODEV;
1614
Rafael J. Wysocki5f451fe2009-01-19 20:59:22 +01001615 if (piix_broken_system_poweroff(pdev)) {
1616 piix_port_info[ent->driver_data].flags |=
1617 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1618 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1619 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1620 "on poweroff and hibernation\n");
1621 }
1622
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001623 port_info[0] = piix_port_info[ent->driver_data];
1624 port_info[1] = piix_port_info[ent->driver_data];
1625
1626 port_flags = port_info[0].flags;
1627
1628 /* enable device and prepare host */
1629 rc = pcim_enable_device(pdev);
1630 if (rc)
1631 return rc;
1632
Tejun Heo2852bcf2009-01-02 12:04:48 +09001633 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1634 if (!hpriv)
1635 return -ENOMEM;
1636
1637 /* Save IOCFG, this will be used for cable detection, quirk
1638 * detection and restoration on detach. This is necessary
1639 * because some ACPI implementations mess up cable related
1640 * bits on _STM. Reported on kernel bz#11879.
1641 */
1642 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1643
Tejun Heo5016d7d2008-03-26 15:46:58 +09001644 /* ICH6R may be driven by either ata_piix or ahci driver
1645 * regardless of BIOS configuration. Make sure AHCI mode is
1646 * off.
1647 */
1648 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
Stephen Hemmingerda3ceb22008-09-08 09:31:39 -07001649 rc = piix_disable_ahci(pdev);
Tejun Heo5016d7d2008-03-26 15:46:58 +09001650 if (rc)
1651 return rc;
1652 }
1653
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001654 /* SATA map init can change port_info, do it before prepping host */
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001655 if (port_flags & ATA_FLAG_SATA)
1656 hpriv->map = piix_init_sata_map(pdev, port_info,
1657 piix_map_db_table[ent->driver_data]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001658
Tejun Heo1c5afdf2010-05-19 22:10:22 +02001659 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001660 if (rc)
1661 return rc;
1662 host->private_data = hpriv;
Tejun Heoff0fc142005-12-18 17:17:07 +09001663
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001664 /* initialize controller */
Tejun Heoc7290722008-01-18 18:36:30 +09001665 if (port_flags & ATA_FLAG_SATA) {
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001666 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
Tejun Heobe77e432008-07-31 17:02:44 +09001667 rc = piix_init_sidpr(host);
1668 if (rc)
1669 return rc;
Tejun Heoa97c40062010-09-01 17:50:08 +02001670 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1671 sht = &piix_sidpr_sht;
Tejun Heoc7290722008-01-18 18:36:30 +09001672 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001673
Tejun Heo43a98f02007-08-23 10:15:18 +09001674 /* apply IOCFG bit18 quirk */
Tejun Heo2852bcf2009-01-02 12:04:48 +09001675 piix_iocfg_bit18_quirk(host);
Tejun Heo43a98f02007-08-23 10:15:18 +09001676
Linus Torvalds1da177e2005-04-16 15:20:36 -07001677 /* On ICH5, some BIOSen disable the interrupt using the
1678 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1679 * On ICH6, this bit has the same effect, but only when
1680 * MSI is disabled (and it is disabled, as we don't use
1681 * message-signalled interrupts currently).
1682 */
Jeff Garzikcca39742006-08-24 03:19:22 -04001683 if (port_flags & PIIX_FLAG_CHECKINTR)
Brett M Russa04ce0f2005-08-15 15:23:41 -04001684 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001685
Alan Coxc621b142005-12-08 19:22:28 +00001686 if (piix_check_450nx_errata(pdev)) {
1687 /* This writes into the master table but it does not
1688 really matter for this errata as we will apply it to
1689 all the PIIX devices on the board */
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001690 host->ports[0]->mwdma_mask = 0;
1691 host->ports[0]->udma_mask = 0;
1692 host->ports[1]->mwdma_mask = 0;
1693 host->ports[1]->udma_mask = 0;
Alan Coxc621b142005-12-08 19:22:28 +00001694 }
Arjan van de Ven517d3cc2009-05-13 15:02:42 +01001695 host->flags |= ATA_HOST_PARALLEL_SCAN;
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001696
Andy Whitcroftcd006082012-05-04 22:15:11 +01001697 /* Allow hosts to specify device types to ignore when scanning. */
1698 piix_ignore_devices_quirk(host);
1699
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001700 pci_set_master(pdev);
Tejun Heoa97c40062010-09-01 17:50:08 +02001701 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001702}
1703
Tejun Heo2852bcf2009-01-02 12:04:48 +09001704static void piix_remove_one(struct pci_dev *pdev)
1705{
1706 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1707 struct piix_host_priv *hpriv = host->private_data;
1708
1709 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1710
1711 ata_pci_remove_one(pdev);
1712}
1713
Bartlomiej Zolnierkiewiczf295be22012-11-30 11:56:04 +01001714static struct pci_driver piix_pci_driver = {
1715 .name = DRV_NAME,
1716 .id_table = piix_pci_tbl,
1717 .probe = piix_init_one,
1718 .remove = piix_remove_one,
1719#ifdef CONFIG_PM
1720 .suspend = piix_pci_device_suspend,
1721 .resume = piix_pci_device_resume,
1722#endif
1723};
1724
Linus Torvalds1da177e2005-04-16 15:20:36 -07001725static int __init piix_init(void)
1726{
1727 int rc;
1728
Pavel Roskinb7887192006-08-10 18:13:18 +09001729 DPRINTK("pci_register_driver\n");
1730 rc = pci_register_driver(&piix_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001731 if (rc)
1732 return rc;
1733
1734 in_module_init = 0;
1735
1736 DPRINTK("done\n");
1737 return 0;
1738}
1739
Linus Torvalds1da177e2005-04-16 15:20:36 -07001740static void __exit piix_exit(void)
1741{
1742 pci_unregister_driver(&piix_pci_driver);
1743}
1744
1745module_init(piix_init);
1746module_exit(piix_exit);