blob: 11c61b4d81491767ad74fc995df8c1f5362ea4ca [file] [log] [blame]
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -03001/* Intel i7 core/Nehalem Memory Controller kernel module
2 *
3 * This driver supports yhe memory controllers found on the Intel
4 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
5 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
6 * and Westmere-EP.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03007 *
8 * This file may be distributed under the terms of the
9 * GNU General Public License version 2 only.
10 *
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -030011 * Copyright (c) 2009-2010 by:
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030012 * Mauro Carvalho Chehab <mchehab@redhat.com>
13 *
14 * Red Hat Inc. http://www.redhat.com
15 *
16 * Forked and adapted from the i5400_edac driver
17 *
18 * Based on the following public Intel datasheets:
19 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
20 * Datasheet, Volume 2:
21 * http://download.intel.com/design/processor/datashts/320835.pdf
22 * Intel Xeon Processor 5500 Series Datasheet Volume 2
23 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
24 * also available at:
25 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
26 */
27
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030028#include <linux/module.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/pci_ids.h>
32#include <linux/slab.h>
Randy Dunlap3b918c12009-11-08 01:36:40 -020033#include <linux/delay.h>
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030034#include <linux/edac.h>
35#include <linux/mmzone.h>
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -030036#include <linux/edac_mce.h>
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -030037#include <linux/smp.h>
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -030038#include <asm/processor.h>
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030039
40#include "edac_core.h"
41
Mauro Carvalho Chehab18c29002010-08-10 18:33:27 -030042/* Static vars */
43static LIST_HEAD(i7core_edac_list);
44static DEFINE_MUTEX(i7core_edac_lock);
45static int probed;
46
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030047/*
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -030048 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
49 * registers start at bus 255, and are not reported by BIOS.
50 * We currently find devices with only 2 sockets. In order to support more QPI
51 * Quick Path Interconnect, just increment this number.
52 */
53#define MAX_SOCKET_BUSES 2
54
55
56/*
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030057 * Alter this version for the module when modifications are made
58 */
59#define I7CORE_REVISION " Ver: 1.0.0 " __DATE__
60#define EDAC_MOD_STR "i7core_edac"
61
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030062/*
63 * Debug macros
64 */
65#define i7core_printk(level, fmt, arg...) \
66 edac_printk(level, "i7core", fmt, ##arg)
67
68#define i7core_mc_printk(mci, level, fmt, arg...) \
69 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
70
71/*
72 * i7core Memory Controller Registers
73 */
74
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -030075 /* OFFSETS for Device 0 Function 0 */
76
77#define MC_CFG_CONTROL 0x90
78
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030079 /* OFFSETS for Device 3 Function 0 */
80
81#define MC_CONTROL 0x48
82#define MC_STATUS 0x4c
83#define MC_MAX_DOD 0x64
84
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -030085/*
86 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
87 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
88 */
89
90#define MC_TEST_ERR_RCV1 0x60
91 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
92
93#define MC_TEST_ERR_RCV0 0x64
94 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
95 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
96
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -030097/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
98#define MC_COR_ECC_CNT_0 0x80
99#define MC_COR_ECC_CNT_1 0x84
100#define MC_COR_ECC_CNT_2 0x88
101#define MC_COR_ECC_CNT_3 0x8c
102#define MC_COR_ECC_CNT_4 0x90
103#define MC_COR_ECC_CNT_5 0x94
104
105#define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
106#define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
107
108
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300109 /* OFFSETS for Devices 4,5 and 6 Function 0 */
110
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300111#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
112 #define THREE_DIMMS_PRESENT (1 << 24)
113 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
114 #define QUAD_RANK_PRESENT (1 << 22)
115 #define REGISTERED_DIMM (1 << 15)
116
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300117#define MC_CHANNEL_MAPPER 0x60
118 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
119 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
120
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300121#define MC_CHANNEL_RANK_PRESENT 0x7c
122 #define RANK_PRESENT_MASK 0xffff
123
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300124#define MC_CHANNEL_ADDR_MATCH 0xf0
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300125#define MC_CHANNEL_ERROR_MASK 0xf8
126#define MC_CHANNEL_ERROR_INJECT 0xfc
127 #define INJECT_ADDR_PARITY 0x10
128 #define INJECT_ECC 0x08
129 #define MASK_CACHELINE 0x06
130 #define MASK_FULL_CACHELINE 0x06
131 #define MASK_MSB32_CACHELINE 0x04
132 #define MASK_LSB32_CACHELINE 0x02
133 #define NO_MASK_CACHELINE 0x00
134 #define REPEAT_EN 0x01
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300135
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300136 /* OFFSETS for Devices 4,5 and 6 Function 1 */
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -0300137
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300138#define MC_DOD_CH_DIMM0 0x48
139#define MC_DOD_CH_DIMM1 0x4c
140#define MC_DOD_CH_DIMM2 0x50
141 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
142 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
143 #define DIMM_PRESENT_MASK (1 << 9)
144 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300145 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
146 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
147 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
148 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300149 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300150 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300151 #define MC_DOD_NUMCOL_MASK 3
152 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300153
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300154#define MC_RANK_PRESENT 0x7c
155
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300156#define MC_SAG_CH_0 0x80
157#define MC_SAG_CH_1 0x84
158#define MC_SAG_CH_2 0x88
159#define MC_SAG_CH_3 0x8c
160#define MC_SAG_CH_4 0x90
161#define MC_SAG_CH_5 0x94
162#define MC_SAG_CH_6 0x98
163#define MC_SAG_CH_7 0x9c
164
165#define MC_RIR_LIMIT_CH_0 0x40
166#define MC_RIR_LIMIT_CH_1 0x44
167#define MC_RIR_LIMIT_CH_2 0x48
168#define MC_RIR_LIMIT_CH_3 0x4C
169#define MC_RIR_LIMIT_CH_4 0x50
170#define MC_RIR_LIMIT_CH_5 0x54
171#define MC_RIR_LIMIT_CH_6 0x58
172#define MC_RIR_LIMIT_CH_7 0x5C
173#define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
174
175#define MC_RIR_WAY_CH 0x80
176 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
177 #define MC_RIR_WAY_RANK_MASK 0x7
178
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300179/*
180 * i7core structs
181 */
182
183#define NUM_CHANS 3
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300184#define MAX_DIMMS 3 /* Max DIMMS per channel */
185#define MAX_MCR_FUNC 4
186#define MAX_CHAN_FUNC 3
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300187
188struct i7core_info {
189 u32 mc_control;
190 u32 mc_status;
191 u32 max_dod;
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300192 u32 ch_map;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300193};
194
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300195
196struct i7core_inject {
197 int enable;
198
199 u32 section;
200 u32 type;
201 u32 eccmask;
202
203 /* Error address mask */
204 int channel, dimm, rank, bank, page, col;
205};
206
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300207struct i7core_channel {
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300208 u32 ranks;
209 u32 dimms;
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300210};
211
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300212struct pci_id_descr {
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300213 int dev;
214 int func;
215 int dev_id;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300216 int optional;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300217};
218
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300219struct pci_id_table {
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300220 const struct pci_id_descr *descr;
221 int n_devs;
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300222};
223
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300224struct i7core_dev {
225 struct list_head list;
226 u8 socket;
227 struct pci_dev **pdev;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300228 int n_devs;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300229 struct mem_ctl_info *mci;
230};
231
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300232struct i7core_pvt {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300233 struct pci_dev *pci_noncore;
234 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
235 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
236
237 struct i7core_dev *i7core_dev;
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300238
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300239 struct i7core_info info;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300240 struct i7core_inject inject;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300241 struct i7core_channel channel[NUM_CHANS];
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300242
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300243 int channels; /* Number of active channels */
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300244
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300245 int ce_count_available;
246 int csrow_map[NUM_CHANS][MAX_DIMMS];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300247
248 /* ECC corrected errors counts per udimm */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300249 unsigned long udimm_ce_count[MAX_DIMMS];
250 int udimm_last_ce_count[MAX_DIMMS];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300251 /* ECC corrected errors counts per rdimm */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300252 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
253 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300254
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300255 unsigned int is_registered;
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -0300256
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -0300257 /* mcelog glue */
258 struct edac_mce edac_mce;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -0300259
260 /* Fifo double buffers */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -0300261 struct mce mce_entry[MCE_LOG_LEN];
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -0300262 struct mce mce_outentry[MCE_LOG_LEN];
263
264 /* Fifo in/out counters */
265 unsigned mce_in, mce_out;
266
267 /* Count indicator to show errors not got */
268 unsigned mce_overrun;
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -0300269
270 /* Struct to control EDAC polling */
271 struct edac_pci_ctl_info *i7core_pci;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300272};
273
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300274#define PCI_DESCR(device, function, device_id) \
275 .dev = (device), \
276 .func = (function), \
277 .dev_id = (device_id)
278
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300279static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300280 /* Memory controller */
281 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
282 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300283 /* Exists only for RDIMM */
284 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300285 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
286
287 /* Channel 0 */
288 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
289 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
290 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
291 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
292
293 /* Channel 1 */
294 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
295 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
296 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
297 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
298
299 /* Channel 2 */
300 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
301 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
302 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
303 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
Mauro Carvalho Chehab310cbb72009-07-17 00:09:10 -0300304
305 /* Generic Non-core registers */
306 /*
307 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
308 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
309 * the probing code needs to test for the other address in case of
310 * failure of this one
311 */
Mauro Carvalho Chehabfd382652009-10-14 06:07:07 -0300312 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
Mauro Carvalho Chehab310cbb72009-07-17 00:09:10 -0300313
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300314};
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300315
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300316static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300317 { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
318 { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
319 { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
320
321 { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
322 { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
323 { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
324 { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
325
Mauro Carvalho Chehab508fa172009-10-14 13:44:37 -0300326 { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
327 { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
328 { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
329 { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300330
Mauro Carvalho Chehabf05da2f2009-10-14 13:31:06 -0300331 /*
332 * This is the PCI device has an alternate address on some
333 * processors like Core i7 860
334 */
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300335 { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
336};
337
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300338static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300339 /* Memory controller */
340 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
341 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
342 /* Exists only for RDIMM */
343 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
344 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
345
346 /* Channel 0 */
347 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
348 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
349 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
350 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
351
352 /* Channel 1 */
353 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
354 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
355 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
356 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
357
358 /* Channel 2 */
359 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
360 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
361 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
362 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
363
364 /* Generic Non-core registers */
365 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
366
367};
368
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300369#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
370static const struct pci_id_table pci_dev_table[] = {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300371 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
372 PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
373 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
374};
375
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300376/*
377 * pci_device_id table for which devices we are looking for
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300378 */
379static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -0300380 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
Mauro Carvalho Chehabf05da2f2009-10-14 13:31:06 -0300381 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300382 {0,} /* 0 terminated list. */
383};
384
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300385/****************************************************************************
386 Anciliary status routines
387 ****************************************************************************/
388
389 /* MC_CONTROL bits */
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300390#define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
391#define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300392
393 /* MC_STATUS bits */
Keith Mannthey61053fd2009-09-02 23:46:59 -0300394#define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300395#define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300396
397 /* MC_MAX_DOD read functions */
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300398static inline int numdimms(u32 dimms)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300399{
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300400 return (dimms & 0x3) + 1;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300401}
402
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300403static inline int numrank(u32 rank)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300404{
405 static int ranks[4] = { 1, 2, 4, -EINVAL };
406
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300407 return ranks[rank & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300408}
409
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300410static inline int numbank(u32 bank)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300411{
412 static int banks[4] = { 4, 8, 16, -EINVAL };
413
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300414 return banks[bank & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300415}
416
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300417static inline int numrow(u32 row)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300418{
419 static int rows[8] = {
420 1 << 12, 1 << 13, 1 << 14, 1 << 15,
421 1 << 16, -EINVAL, -EINVAL, -EINVAL,
422 };
423
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300424 return rows[row & 0x7];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300425}
426
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300427static inline int numcol(u32 col)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300428{
429 static int cols[8] = {
430 1 << 10, 1 << 11, 1 << 12, -EINVAL,
431 };
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300432 return cols[col & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300433}
434
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300435static struct i7core_dev *get_i7core_dev(u8 socket)
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300436{
437 struct i7core_dev *i7core_dev;
438
439 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
440 if (i7core_dev->socket == socket)
441 return i7core_dev;
442 }
443
444 return NULL;
445}
446
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300447/****************************************************************************
448 Memory check routines
449 ****************************************************************************/
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300450static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
451 unsigned func)
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300452{
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300453 struct i7core_dev *i7core_dev = get_i7core_dev(socket);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300454 int i;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300455
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300456 if (!i7core_dev)
457 return NULL;
458
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300459 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300460 if (!i7core_dev->pdev[i])
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300461 continue;
462
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300463 if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
464 PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
465 return i7core_dev->pdev[i];
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300466 }
467 }
468
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300469 return NULL;
470}
471
Mauro Carvalho Chehabec6df242009-07-18 10:44:30 -0300472/**
473 * i7core_get_active_channels() - gets the number of channels and csrows
474 * @socket: Quick Path Interconnect socket
475 * @channels: Number of channels that will be returned
476 * @csrows: Number of csrows found
477 *
478 * Since EDAC core needs to know in advance the number of available channels
479 * and csrows, in order to allocate memory for csrows/channels, it is needed
480 * to run two similar steps. At the first step, implemented on this function,
481 * it checks the number of csrows/channels present at one socket.
482 * this is used in order to properly allocate the size of mci components.
483 *
484 * It should be noticed that none of the current available datasheets explain
485 * or even mention how csrows are seen by the memory controller. So, we need
486 * to add a fake description for csrows.
487 * So, this driver is attributing one DIMM memory for one csrow.
488 */
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300489static int i7core_get_active_channels(const u8 socket, unsigned *channels,
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300490 unsigned *csrows)
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300491{
492 struct pci_dev *pdev = NULL;
493 int i, j;
494 u32 status, control;
495
496 *channels = 0;
497 *csrows = 0;
498
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300499 pdev = get_pdev_slot_func(socket, 3, 0);
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -0300500 if (!pdev) {
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300501 i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
502 socket);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300503 return -ENODEV;
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -0300504 }
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300505
506 /* Device 3 function 0 reads */
507 pci_read_config_dword(pdev, MC_STATUS, &status);
508 pci_read_config_dword(pdev, MC_CONTROL, &control);
509
510 for (i = 0; i < NUM_CHANS; i++) {
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300511 u32 dimm_dod[3];
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300512 /* Check if the channel is active */
513 if (!(control & (1 << (8 + i))))
514 continue;
515
516 /* Check if the channel is disabled */
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300517 if (status & (1 << i))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300518 continue;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300519
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300520 pdev = get_pdev_slot_func(socket, i + 4, 1);
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300521 if (!pdev) {
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300522 i7core_printk(KERN_ERR, "Couldn't find socket %d "
523 "fn %d.%d!!!\n",
524 socket, i + 4, 1);
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300525 return -ENODEV;
526 }
527 /* Devices 4-6 function 1 */
528 pci_read_config_dword(pdev,
529 MC_DOD_CH_DIMM0, &dimm_dod[0]);
530 pci_read_config_dword(pdev,
531 MC_DOD_CH_DIMM1, &dimm_dod[1]);
532 pci_read_config_dword(pdev,
533 MC_DOD_CH_DIMM2, &dimm_dod[2]);
534
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300535 (*channels)++;
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300536
537 for (j = 0; j < 3; j++) {
538 if (!DIMM_PRESENT(dimm_dod[j]))
539 continue;
540 (*csrows)++;
541 }
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300542 }
543
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -0300544 debugf0("Number of active channels on socket %d: %d\n",
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300545 socket, *channels);
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300546
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300547 return 0;
548}
549
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300550static int get_dimm_config(const struct mem_ctl_info *mci, int *csrow)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300551{
552 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300553 struct csrow_info *csr;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300554 struct pci_dev *pdev;
Mauro Carvalho Chehabba6c5c62009-07-15 09:02:32 -0300555 int i, j;
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300556 unsigned long last_page = 0;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300557 enum edac_type mode;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300558 enum mem_type mtype;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300559
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300560 /* Get data from the MC register, function 0 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300561 pdev = pvt->pci_mcr[0];
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300562 if (!pdev)
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300563 return -ENODEV;
564
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300565 /* Device 3 function 0 reads */
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300566 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
567 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
568 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
569 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300570
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300571 debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
Mauro Carvalho Chehab4af91882009-09-24 09:58:26 -0300572 pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300573 pvt->info.max_dod, pvt->info.ch_map);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300574
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300575 if (ECC_ENABLED(pvt)) {
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300576 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300577 if (ECCx8(pvt))
578 mode = EDAC_S8ECD8ED;
579 else
580 mode = EDAC_S4ECD4ED;
581 } else {
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300582 debugf0("ECC disabled\n");
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300583 mode = EDAC_NONE;
584 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300585
586 /* FIXME: need to handle the error codes */
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300587 debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
588 "x%x x 0x%x\n",
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300589 numdimms(pvt->info.max_dod),
590 numrank(pvt->info.max_dod >> 2),
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300591 numbank(pvt->info.max_dod >> 4),
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300592 numrow(pvt->info.max_dod >> 6),
593 numcol(pvt->info.max_dod >> 9));
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300594
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300595 for (i = 0; i < NUM_CHANS; i++) {
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300596 u32 data, dimm_dod[3], value[8];
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300597
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300598 if (!pvt->pci_ch[i][0])
599 continue;
600
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300601 if (!CH_ACTIVE(pvt, i)) {
602 debugf0("Channel %i is not active\n", i);
603 continue;
604 }
605 if (CH_DISABLED(pvt, i)) {
606 debugf0("Channel %i is disabled\n", i);
607 continue;
608 }
609
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300610 /* Devices 4-6 function 0 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300611 pci_read_config_dword(pvt->pci_ch[i][0],
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300612 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
613
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300614 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300615 4 : 2;
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300616
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300617 if (data & REGISTERED_DIMM)
618 mtype = MEM_RDDR3;
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -0300619 else
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300620 mtype = MEM_DDR3;
621#if 0
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300622 if (data & THREE_DIMMS_PRESENT)
623 pvt->channel[i].dimms = 3;
624 else if (data & SINGLE_QUAD_RANK_PRESENT)
625 pvt->channel[i].dimms = 1;
626 else
627 pvt->channel[i].dimms = 2;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300628#endif
629
630 /* Devices 4-6 function 1 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300631 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300632 MC_DOD_CH_DIMM0, &dimm_dod[0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300633 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300634 MC_DOD_CH_DIMM1, &dimm_dod[1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300635 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300636 MC_DOD_CH_DIMM2, &dimm_dod[2]);
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300637
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300638 debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300639 "%d ranks, %cDIMMs\n",
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300640 i,
641 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
642 data,
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300643 pvt->channel[i].ranks,
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300644 (data & REGISTERED_DIMM) ? 'R' : 'U');
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300645
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300646 for (j = 0; j < 3; j++) {
647 u32 banks, ranks, rows, cols;
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300648 u32 size, npages;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300649
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300650 if (!DIMM_PRESENT(dimm_dod[j]))
651 continue;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300652
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300653 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
654 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
655 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
656 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300657
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300658 /* DDR3 has 8 I/O banks */
659 size = (rows * cols * banks * ranks) >> (20 - 3);
660
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300661 pvt->channel[i].dimms++;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300662
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300663 debugf0("\tdimm %d %d Mb offset: %x, "
664 "bank: %d, rank: %d, row: %#x, col: %#x\n",
665 j, size,
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300666 RANKOFFSET(dimm_dod[j]),
667 banks, ranks, rows, cols);
668
Mauro Carvalho Chehabe9144602010-08-10 20:26:35 -0300669 npages = MiB_TO_PAGES(size);
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300670
Mauro Carvalho Chehabba6c5c62009-07-15 09:02:32 -0300671 csr = &mci->csrows[*csrow];
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300672 csr->first_page = last_page + 1;
673 last_page += npages;
674 csr->last_page = last_page;
675 csr->nr_pages = npages;
676
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300677 csr->page_mask = 0;
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300678 csr->grain = 8;
Mauro Carvalho Chehabba6c5c62009-07-15 09:02:32 -0300679 csr->csrow_idx = *csrow;
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300680 csr->nr_channels = 1;
681
682 csr->channels[0].chan_idx = i;
683 csr->channels[0].ce_count = 0;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300684
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300685 pvt->csrow_map[i][j] = *csrow;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300686
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300687 switch (banks) {
688 case 4:
689 csr->dtype = DEV_X4;
690 break;
691 case 8:
692 csr->dtype = DEV_X8;
693 break;
694 case 16:
695 csr->dtype = DEV_X16;
696 break;
697 default:
698 csr->dtype = DEV_UNKNOWN;
699 }
700
701 csr->edac_mode = mode;
702 csr->mtype = mtype;
703
Mauro Carvalho Chehabba6c5c62009-07-15 09:02:32 -0300704 (*csrow)++;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300705 }
706
707 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
708 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
709 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
710 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
711 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
712 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
713 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
714 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300715 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300716 for (j = 0; j < 8; j++)
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300717 debugf1("\t\t%#x\t%#x\t%#x\n",
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300718 (value[j] >> 27) & 0x1,
719 (value[j] >> 24) & 0x7,
720 (value[j] && ((1 << 24) - 1)));
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300721 }
722
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300723 return 0;
724}
725
726/****************************************************************************
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300727 Error insertion routines
728 ****************************************************************************/
729
730/* The i7core has independent error injection features per channel.
731 However, to have a simpler code, we don't allow enabling error injection
732 on more than one channel.
733 Also, since a change at an inject parameter will be applied only at enable,
734 we're disabling error injection on all write calls to the sysfs nodes that
735 controls the error code injection.
736 */
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300737static int disable_inject(const struct mem_ctl_info *mci)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300738{
739 struct i7core_pvt *pvt = mci->pvt_info;
740
741 pvt->inject.enable = 0;
742
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300743 if (!pvt->pci_ch[pvt->inject.channel][0])
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300744 return -ENODEV;
745
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300746 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300747 MC_CHANNEL_ERROR_INJECT, 0);
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300748
749 return 0;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300750}
751
752/*
753 * i7core inject inject.section
754 *
755 * accept and store error injection inject.section value
756 * bit 0 - refers to the lower 32-byte half cacheline
757 * bit 1 - refers to the upper 32-byte half cacheline
758 */
759static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
760 const char *data, size_t count)
761{
762 struct i7core_pvt *pvt = mci->pvt_info;
763 unsigned long value;
764 int rc;
765
766 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300767 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300768
769 rc = strict_strtoul(data, 10, &value);
770 if ((rc < 0) || (value > 3))
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300771 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300772
773 pvt->inject.section = (u32) value;
774 return count;
775}
776
777static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
778 char *data)
779{
780 struct i7core_pvt *pvt = mci->pvt_info;
781 return sprintf(data, "0x%08x\n", pvt->inject.section);
782}
783
784/*
785 * i7core inject.type
786 *
787 * accept and store error injection inject.section value
788 * bit 0 - repeat enable - Enable error repetition
789 * bit 1 - inject ECC error
790 * bit 2 - inject parity error
791 */
792static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
793 const char *data, size_t count)
794{
795 struct i7core_pvt *pvt = mci->pvt_info;
796 unsigned long value;
797 int rc;
798
799 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300800 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300801
802 rc = strict_strtoul(data, 10, &value);
803 if ((rc < 0) || (value > 7))
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300804 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300805
806 pvt->inject.type = (u32) value;
807 return count;
808}
809
810static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
811 char *data)
812{
813 struct i7core_pvt *pvt = mci->pvt_info;
814 return sprintf(data, "0x%08x\n", pvt->inject.type);
815}
816
817/*
818 * i7core_inject_inject.eccmask_store
819 *
820 * The type of error (UE/CE) will depend on the inject.eccmask value:
821 * Any bits set to a 1 will flip the corresponding ECC bit
822 * Correctable errors can be injected by flipping 1 bit or the bits within
823 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
824 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
825 * uncorrectable error to be injected.
826 */
827static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
828 const char *data, size_t count)
829{
830 struct i7core_pvt *pvt = mci->pvt_info;
831 unsigned long value;
832 int rc;
833
834 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300835 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300836
837 rc = strict_strtoul(data, 10, &value);
838 if (rc < 0)
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300839 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300840
841 pvt->inject.eccmask = (u32) value;
842 return count;
843}
844
845static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
846 char *data)
847{
848 struct i7core_pvt *pvt = mci->pvt_info;
849 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
850}
851
852/*
853 * i7core_addrmatch
854 *
855 * The type of error (UE/CE) will depend on the inject.eccmask value:
856 * Any bits set to a 1 will flip the corresponding ECC bit
857 * Correctable errors can be injected by flipping 1 bit or the bits within
858 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
859 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
860 * uncorrectable error to be injected.
861 */
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300862
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300863#define DECLARE_ADDR_MATCH(param, limit) \
864static ssize_t i7core_inject_store_##param( \
865 struct mem_ctl_info *mci, \
866 const char *data, size_t count) \
867{ \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300868 struct i7core_pvt *pvt; \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300869 long value; \
870 int rc; \
871 \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300872 debugf1("%s()\n", __func__); \
873 pvt = mci->pvt_info; \
874 \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300875 if (pvt->inject.enable) \
876 disable_inject(mci); \
877 \
Mauro Carvalho Chehab4f87fad2009-10-04 11:54:56 -0300878 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300879 value = -1; \
880 else { \
881 rc = strict_strtoul(data, 10, &value); \
882 if ((rc < 0) || (value >= limit)) \
883 return -EIO; \
884 } \
885 \
886 pvt->inject.param = value; \
887 \
888 return count; \
889} \
890 \
891static ssize_t i7core_inject_show_##param( \
892 struct mem_ctl_info *mci, \
893 char *data) \
894{ \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300895 struct i7core_pvt *pvt; \
896 \
897 pvt = mci->pvt_info; \
898 debugf1("%s() pvt=%p\n", __func__, pvt); \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300899 if (pvt->inject.param < 0) \
900 return sprintf(data, "any\n"); \
901 else \
902 return sprintf(data, "%d\n", pvt->inject.param);\
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300903}
904
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300905#define ATTR_ADDR_MATCH(param) \
906 { \
907 .attr = { \
908 .name = #param, \
909 .mode = (S_IRUGO | S_IWUSR) \
910 }, \
911 .show = i7core_inject_show_##param, \
912 .store = i7core_inject_store_##param, \
913 }
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300914
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300915DECLARE_ADDR_MATCH(channel, 3);
916DECLARE_ADDR_MATCH(dimm, 3);
917DECLARE_ADDR_MATCH(rank, 4);
918DECLARE_ADDR_MATCH(bank, 32);
919DECLARE_ADDR_MATCH(page, 0x10000);
920DECLARE_ADDR_MATCH(col, 0x4000);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300921
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300922static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300923{
924 u32 read;
925 int count;
926
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300927 debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
928 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
929 where, val);
930
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300931 for (count = 0; count < 10; count++) {
932 if (count)
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -0300933 msleep(100);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300934 pci_write_config_dword(dev, where, val);
935 pci_read_config_dword(dev, where, &read);
936
937 if (read == val)
938 return 0;
939 }
940
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300941 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
942 "write=%08x. Read=%08x\n",
943 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
944 where, val, read);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300945
946 return -EINVAL;
947}
948
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300949/*
950 * This routine prepares the Memory Controller for error injection.
951 * The error will be injected when some process tries to write to the
952 * memory that matches the given criteria.
953 * The criteria can be set in terms of a mask where dimm, rank, bank, page
954 * and col can be specified.
955 * A -1 value for any of the mask items will make the MCU to ignore
956 * that matching criteria for error injection.
957 *
958 * It should be noticed that the error will only happen after a write operation
959 * on a memory that matches the condition. if REPEAT_EN is not enabled at
960 * inject mask, then it will produce just one error. Otherwise, it will repeat
961 * until the injectmask would be cleaned.
962 *
963 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
964 * is reliable enough to check if the MC is using the
965 * three channels. However, this is not clear at the datasheet.
966 */
967static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
968 const char *data, size_t count)
969{
970 struct i7core_pvt *pvt = mci->pvt_info;
971 u32 injectmask;
972 u64 mask = 0;
973 int rc;
974 long enable;
975
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300976 if (!pvt->pci_ch[pvt->inject.channel][0])
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300977 return 0;
978
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300979 rc = strict_strtoul(data, 10, &enable);
980 if ((rc < 0))
981 return 0;
982
983 if (enable) {
984 pvt->inject.enable = 1;
985 } else {
986 disable_inject(mci);
987 return count;
988 }
989
990 /* Sets pvt->inject.dimm mask */
991 if (pvt->inject.dimm < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200992 mask |= 1LL << 41;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300993 else {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300994 if (pvt->channel[pvt->inject.channel].dimms > 2)
Alan Cox486dd092009-11-08 01:34:27 -0200995 mask |= (pvt->inject.dimm & 0x3LL) << 35;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300996 else
Alan Cox486dd092009-11-08 01:34:27 -0200997 mask |= (pvt->inject.dimm & 0x1LL) << 36;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300998 }
999
1000 /* Sets pvt->inject.rank mask */
1001 if (pvt->inject.rank < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001002 mask |= 1LL << 40;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001003 else {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001004 if (pvt->channel[pvt->inject.channel].dimms > 2)
Alan Cox486dd092009-11-08 01:34:27 -02001005 mask |= (pvt->inject.rank & 0x1LL) << 34;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001006 else
Alan Cox486dd092009-11-08 01:34:27 -02001007 mask |= (pvt->inject.rank & 0x3LL) << 34;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001008 }
1009
1010 /* Sets pvt->inject.bank mask */
1011 if (pvt->inject.bank < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001012 mask |= 1LL << 39;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001013 else
Alan Cox486dd092009-11-08 01:34:27 -02001014 mask |= (pvt->inject.bank & 0x15LL) << 30;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001015
1016 /* Sets pvt->inject.page mask */
1017 if (pvt->inject.page < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001018 mask |= 1LL << 38;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001019 else
Alan Cox486dd092009-11-08 01:34:27 -02001020 mask |= (pvt->inject.page & 0xffff) << 14;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001021
1022 /* Sets pvt->inject.column mask */
1023 if (pvt->inject.col < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001024 mask |= 1LL << 37;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001025 else
Alan Cox486dd092009-11-08 01:34:27 -02001026 mask |= (pvt->inject.col & 0x3fff);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001027
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001028 /*
1029 * bit 0: REPEAT_EN
1030 * bits 1-2: MASK_HALF_CACHELINE
1031 * bit 3: INJECT_ECC
1032 * bit 4: INJECT_ADDR_PARITY
1033 */
1034
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001035 injectmask = (pvt->inject.type & 1) |
1036 (pvt->inject.section & 0x3) << 1 |
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001037 (pvt->inject.type & 0x6) << (3 - 1);
1038
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001039 /* Unlock writes to registers - this register is write only */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001040 pci_write_config_dword(pvt->pci_noncore,
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001041 MC_CFG_CONTROL, 0x2);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001042
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001043 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001044 MC_CHANNEL_ADDR_MATCH, mask);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001045 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001046 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
1047
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001048 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001049 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
1050
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001051 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -03001052 MC_CHANNEL_ERROR_INJECT, injectmask);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001053
1054 /*
1055 * This is something undocumented, based on my tests
1056 * Without writing 8 to this register, errors aren't injected. Not sure
1057 * why.
1058 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001059 pci_write_config_dword(pvt->pci_noncore,
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001060 MC_CFG_CONTROL, 8);
1061
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03001062 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
1063 " inject 0x%08x\n",
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001064 mask, pvt->inject.eccmask, injectmask);
1065
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001066
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001067 return count;
1068}
1069
1070static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
1071 char *data)
1072{
1073 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001074 u32 injectmask;
1075
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -03001076 if (!pvt->pci_ch[pvt->inject.channel][0])
1077 return 0;
1078
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001079 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -03001080 MC_CHANNEL_ERROR_INJECT, &injectmask);
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001081
1082 debugf0("Inject error read: 0x%018x\n", injectmask);
1083
1084 if (injectmask & 0x0c)
1085 pvt->inject.enable = 1;
1086
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001087 return sprintf(data, "%d\n", pvt->inject.enable);
1088}
1089
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001090#define DECLARE_COUNTER(param) \
1091static ssize_t i7core_show_counter_##param( \
1092 struct mem_ctl_info *mci, \
1093 char *data) \
1094{ \
1095 struct i7core_pvt *pvt = mci->pvt_info; \
1096 \
1097 debugf1("%s() \n", __func__); \
1098 if (!pvt->ce_count_available || (pvt->is_registered)) \
1099 return sprintf(data, "data unavailable\n"); \
1100 return sprintf(data, "%lu\n", \
1101 pvt->udimm_ce_count[param]); \
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001102}
1103
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001104#define ATTR_COUNTER(param) \
1105 { \
1106 .attr = { \
1107 .name = __stringify(udimm##param), \
1108 .mode = (S_IRUGO | S_IWUSR) \
1109 }, \
1110 .show = i7core_show_counter_##param \
1111 }
1112
1113DECLARE_COUNTER(0);
1114DECLARE_COUNTER(1);
1115DECLARE_COUNTER(2);
1116
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001117/*
1118 * Sysfs struct
1119 */
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001120
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001121static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001122 ATTR_ADDR_MATCH(channel),
1123 ATTR_ADDR_MATCH(dimm),
1124 ATTR_ADDR_MATCH(rank),
1125 ATTR_ADDR_MATCH(bank),
1126 ATTR_ADDR_MATCH(page),
1127 ATTR_ADDR_MATCH(col),
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001128 { } /* End of list */
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001129};
1130
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001131static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001132 .name = "inject_addrmatch",
1133 .mcidev_attr = i7core_addrmatch_attrs,
1134};
1135
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001136static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001137 ATTR_COUNTER(0),
1138 ATTR_COUNTER(1),
1139 ATTR_COUNTER(2),
Marcin Slusarz64aab722010-09-30 15:15:30 -07001140 { .attr = { .name = NULL } }
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001141};
1142
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001143static const struct mcidev_sysfs_group i7core_udimm_counters = {
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001144 .name = "all_channel_counts",
1145 .mcidev_attr = i7core_udimm_counters_attrs,
1146};
1147
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001148static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001149 {
1150 .attr = {
1151 .name = "inject_section",
1152 .mode = (S_IRUGO | S_IWUSR)
1153 },
1154 .show = i7core_inject_section_show,
1155 .store = i7core_inject_section_store,
1156 }, {
1157 .attr = {
1158 .name = "inject_type",
1159 .mode = (S_IRUGO | S_IWUSR)
1160 },
1161 .show = i7core_inject_type_show,
1162 .store = i7core_inject_type_store,
1163 }, {
1164 .attr = {
1165 .name = "inject_eccmask",
1166 .mode = (S_IRUGO | S_IWUSR)
1167 },
1168 .show = i7core_inject_eccmask_show,
1169 .store = i7core_inject_eccmask_store,
1170 }, {
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001171 .grp = &i7core_inject_addrmatch,
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001172 }, {
1173 .attr = {
1174 .name = "inject_enable",
1175 .mode = (S_IRUGO | S_IWUSR)
1176 },
1177 .show = i7core_inject_enable_show,
1178 .store = i7core_inject_enable_store,
1179 },
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001180 { } /* End of list */
1181};
1182
1183static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
1184 {
1185 .attr = {
1186 .name = "inject_section",
1187 .mode = (S_IRUGO | S_IWUSR)
1188 },
1189 .show = i7core_inject_section_show,
1190 .store = i7core_inject_section_store,
1191 }, {
1192 .attr = {
1193 .name = "inject_type",
1194 .mode = (S_IRUGO | S_IWUSR)
1195 },
1196 .show = i7core_inject_type_show,
1197 .store = i7core_inject_type_store,
1198 }, {
1199 .attr = {
1200 .name = "inject_eccmask",
1201 .mode = (S_IRUGO | S_IWUSR)
1202 },
1203 .show = i7core_inject_eccmask_show,
1204 .store = i7core_inject_eccmask_store,
1205 }, {
1206 .grp = &i7core_inject_addrmatch,
1207 }, {
1208 .attr = {
1209 .name = "inject_enable",
1210 .mode = (S_IRUGO | S_IWUSR)
1211 },
1212 .show = i7core_inject_enable_show,
1213 .store = i7core_inject_enable_store,
1214 }, {
1215 .grp = &i7core_udimm_counters,
1216 },
1217 { } /* End of list */
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001218};
1219
1220/****************************************************************************
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001221 Device initialization routines: put/get, init/exit
1222 ****************************************************************************/
1223
1224/*
1225 * i7core_put_devices 'put' all the devices that we have
1226 * reserved via 'get'
1227 */
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001228static void i7core_put_devices(struct i7core_dev *i7core_dev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001229{
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001230 int i;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001231
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03001232 debugf0(__FILE__ ": %s()\n", __func__);
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001233 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03001234 struct pci_dev *pdev = i7core_dev->pdev[i];
1235 if (!pdev)
1236 continue;
1237 debugf0("Removing dev %02x:%02x.%d\n",
1238 pdev->bus->number,
1239 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1240 pci_dev_put(pdev);
1241 }
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001242 kfree(i7core_dev->pdev);
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001243}
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001244
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001245static void i7core_put_all_devices(void)
1246{
Mauro Carvalho Chehab42538682009-09-24 09:59:13 -03001247 struct i7core_dev *i7core_dev, *tmp;
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001248
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03001249 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001250 i7core_put_devices(i7core_dev);
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03001251 list_del(&i7core_dev->list);
1252 kfree(i7core_dev);
1253 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001254}
1255
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001256static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
Keith Manntheybc2d7242009-09-03 00:05:05 -03001257{
1258 struct pci_dev *pdev = NULL;
1259 int i;
1260 /*
1261 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
1262 * aren't announced by acpi. So, we need to use a legacy scan probing
1263 * to detect them
1264 */
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001265 while (table && table->descr) {
1266 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
1267 if (unlikely(!pdev)) {
1268 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1269 pcibios_scan_specific_bus(255-i);
1270 }
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001271 pci_dev_put(pdev);
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001272 table++;
Keith Manntheybc2d7242009-09-03 00:05:05 -03001273 }
1274}
1275
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001276static unsigned i7core_pci_lastbus(void)
1277{
1278 int last_bus = 0, bus;
1279 struct pci_bus *b = NULL;
1280
1281 while ((b = pci_find_next_bus(b)) != NULL) {
1282 bus = b->number;
1283 debugf0("Found bus %d\n", bus);
1284 if (bus > last_bus)
1285 last_bus = bus;
1286 }
1287
1288 debugf0("Last bus %d\n", last_bus);
1289
1290 return last_bus;
1291}
1292
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001293/*
1294 * i7core_get_devices Find and perform 'get' operation on the MCH's
1295 * device/functions we want to reference for this driver
1296 *
1297 * Need to 'get' device 16 func 1 and func 2
1298 */
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001299int i7core_get_onedevice(struct pci_dev **prev, const int devno,
1300 const struct pci_id_descr *dev_descr,
1301 const unsigned n_devs,
1302 const unsigned last_bus)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001303{
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001304 struct i7core_dev *i7core_dev;
1305
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001306 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -03001307 u8 bus = 0;
1308 u8 socket = 0;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001309
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001310 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001311 dev_descr->dev_id, *prev);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001312
1313 /*
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001314 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
1315 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1316 * to probe for the alternate address in case of failure
1317 */
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001318 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001319 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
Mauro Carvalho Chehabfd382652009-10-14 06:07:07 -03001320 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -03001321
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001322 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
Mauro Carvalho Chehabf05da2f2009-10-14 13:31:06 -03001323 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1324 PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
1325 *prev);
1326
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001327 if (!pdev) {
1328 if (*prev) {
1329 *prev = pdev;
1330 return 0;
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -03001331 }
1332
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001333 if (dev_descr->optional)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001334 return 0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001335
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001336 if (devno == 0)
1337 return -ENODEV;
1338
Daniel J Bluemanab089372010-07-23 23:16:52 +01001339 i7core_printk(KERN_INFO,
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001340 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001341 dev_descr->dev, dev_descr->func,
1342 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001343
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001344 /* End of list, leave */
1345 return -ENODEV;
1346 }
1347 bus = pdev->bus->number;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001348
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001349 socket = last_bus - bus;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001350
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001351 i7core_dev = get_i7core_dev(socket);
1352 if (!i7core_dev) {
1353 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
1354 if (!i7core_dev)
1355 return -ENOMEM;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001356 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * n_devs,
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001357 GFP_KERNEL);
Alexander Beregalov2a6fae32010-01-07 23:27:30 -03001358 if (!i7core_dev->pdev) {
1359 kfree(i7core_dev);
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001360 return -ENOMEM;
Alexander Beregalov2a6fae32010-01-07 23:27:30 -03001361 }
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001362 i7core_dev->socket = socket;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001363 i7core_dev->n_devs = n_devs;
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001364 list_add_tail(&i7core_dev->list, &i7core_edac_list);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001365 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001366
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001367 if (i7core_dev->pdev[devno]) {
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001368 i7core_printk(KERN_ERR,
1369 "Duplicated device for "
1370 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001371 bus, dev_descr->dev, dev_descr->func,
1372 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001373 pci_dev_put(pdev);
1374 return -ENODEV;
1375 }
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001376
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001377 i7core_dev->pdev[devno] = pdev;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001378
1379 /* Sanity check */
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001380 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1381 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001382 i7core_printk(KERN_ERR,
1383 "Device PCI ID %04x:%04x "
1384 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001385 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001386 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001387 bus, dev_descr->dev, dev_descr->func);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001388 return -ENODEV;
1389 }
1390
1391 /* Be sure that the device is enabled */
1392 if (unlikely(pci_enable_device(pdev) < 0)) {
1393 i7core_printk(KERN_ERR,
1394 "Couldn't enable "
1395 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001396 bus, dev_descr->dev, dev_descr->func,
1397 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001398 return -ENODEV;
1399 }
1400
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03001401 debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001402 socket, bus, dev_descr->dev,
1403 dev_descr->func,
1404 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001405
1406 *prev = pdev;
1407
1408 return 0;
1409}
1410
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001411static int i7core_get_devices(const struct pci_id_table *table)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001412{
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001413 int i, rc, last_bus;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001414 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001415 const struct pci_id_descr *dev_descr;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001416
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001417 last_bus = i7core_pci_lastbus();
1418
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001419 while (table && table->descr) {
1420 dev_descr = table->descr;
1421 for (i = 0; i < table->n_devs; i++) {
1422 pdev = NULL;
1423 do {
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001424 rc = i7core_get_onedevice(&pdev, i,
1425 &dev_descr[i],
1426 table->n_devs,
1427 last_bus);
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001428 if (rc < 0) {
1429 if (i == 0) {
1430 i = table->n_devs;
1431 break;
1432 }
1433 i7core_put_all_devices();
1434 return -ENODEV;
1435 }
1436 } while (pdev);
1437 }
1438 table++;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001439 }
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001440
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001441 return 0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001442}
1443
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001444static int mci_bind_devs(struct mem_ctl_info *mci,
1445 struct i7core_dev *i7core_dev)
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001446{
1447 struct i7core_pvt *pvt = mci->pvt_info;
1448 struct pci_dev *pdev;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001449 int i, func, slot;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001450
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001451 /* Associates i7core_dev and mci for future usage */
1452 pvt->i7core_dev = i7core_dev;
1453 i7core_dev->mci = mci;
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001454
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001455 pvt->is_registered = 0;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001456 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001457 pdev = i7core_dev->pdev[i];
1458 if (!pdev)
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001459 continue;
1460
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001461 func = PCI_FUNC(pdev->devfn);
1462 slot = PCI_SLOT(pdev->devfn);
1463 if (slot == 3) {
1464 if (unlikely(func > MAX_MCR_FUNC))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001465 goto error;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001466 pvt->pci_mcr[func] = pdev;
1467 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1468 if (unlikely(func > MAX_CHAN_FUNC))
1469 goto error;
1470 pvt->pci_ch[slot - 4][func] = pdev;
1471 } else if (!slot && !func)
1472 pvt->pci_noncore = pdev;
1473 else
1474 goto error;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001475
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001476 debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
1477 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1478 pdev, i7core_dev->socket);
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -03001479
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001480 if (PCI_SLOT(pdev->devfn) == 3 &&
1481 PCI_FUNC(pdev->devfn) == 2)
1482 pvt->is_registered = 1;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001483 }
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -03001484
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001485 return 0;
1486
1487error:
1488 i7core_printk(KERN_ERR, "Device %d, function %d "
1489 "is out of the expected range\n",
1490 slot, func);
1491 return -EINVAL;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001492}
1493
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001494/****************************************************************************
1495 Error check routines
1496 ****************************************************************************/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001497static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001498 const int chan,
1499 const int dimm,
1500 const int add)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001501{
1502 char *msg;
1503 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001504 int row = pvt->csrow_map[chan][dimm], i;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001505
1506 for (i = 0; i < add; i++) {
1507 msg = kasprintf(GFP_KERNEL, "Corrected error "
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001508 "(Socket=%d channel=%d dimm=%d)",
1509 pvt->i7core_dev->socket, chan, dimm);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001510
1511 edac_mc_handle_fbd_ce(mci, row, 0, msg);
1512 kfree (msg);
1513 }
1514}
1515
1516static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001517 const int chan,
1518 const int new0,
1519 const int new1,
1520 const int new2)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001521{
1522 struct i7core_pvt *pvt = mci->pvt_info;
1523 int add0 = 0, add1 = 0, add2 = 0;
1524 /* Updates CE counters if it is not the first time here */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001525 if (pvt->ce_count_available) {
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001526 /* Updates CE counters */
1527
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001528 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1529 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1530 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001531
1532 if (add2 < 0)
1533 add2 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001534 pvt->rdimm_ce_count[chan][2] += add2;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001535
1536 if (add1 < 0)
1537 add1 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001538 pvt->rdimm_ce_count[chan][1] += add1;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001539
1540 if (add0 < 0)
1541 add0 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001542 pvt->rdimm_ce_count[chan][0] += add0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001543 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001544 pvt->ce_count_available = 1;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001545
1546 /* Store the new values */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001547 pvt->rdimm_last_ce_count[chan][2] = new2;
1548 pvt->rdimm_last_ce_count[chan][1] = new1;
1549 pvt->rdimm_last_ce_count[chan][0] = new0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001550
1551 /*updated the edac core */
1552 if (add0 != 0)
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001553 i7core_rdimm_update_csrow(mci, chan, 0, add0);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001554 if (add1 != 0)
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001555 i7core_rdimm_update_csrow(mci, chan, 1, add1);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001556 if (add2 != 0)
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001557 i7core_rdimm_update_csrow(mci, chan, 2, add2);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001558
1559}
1560
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001561static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001562{
1563 struct i7core_pvt *pvt = mci->pvt_info;
1564 u32 rcv[3][2];
1565 int i, new0, new1, new2;
1566
1567 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001568 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001569 &rcv[0][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001570 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001571 &rcv[0][1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001572 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001573 &rcv[1][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001574 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001575 &rcv[1][1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001576 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001577 &rcv[2][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001578 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001579 &rcv[2][1]);
1580 for (i = 0 ; i < 3; i++) {
1581 debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1582 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
1583 /*if the channel has 3 dimms*/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001584 if (pvt->channel[i].dimms > 2) {
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001585 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1586 new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1587 new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1588 } else {
1589 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1590 DIMM_BOT_COR_ERR(rcv[i][0]);
1591 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1592 DIMM_BOT_COR_ERR(rcv[i][1]);
1593 new2 = 0;
1594 }
1595
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001596 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001597 }
1598}
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001599
1600/* This function is based on the device 3 function 4 registers as described on:
1601 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1602 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1603 * also available at:
1604 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1605 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001606static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001607{
1608 struct i7core_pvt *pvt = mci->pvt_info;
1609 u32 rcv1, rcv0;
1610 int new0, new1, new2;
1611
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001612 if (!pvt->pci_mcr[4]) {
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -03001613 debugf0("%s MCR registers not found\n", __func__);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001614 return;
1615 }
1616
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001617 /* Corrected test errors */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001618 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1619 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001620
1621 /* Store the new values */
1622 new2 = DIMM2_COR_ERR(rcv1);
1623 new1 = DIMM1_COR_ERR(rcv0);
1624 new0 = DIMM0_COR_ERR(rcv0);
1625
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001626 /* Updates CE counters if it is not the first time here */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001627 if (pvt->ce_count_available) {
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001628 /* Updates CE counters */
1629 int add0, add1, add2;
1630
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001631 add2 = new2 - pvt->udimm_last_ce_count[2];
1632 add1 = new1 - pvt->udimm_last_ce_count[1];
1633 add0 = new0 - pvt->udimm_last_ce_count[0];
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001634
1635 if (add2 < 0)
1636 add2 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001637 pvt->udimm_ce_count[2] += add2;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001638
1639 if (add1 < 0)
1640 add1 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001641 pvt->udimm_ce_count[1] += add1;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001642
1643 if (add0 < 0)
1644 add0 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001645 pvt->udimm_ce_count[0] += add0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001646
1647 if (add0 | add1 | add2)
1648 i7core_printk(KERN_ERR, "New Corrected error(s): "
1649 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1650 add0, add1, add2);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001651 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001652 pvt->ce_count_available = 1;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001653
1654 /* Store the new values */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001655 pvt->udimm_last_ce_count[2] = new2;
1656 pvt->udimm_last_ce_count[1] = new1;
1657 pvt->udimm_last_ce_count[0] = new0;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001658}
1659
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001660/*
1661 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1662 * Architectures Software Developer’s Manual Volume 3B.
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001663 * Nehalem are defined as family 0x06, model 0x1a
1664 *
1665 * The MCA registers used here are the following ones:
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001666 * struct mce field MCA Register
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001667 * m->status MSR_IA32_MC8_STATUS
1668 * m->addr MSR_IA32_MC8_ADDR
1669 * m->misc MSR_IA32_MC8_MISC
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001670 * In the case of Nehalem, the error information is masked at .status and .misc
1671 * fields
1672 */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001673static void i7core_mce_output_error(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001674 const struct mce *m)
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001675{
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001676 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001677 char *type, *optype, *err, *msg;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001678 unsigned long error = m->status & 0x1ff0000l;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001679 u32 optypenum = (m->status >> 4) & 0x07;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001680 u32 core_err_cnt = (m->status >> 38) && 0x7fff;
1681 u32 dimm = (m->misc >> 16) & 0x3;
1682 u32 channel = (m->misc >> 18) & 0x3;
1683 u32 syndrome = m->misc >> 32;
1684 u32 errnum = find_first_bit(&error, 32);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001685 int csrow;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001686
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001687 if (m->mcgstatus & 1)
1688 type = "FATAL";
1689 else
1690 type = "NON_FATAL";
1691
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001692 switch (optypenum) {
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -03001693 case 0:
1694 optype = "generic undef request";
1695 break;
1696 case 1:
1697 optype = "read error";
1698 break;
1699 case 2:
1700 optype = "write error";
1701 break;
1702 case 3:
1703 optype = "addr/cmd error";
1704 break;
1705 case 4:
1706 optype = "scrubbing error";
1707 break;
1708 default:
1709 optype = "reserved";
1710 break;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001711 }
1712
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001713 switch (errnum) {
1714 case 16:
1715 err = "read ECC error";
1716 break;
1717 case 17:
1718 err = "RAS ECC error";
1719 break;
1720 case 18:
1721 err = "write parity error";
1722 break;
1723 case 19:
1724 err = "redundacy loss";
1725 break;
1726 case 20:
1727 err = "reserved";
1728 break;
1729 case 21:
1730 err = "memory range error";
1731 break;
1732 case 22:
1733 err = "RTID out of range";
1734 break;
1735 case 23:
1736 err = "address parity error";
1737 break;
1738 case 24:
1739 err = "byte enable parity error";
1740 break;
1741 default:
1742 err = "unknown";
1743 }
1744
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001745 /* FIXME: should convert addr into bank and rank information */
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001746 msg = kasprintf(GFP_ATOMIC,
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001747 "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001748 "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001749 type, (long long) m->addr, m->cpu, dimm, channel,
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001750 syndrome, core_err_cnt, (long long)m->status,
1751 (long long)m->misc, optype, err);
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001752
1753 debugf0("%s", msg);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001754
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001755 csrow = pvt->csrow_map[channel][dimm];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001756
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001757 /* Call the helper to output message */
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001758 if (m->mcgstatus & 1)
1759 edac_mc_handle_fbd_ue(mci, csrow, 0,
1760 0 /* FIXME: should be channel here */, msg);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001761 else if (!pvt->is_registered)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001762 edac_mc_handle_fbd_ce(mci, csrow,
1763 0 /* FIXME: should be channel here */, msg);
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001764
1765 kfree(msg);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001766}
1767
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001768/*
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001769 * i7core_check_error Retrieve and process errors reported by the
1770 * hardware. Called by the Core module.
1771 */
1772static void i7core_check_error(struct mem_ctl_info *mci)
1773{
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001774 struct i7core_pvt *pvt = mci->pvt_info;
1775 int i;
1776 unsigned count = 0;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001777 struct mce *m;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001778
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001779 /*
1780 * MCE first step: Copy all mce errors into a temporary buffer
1781 * We use a double buffering here, to reduce the risk of
1782 * loosing an error.
1783 */
1784 smp_rmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001785 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1786 % MCE_LOG_LEN;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001787 if (!count)
Vernon Mauery8a311e12010-04-16 19:40:19 -03001788 goto check_ce_error;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001789
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001790 m = pvt->mce_outentry;
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001791 if (pvt->mce_in + count > MCE_LOG_LEN) {
1792 unsigned l = MCE_LOG_LEN - pvt->mce_in;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001793
1794 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1795 smp_wmb();
1796 pvt->mce_in = 0;
1797 count -= l;
1798 m += l;
1799 }
1800 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1801 smp_wmb();
1802 pvt->mce_in += count;
1803
1804 smp_rmb();
1805 if (pvt->mce_overrun) {
1806 i7core_printk(KERN_ERR, "Lost %d memory errors\n",
1807 pvt->mce_overrun);
1808 smp_wmb();
1809 pvt->mce_overrun = 0;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001810 }
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001811
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001812 /*
1813 * MCE second step: parse errors and display
1814 */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001815 for (i = 0; i < count; i++)
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001816 i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001817
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001818 /*
1819 * Now, let's increment CE error counts
1820 */
Vernon Mauery8a311e12010-04-16 19:40:19 -03001821check_ce_error:
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001822 if (!pvt->is_registered)
1823 i7core_udimm_check_mc_ecc_err(mci);
1824 else
1825 i7core_rdimm_check_mc_ecc_err(mci);
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001826}
1827
1828/*
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001829 * i7core_mce_check_error Replicates mcelog routine to get errors
1830 * This routine simply queues mcelog errors, and
1831 * return. The error itself should be handled later
1832 * by i7core_check_error.
Mauro Carvalho Chehab6e103be2009-10-05 09:40:09 -03001833 * WARNING: As this routine should be called at NMI time, extra care should
1834 * be taken to avoid deadlocks, and to be as fast as possible.
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001835 */
1836static int i7core_mce_check_error(void *priv, struct mce *mce)
1837{
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001838 struct mem_ctl_info *mci = priv;
1839 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001840
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001841 /*
1842 * Just let mcelog handle it if the error is
1843 * outside the memory controller
1844 */
1845 if (((mce->status & 0xffff) >> 7) != 1)
1846 return 0;
1847
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001848 /* Bank 8 registers are the only ones that we know how to handle */
1849 if (mce->bank != 8)
1850 return 0;
1851
Randy Dunlap3b918c12009-11-08 01:36:40 -02001852#ifdef CONFIG_SMP
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001853 /* Only handle if it is the right mc controller */
Mauro Carvalho Chehab6e103be2009-10-05 09:40:09 -03001854 if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket)
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001855 return 0;
Randy Dunlap3b918c12009-11-08 01:36:40 -02001856#endif
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001857
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001858 smp_rmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001859 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001860 smp_wmb();
1861 pvt->mce_overrun++;
1862 return 0;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001863 }
Mauro Carvalho Chehab6e103be2009-10-05 09:40:09 -03001864
1865 /* Copy memory error at the ringbuffer */
1866 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001867 smp_wmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001868 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001869
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001870 /* Handle fatal errors immediately */
1871 if (mce->mcgstatus & 1)
1872 i7core_check_error(mci);
1873
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001874 /* Advice mcelog that the error were handled */
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001875 return 1;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001876}
1877
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001878static int i7core_register_mci(struct i7core_dev *i7core_dev,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001879 const int num_channels, const int num_csrows)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001880{
1881 struct mem_ctl_info *mci;
1882 struct i7core_pvt *pvt;
Mauro Carvalho Chehabba6c5c62009-07-15 09:02:32 -03001883 int csrow = 0;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001884 int rc;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001885
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001886 /* allocate a new MC control structure */
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03001887 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels,
1888 i7core_dev->socket);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001889 if (unlikely(!mci))
1890 return -ENOMEM;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001891
Mauro Carvalho Chehab3cfd0142010-08-10 23:23:46 -03001892 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1893 __func__, mci, &i7core_dev->pdev[0]->dev);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001894
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001895 /* record ptr to the generic device */
1896 mci->dev = &i7core_dev->pdev[0]->dev;
1897
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001898 pvt = mci->pvt_info;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001899 memset(pvt, 0, sizeof(*pvt));
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -03001900
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03001901 /*
1902 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
1903 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
1904 * memory channels
1905 */
1906 mci->mtype_cap = MEM_FLAG_DDR3;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001907 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1908 mci->edac_cap = EDAC_FLAG_NONE;
1909 mci->mod_name = "i7core_edac.c";
1910 mci->mod_ver = I7CORE_REVISION;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001911 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
1912 i7core_dev->socket);
1913 mci->dev_name = pci_name(i7core_dev->pdev[0]);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001914 mci->ctl_page_to_phys = NULL;
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001915
1916 if (pvt->is_registered)
1917 mci->mc_driver_sysfs_attributes = i7core_sysfs_rdimm_attrs;
1918 else
1919 mci->mc_driver_sysfs_attributes = i7core_sysfs_udimm_attrs;
1920
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001921 /* Set the function pointer to an actual operation function */
1922 mci->edac_check = i7core_check_error;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001923
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001924 /* Store pci devices at mci for faster access */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001925 rc = mci_bind_devs(mci, i7core_dev);
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03001926 if (unlikely(rc < 0))
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001927 goto fail;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001928
1929 /* Get dimm basic config */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001930 get_dimm_config(mci, &csrow);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001931
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001932 /* add this new MC control structure to EDAC's list of MCs */
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03001933 if (unlikely(edac_mc_add_mc(mci))) {
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001934 debugf0("MC: " __FILE__
1935 ": %s(): failed edac_mc_add_mc()\n", __func__);
1936 /* FIXME: perhaps some code should go here that disables error
1937 * reporting if we just enabled it
1938 */
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03001939
1940 rc = -EINVAL;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001941 goto fail;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001942 }
1943
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001944 /* Default error mask is any memory */
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001945 pvt->inject.channel = 0;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001946 pvt->inject.dimm = -1;
1947 pvt->inject.rank = -1;
1948 pvt->inject.bank = -1;
1949 pvt->inject.page = -1;
1950 pvt->inject.col = -1;
1951
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001952 /* Registers on edac_mce in order to receive memory errors */
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001953 pvt->edac_mce.priv = mci;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001954 pvt->edac_mce.check_error = i7core_mce_check_error;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001955
Mauro Carvalho Chehab6ee7dd52010-08-10 23:24:16 -03001956 /* allocating generic PCI control info */
1957 pvt->i7core_pci = edac_pci_create_generic_ctl(&i7core_dev->pdev[0]->dev,
1958 EDAC_MOD_STR);
1959 if (unlikely(!pvt->i7core_pci)) {
1960 printk(KERN_WARNING
1961 "%s(): Unable to create PCI control\n",
1962 __func__);
1963 printk(KERN_WARNING
1964 "%s(): PCI error report via EDAC not setup\n",
1965 __func__);
1966 }
1967
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001968 rc = edac_mce_register(&pvt->edac_mce);
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -03001969 if (unlikely(rc < 0)) {
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001970 debugf0("MC: " __FILE__
1971 ": %s(): failed edac_mce_register()\n", __func__);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001972 }
1973
1974fail:
Tony Luckd4d1ef42010-05-18 10:53:25 -03001975 if (rc < 0)
1976 edac_mc_free(mci);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001977 return rc;
1978}
1979
1980/*
1981 * i7core_probe Probe for ONE instance of device to see if it is
1982 * present.
1983 * return:
1984 * 0 for FOUND a device
1985 * < 0 for error code
1986 */
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03001987
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001988static int __devinit i7core_probe(struct pci_dev *pdev,
1989 const struct pci_device_id *id)
1990{
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001991 int rc;
1992 struct i7core_dev *i7core_dev;
1993
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03001994 /* get the pci devices we want to reserve for our use */
1995 mutex_lock(&i7core_edac_lock);
1996
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001997 /*
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03001998 * All memory controllers are allocated at the first pass.
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001999 */
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002000 if (unlikely(probed >= 1)) {
2001 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002002 return -EINVAL;
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002003 }
2004 probed++;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03002005
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03002006 rc = i7core_get_devices(pci_dev_table);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002007 if (unlikely(rc < 0))
2008 goto fail0;
2009
2010 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
2011 int channels;
2012 int csrows;
2013
2014 /* Check the number of active and not disabled channels */
2015 rc = i7core_get_active_channels(i7core_dev->socket,
2016 &channels, &csrows);
2017 if (unlikely(rc < 0))
2018 goto fail1;
2019
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03002020 rc = i7core_register_mci(i7core_dev, channels, csrows);
2021 if (unlikely(rc < 0))
2022 goto fail1;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03002023 }
2024
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002025 i7core_printk(KERN_INFO, "Driver loaded.\n");
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03002026
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002027 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002028 return 0;
2029
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002030fail1:
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03002031 i7core_put_all_devices();
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002032fail0:
2033 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002034 return rc;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002035}
2036
2037/*
2038 * i7core_remove destructor for one instance of device
2039 *
2040 */
2041static void __devexit i7core_remove(struct pci_dev *pdev)
2042{
2043 struct mem_ctl_info *mci;
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002044 struct i7core_dev *i7core_dev, *tmp;
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -03002045 struct i7core_pvt *pvt;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002046
2047 debugf0(__FILE__ ": %s()\n", __func__);
2048
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002049 /*
2050 * we have a trouble here: pdev value for removal will be wrong, since
2051 * it will point to the X58 register used to detect that the machine
2052 * is a Nehalem or upper design. However, due to the way several PCI
2053 * devices are grouped together to provide MC functionality, we need
2054 * to use a different method for releasing the devices
2055 */
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03002056
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002057 mutex_lock(&i7core_edac_lock);
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002058 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -03002059 mci = find_mci_by_dev(&i7core_dev->pdev[0]->dev);
2060 if (unlikely(!mci || !mci->pvt_info)) {
Mauro Carvalho Chehab3cfd0142010-08-10 23:23:46 -03002061 debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
2062 __func__, &i7core_dev->pdev[0]->dev);
2063
2064 i7core_printk(KERN_ERR,
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -03002065 "Couldn't find mci hanler\n");
2066 } else {
2067 pvt = mci->pvt_info;
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002068 i7core_dev = pvt->i7core_dev;
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -03002069
Mauro Carvalho Chehab3cfd0142010-08-10 23:23:46 -03002070 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
2071 __func__, mci, &i7core_dev->pdev[0]->dev);
2072
Mauro Carvalho Chehab41ba6c12010-08-11 00:58:11 -03002073 /* Disable MCE NMI handler */
2074 edac_mce_unregister(&pvt->edac_mce);
2075
2076 /* Disable EDAC polling */
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -03002077 if (likely(pvt->i7core_pci))
2078 edac_pci_release_generic_ctl(pvt->i7core_pci);
2079 else
2080 i7core_printk(KERN_ERR,
2081 "Couldn't find mem_ctl_info for socket %d\n",
2082 i7core_dev->socket);
2083 pvt->i7core_pci = NULL;
2084
Mauro Carvalho Chehab41ba6c12010-08-11 00:58:11 -03002085 /* Remove MC sysfs nodes */
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -03002086 edac_mc_del_mc(&i7core_dev->pdev[0]->dev);
2087
Mauro Carvalho Chehab41ba6c12010-08-11 00:58:11 -03002088 /* Free data */
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002089 kfree(mci->ctl_name);
2090 edac_mc_free(mci);
Mauro Carvalho Chehab41ba6c12010-08-11 00:58:11 -03002091
2092 /* Release PCI resources */
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002093 i7core_put_devices(i7core_dev);
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002094 }
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03002095 list_del(&i7core_dev->list);
2096 kfree(i7core_dev);
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002097 }
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002098 probed--;
2099
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002100 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002101}
2102
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002103MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
2104
2105/*
2106 * i7core_driver pci_driver structure for this module
2107 *
2108 */
2109static struct pci_driver i7core_driver = {
2110 .name = "i7core_edac",
2111 .probe = i7core_probe,
2112 .remove = __devexit_p(i7core_remove),
2113 .id_table = i7core_pci_tbl,
2114};
2115
2116/*
2117 * i7core_init Module entry function
2118 * Try to initialize this module for its devices
2119 */
2120static int __init i7core_init(void)
2121{
2122 int pci_rc;
2123
2124 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2125
2126 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2127 opstate_init();
2128
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03002129 i7core_xeon_pci_fixup(pci_dev_table);
Keith Manntheybc2d7242009-09-03 00:05:05 -03002130
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002131 pci_rc = pci_register_driver(&i7core_driver);
2132
Mauro Carvalho Chehab3ef288a2009-09-02 23:43:33 -03002133 if (pci_rc >= 0)
2134 return 0;
2135
2136 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
2137 pci_rc);
2138
2139 return pci_rc;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002140}
2141
2142/*
2143 * i7core_exit() Module exit function
2144 * Unregister the driver
2145 */
2146static void __exit i7core_exit(void)
2147{
2148 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2149 pci_unregister_driver(&i7core_driver);
2150}
2151
2152module_init(i7core_init);
2153module_exit(i7core_exit);
2154
2155MODULE_LICENSE("GPL");
2156MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2157MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2158MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
2159 I7CORE_REVISION);
2160
2161module_param(edac_op_state, int, 0444);
2162MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");