Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
Jerome Glisse | 8d1c702 | 2012-07-17 17:17:16 -0400 | [diff] [blame] | 25 | * Jerome Glisse |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 26 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 27 | #include <drm/drmP.h> |
| 28 | #include <drm/radeon_drm.h> |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 29 | #include "radeon.h" |
| 30 | |
| 31 | #include "atom.h" |
| 32 | #include "atom-bits.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drm_dp_helper.h> |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 34 | |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 35 | /* move these to drm_dp_helper.c/h */ |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 37 | #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 38 | |
| 39 | static char *voltage_names[] = { |
| 40 | "0.4V", "0.6V", "0.8V", "1.2V" |
| 41 | }; |
| 42 | static char *pre_emph_names[] = { |
| 43 | "0dB", "3.5dB", "6dB", "9.5dB" |
| 44 | }; |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 45 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 46 | /***** radeon AUX functions *****/ |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 47 | union aux_channel_transaction { |
| 48 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; |
| 49 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; |
| 50 | }; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 51 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 52 | static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, |
| 53 | u8 *send, int send_bytes, |
| 54 | u8 *recv, int recv_size, |
| 55 | u8 delay, u8 *ack) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 56 | { |
| 57 | struct drm_device *dev = chan->dev; |
| 58 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 59 | union aux_channel_transaction args; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 60 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); |
| 61 | unsigned char *base; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 62 | int recv_bytes; |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 63 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 64 | memset(&args, 0, sizeof(args)); |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 65 | |
Alex Deucher | 97412a7 | 2012-03-20 17:18:06 -0400 | [diff] [blame] | 66 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 67 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 68 | memcpy(base, send, send_bytes); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 69 | |
Alex Deucher | 97412a7 | 2012-03-20 17:18:06 -0400 | [diff] [blame] | 70 | args.v1.lpAuxRequest = 0 + 4; |
| 71 | args.v1.lpDataOut = 16 + 4; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 72 | args.v1.ucDataOutLen = 0; |
| 73 | args.v1.ucChannelID = chan->rec.i2c_id; |
| 74 | args.v1.ucDelay = delay / 10; |
| 75 | if (ASIC_IS_DCE4(rdev)) |
Alex Deucher | 8e36ed0 | 2010-05-18 19:26:47 -0400 | [diff] [blame] | 76 | args.v2.ucHPD_ID = chan->rec.hpd; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 77 | |
| 78 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 79 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 80 | *ack = args.v1.ucReplyStatus; |
| 81 | |
| 82 | /* timeout */ |
| 83 | if (args.v1.ucReplyStatus == 1) { |
| 84 | DRM_DEBUG_KMS("dp_aux_ch timeout\n"); |
| 85 | return -ETIMEDOUT; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 86 | } |
| 87 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 88 | /* flags not zero */ |
| 89 | if (args.v1.ucReplyStatus == 2) { |
| 90 | DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); |
| 91 | return -EBUSY; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 92 | } |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 93 | |
| 94 | /* error */ |
| 95 | if (args.v1.ucReplyStatus == 3) { |
| 96 | DRM_DEBUG_KMS("dp_aux_ch error\n"); |
| 97 | return -EIO; |
| 98 | } |
| 99 | |
| 100 | recv_bytes = args.v1.ucDataOutLen; |
| 101 | if (recv_bytes > recv_size) |
| 102 | recv_bytes = recv_size; |
| 103 | |
| 104 | if (recv && recv_size) |
| 105 | memcpy(recv, base + 16, recv_bytes); |
| 106 | |
| 107 | return recv_bytes; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 108 | } |
| 109 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 110 | static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, |
| 111 | u16 address, u8 *send, u8 send_bytes, u8 delay) |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 112 | { |
| 113 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 114 | int ret; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 115 | u8 msg[20]; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 116 | int msg_bytes = send_bytes + 4; |
| 117 | u8 ack; |
Alex Deucher | 6375bda | 2011-10-03 09:13:46 -0400 | [diff] [blame] | 118 | unsigned retry; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 119 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 120 | if (send_bytes > 16) |
| 121 | return -1; |
| 122 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 123 | msg[0] = address; |
| 124 | msg[1] = address >> 8; |
| 125 | msg[2] = AUX_NATIVE_WRITE << 4; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 126 | msg[3] = (msg_bytes << 4) | (send_bytes - 1); |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 127 | memcpy(&msg[4], send, send_bytes); |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 128 | |
Alex Deucher | 6375bda | 2011-10-03 09:13:46 -0400 | [diff] [blame] | 129 | for (retry = 0; retry < 4; retry++) { |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 130 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
| 131 | msg, msg_bytes, NULL, 0, delay, &ack); |
Alex Deucher | 4f33284 | 2011-10-04 17:23:15 -0400 | [diff] [blame] | 132 | if (ret == -EBUSY) |
| 133 | continue; |
| 134 | else if (ret < 0) |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 135 | return ret; |
| 136 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
Alex Deucher | 6375bda | 2011-10-03 09:13:46 -0400 | [diff] [blame] | 137 | return send_bytes; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 138 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
| 139 | udelay(400); |
| 140 | else |
| 141 | return -EIO; |
| 142 | } |
| 143 | |
Alex Deucher | 6375bda | 2011-10-03 09:13:46 -0400 | [diff] [blame] | 144 | return -EIO; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 145 | } |
| 146 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 147 | static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, |
| 148 | u16 address, u8 *recv, int recv_bytes, u8 delay) |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 149 | { |
| 150 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 151 | u8 msg[4]; |
| 152 | int msg_bytes = 4; |
| 153 | u8 ack; |
| 154 | int ret; |
Alex Deucher | 6375bda | 2011-10-03 09:13:46 -0400 | [diff] [blame] | 155 | unsigned retry; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 156 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 157 | msg[0] = address; |
| 158 | msg[1] = address >> 8; |
| 159 | msg[2] = AUX_NATIVE_READ << 4; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 160 | msg[3] = (msg_bytes << 4) | (recv_bytes - 1); |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 161 | |
Alex Deucher | 6375bda | 2011-10-03 09:13:46 -0400 | [diff] [blame] | 162 | for (retry = 0; retry < 4; retry++) { |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 163 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
| 164 | msg, msg_bytes, recv, recv_bytes, delay, &ack); |
Alex Deucher | 4f33284 | 2011-10-04 17:23:15 -0400 | [diff] [blame] | 165 | if (ret == -EBUSY) |
| 166 | continue; |
| 167 | else if (ret < 0) |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 168 | return ret; |
| 169 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
| 170 | return ret; |
| 171 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
| 172 | udelay(400); |
Alex Deucher | 109bc10 | 2011-10-03 09:13:45 -0400 | [diff] [blame] | 173 | else if (ret == 0) |
| 174 | return -EPROTO; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 175 | else |
| 176 | return -EIO; |
| 177 | } |
Alex Deucher | 6375bda | 2011-10-03 09:13:46 -0400 | [diff] [blame] | 178 | |
| 179 | return -EIO; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 180 | } |
| 181 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 182 | static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, |
| 183 | u16 reg, u8 val) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 184 | { |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 185 | radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 186 | } |
| 187 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 188 | static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector, |
| 189 | u16 reg) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 190 | { |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 191 | u8 val = 0; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 192 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 193 | radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 194 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 195 | return val; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 196 | } |
| 197 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 198 | int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 199 | u8 write_byte, u8 *read_byte) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 200 | { |
| 201 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
| 202 | struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 203 | u16 address = algo_data->address; |
| 204 | u8 msg[5]; |
| 205 | u8 reply[2]; |
| 206 | unsigned retry; |
| 207 | int msg_bytes; |
| 208 | int reply_bytes = 1; |
| 209 | int ret; |
| 210 | u8 ack; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 211 | |
| 212 | /* Set up the command byte */ |
| 213 | if (mode & MODE_I2C_READ) |
| 214 | msg[2] = AUX_I2C_READ << 4; |
| 215 | else |
| 216 | msg[2] = AUX_I2C_WRITE << 4; |
| 217 | |
| 218 | if (!(mode & MODE_I2C_STOP)) |
| 219 | msg[2] |= AUX_I2C_MOT << 4; |
| 220 | |
| 221 | msg[0] = address; |
| 222 | msg[1] = address >> 8; |
| 223 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 224 | switch (mode) { |
| 225 | case MODE_I2C_WRITE: |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 226 | msg_bytes = 5; |
| 227 | msg[3] = msg_bytes << 4; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 228 | msg[4] = write_byte; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 229 | break; |
| 230 | case MODE_I2C_READ: |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 231 | msg_bytes = 4; |
| 232 | msg[3] = msg_bytes << 4; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 233 | break; |
| 234 | default: |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 235 | msg_bytes = 4; |
| 236 | msg[3] = 3 << 4; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 237 | break; |
| 238 | } |
| 239 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 240 | for (retry = 0; retry < 4; retry++) { |
| 241 | ret = radeon_process_aux_ch(auxch, |
| 242 | msg, msg_bytes, reply, reply_bytes, 0, &ack); |
Alex Deucher | 4f33284 | 2011-10-04 17:23:15 -0400 | [diff] [blame] | 243 | if (ret == -EBUSY) |
| 244 | continue; |
| 245 | else if (ret < 0) { |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 246 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
| 247 | return ret; |
| 248 | } |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 249 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 250 | switch (ack & AUX_NATIVE_REPLY_MASK) { |
| 251 | case AUX_NATIVE_REPLY_ACK: |
| 252 | /* I2C-over-AUX Reply field is only valid |
| 253 | * when paired with AUX ACK. |
| 254 | */ |
| 255 | break; |
| 256 | case AUX_NATIVE_REPLY_NACK: |
| 257 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
| 258 | return -EREMOTEIO; |
| 259 | case AUX_NATIVE_REPLY_DEFER: |
| 260 | DRM_DEBUG_KMS("aux_ch native defer\n"); |
| 261 | udelay(400); |
| 262 | continue; |
| 263 | default: |
| 264 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); |
| 265 | return -EREMOTEIO; |
| 266 | } |
| 267 | |
| 268 | switch (ack & AUX_I2C_REPLY_MASK) { |
| 269 | case AUX_I2C_REPLY_ACK: |
| 270 | if (mode == MODE_I2C_READ) |
| 271 | *read_byte = reply[0]; |
| 272 | return ret; |
| 273 | case AUX_I2C_REPLY_NACK: |
| 274 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
| 275 | return -EREMOTEIO; |
| 276 | case AUX_I2C_REPLY_DEFER: |
| 277 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
| 278 | udelay(400); |
| 279 | break; |
| 280 | default: |
| 281 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); |
| 282 | return -EREMOTEIO; |
| 283 | } |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 284 | } |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 285 | |
Alex Deucher | 091264f | 2011-11-08 10:09:58 -0500 | [diff] [blame] | 286 | DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 287 | return -EREMOTEIO; |
| 288 | } |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 289 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 290 | /***** general DP utility functions *****/ |
| 291 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 292 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 |
| 293 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 |
| 294 | |
| 295 | static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], |
| 296 | int lane_count, |
| 297 | u8 train_set[4]) |
| 298 | { |
| 299 | u8 v = 0; |
| 300 | u8 p = 0; |
| 301 | int lane; |
| 302 | |
| 303 | for (lane = 0; lane < lane_count; lane++) { |
Daniel Vetter | 0f037bd | 2012-10-18 10:15:27 +0200 | [diff] [blame] | 304 | u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
| 305 | u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 306 | |
| 307 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
| 308 | lane, |
| 309 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
| 310 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
| 311 | |
| 312 | if (this_v > v) |
| 313 | v = this_v; |
| 314 | if (this_p > p) |
| 315 | p = this_p; |
| 316 | } |
| 317 | |
| 318 | if (v >= DP_VOLTAGE_MAX) |
| 319 | v |= DP_TRAIN_MAX_SWING_REACHED; |
| 320 | |
| 321 | if (p >= DP_PRE_EMPHASIS_MAX) |
| 322 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
| 323 | |
| 324 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
| 325 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
| 326 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
| 327 | |
| 328 | for (lane = 0; lane < 4; lane++) |
| 329 | train_set[lane] = v | p; |
| 330 | } |
| 331 | |
| 332 | /* convert bits per color to bits per pixel */ |
| 333 | /* get bpc from the EDID */ |
| 334 | static int convert_bpc_to_bpp(int bpc) |
| 335 | { |
| 336 | if (bpc == 0) |
| 337 | return 24; |
| 338 | else |
| 339 | return bpc * 3; |
| 340 | } |
| 341 | |
| 342 | /* get the max pix clock supported by the link rate and lane num */ |
| 343 | static int dp_get_max_dp_pix_clock(int link_rate, |
| 344 | int lane_num, |
| 345 | int bpp) |
| 346 | { |
| 347 | return (link_rate * lane_num * 8) / bpp; |
| 348 | } |
| 349 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 350 | /***** radeon specific DP functions *****/ |
| 351 | |
| 352 | /* First get the min lane# when low rate is used according to pixel clock |
| 353 | * (prefer low rate), second check max lane# supported by DP panel, |
| 354 | * if the max lane# < low rate lane# then use max lane# instead. |
| 355 | */ |
| 356 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, |
| 357 | u8 dpcd[DP_DPCD_SIZE], |
| 358 | int pix_clock) |
| 359 | { |
Alex Deucher | eccea79 | 2012-03-26 15:12:54 -0400 | [diff] [blame] | 360 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
Daniel Vetter | 3b5c662 | 2012-10-18 10:15:31 +0200 | [diff] [blame] | 361 | int max_link_rate = drm_dp_max_link_rate(dpcd); |
Daniel Vetter | 397fe15 | 2012-10-22 22:56:43 +0200 | [diff] [blame^] | 362 | int max_lane_num = drm_dp_max_lane_count(dpcd); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 363 | int lane_num; |
| 364 | int max_dp_pix_clock; |
| 365 | |
| 366 | for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { |
| 367 | max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); |
| 368 | if (pix_clock <= max_dp_pix_clock) |
| 369 | break; |
| 370 | } |
| 371 | |
| 372 | return lane_num; |
| 373 | } |
| 374 | |
| 375 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
| 376 | u8 dpcd[DP_DPCD_SIZE], |
| 377 | int pix_clock) |
| 378 | { |
Alex Deucher | eccea79 | 2012-03-26 15:12:54 -0400 | [diff] [blame] | 379 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 380 | int lane_num, max_pix_clock; |
| 381 | |
Alex Deucher | fdca78c | 2011-10-25 11:54:52 -0400 | [diff] [blame] | 382 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
| 383 | ENCODER_OBJECT_ID_NUTMEG) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 384 | return 270000; |
| 385 | |
| 386 | lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); |
| 387 | max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); |
| 388 | if (pix_clock <= max_pix_clock) |
| 389 | return 162000; |
| 390 | max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); |
| 391 | if (pix_clock <= max_pix_clock) |
| 392 | return 270000; |
| 393 | if (radeon_connector_is_dp12_capable(connector)) { |
| 394 | max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); |
| 395 | if (pix_clock <= max_pix_clock) |
| 396 | return 540000; |
| 397 | } |
| 398 | |
Daniel Vetter | 3b5c662 | 2012-10-18 10:15:31 +0200 | [diff] [blame] | 399 | return drm_dp_max_link_rate(dpcd); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 400 | } |
| 401 | |
| 402 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, |
| 403 | int action, int dp_clock, |
| 404 | u8 ucconfig, u8 lane_num) |
| 405 | { |
| 406 | DP_ENCODER_SERVICE_PARAMETERS args; |
| 407 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
| 408 | |
| 409 | memset(&args, 0, sizeof(args)); |
| 410 | args.ucLinkClock = dp_clock / 10; |
| 411 | args.ucConfig = ucconfig; |
| 412 | args.ucAction = action; |
| 413 | args.ucLaneNum = lane_num; |
| 414 | args.ucStatus = 0; |
| 415 | |
| 416 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 417 | return args.ucStatus; |
| 418 | } |
| 419 | |
| 420 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) |
| 421 | { |
| 422 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
| 423 | struct drm_device *dev = radeon_connector->base.dev; |
| 424 | struct radeon_device *rdev = dev->dev_private; |
| 425 | |
| 426 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, |
| 427 | dig_connector->dp_i2c_bus->rec.i2c_id, 0); |
| 428 | } |
| 429 | |
Adam Jackson | 40c5d87 | 2012-05-14 16:05:48 -0400 | [diff] [blame] | 430 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
| 431 | { |
| 432 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
| 433 | u8 buf[3]; |
| 434 | |
| 435 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
| 436 | return; |
| 437 | |
| 438 | if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0)) |
| 439 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
| 440 | buf[0], buf[1], buf[2]); |
| 441 | |
| 442 | if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0)) |
| 443 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
| 444 | buf[0], buf[1], buf[2]); |
| 445 | } |
| 446 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 447 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
| 448 | { |
| 449 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 450 | u8 msg[DP_DPCD_SIZE]; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 451 | int ret, i; |
| 452 | |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 453 | ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, |
| 454 | DP_DPCD_SIZE, 0); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 455 | if (ret > 0) { |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 456 | memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 457 | DRM_DEBUG_KMS("DPCD: "); |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 458 | for (i = 0; i < DP_DPCD_SIZE; i++) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 459 | DRM_DEBUG_KMS("%02x ", msg[i]); |
| 460 | DRM_DEBUG_KMS("\n"); |
Adam Jackson | 40c5d87 | 2012-05-14 16:05:48 -0400 | [diff] [blame] | 461 | |
| 462 | radeon_dp_probe_oui(radeon_connector); |
| 463 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 464 | return true; |
| 465 | } |
| 466 | dig_connector->dpcd[0] = 0; |
| 467 | return false; |
| 468 | } |
| 469 | |
Alex Deucher | 386d4d7 | 2012-01-20 15:01:29 -0500 | [diff] [blame] | 470 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
| 471 | struct drm_connector *connector) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 472 | { |
| 473 | struct drm_device *dev = encoder->dev; |
| 474 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 00dfb8d | 2011-10-31 08:54:41 -0400 | [diff] [blame] | 475 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 476 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
Alex Deucher | 0ceb996 | 2012-08-27 17:48:18 -0400 | [diff] [blame] | 477 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
| 478 | u8 tmp; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 479 | |
| 480 | if (!ASIC_IS_DCE4(rdev)) |
Alex Deucher | 386d4d7 | 2012-01-20 15:01:29 -0500 | [diff] [blame] | 481 | return panel_mode; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 482 | |
Alex Deucher | 0ceb996 | 2012-08-27 17:48:18 -0400 | [diff] [blame] | 483 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
| 484 | /* DP bridge chips */ |
| 485 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); |
| 486 | if (tmp & 1) |
| 487 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
| 488 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || |
| 489 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) |
Alex Deucher | 304a484 | 2012-02-02 10:18:00 -0500 | [diff] [blame] | 490 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
| 491 | else |
Alex Deucher | 0ceb996 | 2012-08-27 17:48:18 -0400 | [diff] [blame] | 492 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
Alex Deucher | 304a484 | 2012-02-02 10:18:00 -0500 | [diff] [blame] | 493 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
Alex Deucher | 0ceb996 | 2012-08-27 17:48:18 -0400 | [diff] [blame] | 494 | /* eDP */ |
| 495 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); |
Alex Deucher | 00dfb8d | 2011-10-31 08:54:41 -0400 | [diff] [blame] | 496 | if (tmp & 1) |
| 497 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
| 498 | } |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 499 | |
Alex Deucher | 386d4d7 | 2012-01-20 15:01:29 -0500 | [diff] [blame] | 500 | return panel_mode; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 501 | } |
| 502 | |
| 503 | void radeon_dp_set_link_config(struct drm_connector *connector, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 504 | const struct drm_display_mode *mode) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 505 | { |
| 506 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 507 | struct radeon_connector_atom_dig *dig_connector; |
| 508 | |
| 509 | if (!radeon_connector->con_priv) |
| 510 | return; |
| 511 | dig_connector = radeon_connector->con_priv; |
| 512 | |
| 513 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
| 514 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
| 515 | dig_connector->dp_clock = |
| 516 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); |
| 517 | dig_connector->dp_lane_count = |
| 518 | radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); |
| 519 | } |
| 520 | } |
| 521 | |
| 522 | int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
| 523 | struct drm_display_mode *mode) |
| 524 | { |
| 525 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 526 | struct radeon_connector_atom_dig *dig_connector; |
| 527 | int dp_clock; |
| 528 | |
| 529 | if (!radeon_connector->con_priv) |
| 530 | return MODE_CLOCK_HIGH; |
| 531 | dig_connector = radeon_connector->con_priv; |
| 532 | |
| 533 | dp_clock = |
| 534 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); |
| 535 | |
| 536 | if ((dp_clock == 540000) && |
| 537 | (!radeon_connector_is_dp12_capable(connector))) |
| 538 | return MODE_CLOCK_HIGH; |
| 539 | |
| 540 | return MODE_OK; |
| 541 | } |
| 542 | |
| 543 | static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector, |
| 544 | u8 link_status[DP_LINK_STATUS_SIZE]) |
| 545 | { |
| 546 | int ret; |
| 547 | ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, |
| 548 | link_status, DP_LINK_STATUS_SIZE, 100); |
| 549 | if (ret <= 0) { |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 550 | return false; |
| 551 | } |
| 552 | |
Andy Shevchenko | 9a6a4b4 | 2012-09-05 12:04:19 +0000 | [diff] [blame] | 553 | DRM_DEBUG_KMS("link status %*ph\n", 6, link_status); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 554 | return true; |
| 555 | } |
| 556 | |
Alex Deucher | d5811e8 | 2011-08-13 13:36:13 -0400 | [diff] [blame] | 557 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
| 558 | { |
| 559 | u8 link_status[DP_LINK_STATUS_SIZE]; |
| 560 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
| 561 | |
| 562 | if (!radeon_dp_get_link_status(radeon_connector, link_status)) |
| 563 | return false; |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 564 | if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
Alex Deucher | d5811e8 | 2011-08-13 13:36:13 -0400 | [diff] [blame] | 565 | return false; |
| 566 | return true; |
| 567 | } |
| 568 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 569 | struct radeon_dp_link_train_info { |
| 570 | struct radeon_device *rdev; |
| 571 | struct drm_encoder *encoder; |
| 572 | struct drm_connector *connector; |
| 573 | struct radeon_connector *radeon_connector; |
| 574 | int enc_id; |
| 575 | int dp_clock; |
| 576 | int dp_lane_count; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 577 | bool tp3_supported; |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 578 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 579 | u8 train_set[4]; |
| 580 | u8 link_status[DP_LINK_STATUS_SIZE]; |
| 581 | u8 tries; |
Jerome Glisse | 5a96a89 | 2011-07-25 11:57:43 -0400 | [diff] [blame] | 582 | bool use_dpencoder; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 583 | }; |
| 584 | |
| 585 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
| 586 | { |
| 587 | /* set the initial vs/emph on the source */ |
| 588 | atombios_dig_transmitter_setup(dp_info->encoder, |
| 589 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, |
| 590 | 0, dp_info->train_set[0]); /* sets all lanes at once */ |
| 591 | |
| 592 | /* set the vs/emph on the sink */ |
| 593 | radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET, |
| 594 | dp_info->train_set, dp_info->dp_lane_count, 0); |
| 595 | } |
| 596 | |
| 597 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
| 598 | { |
| 599 | int rtp = 0; |
| 600 | |
| 601 | /* set training pattern on the source */ |
Jerome Glisse | 5a96a89 | 2011-07-25 11:57:43 -0400 | [diff] [blame] | 602 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 603 | switch (tp) { |
| 604 | case DP_TRAINING_PATTERN_1: |
| 605 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; |
| 606 | break; |
| 607 | case DP_TRAINING_PATTERN_2: |
| 608 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; |
| 609 | break; |
| 610 | case DP_TRAINING_PATTERN_3: |
| 611 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; |
| 612 | break; |
| 613 | } |
| 614 | atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); |
| 615 | } else { |
| 616 | switch (tp) { |
| 617 | case DP_TRAINING_PATTERN_1: |
| 618 | rtp = 0; |
| 619 | break; |
| 620 | case DP_TRAINING_PATTERN_2: |
| 621 | rtp = 1; |
| 622 | break; |
| 623 | } |
| 624 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, |
| 625 | dp_info->dp_clock, dp_info->enc_id, rtp); |
| 626 | } |
| 627 | |
| 628 | /* enable training pattern on the sink */ |
| 629 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); |
| 630 | } |
| 631 | |
| 632 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
| 633 | { |
Alex Deucher | 386d4d7 | 2012-01-20 15:01:29 -0500 | [diff] [blame] | 634 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
| 635 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 636 | u8 tmp; |
| 637 | |
| 638 | /* power up the sink */ |
| 639 | if (dp_info->dpcd[0] >= 0x11) |
| 640 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
| 641 | DP_SET_POWER, DP_SET_POWER_D0); |
| 642 | |
| 643 | /* possibly enable downspread on the sink */ |
| 644 | if (dp_info->dpcd[3] & 0x1) |
| 645 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
| 646 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); |
| 647 | else |
| 648 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
| 649 | DP_DOWNSPREAD_CTRL, 0); |
| 650 | |
Alex Deucher | 386d4d7 | 2012-01-20 15:01:29 -0500 | [diff] [blame] | 651 | if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && |
| 652 | (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { |
| 653 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1); |
| 654 | } |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 655 | |
| 656 | /* set the lane count on the sink */ |
| 657 | tmp = dp_info->dp_lane_count; |
Dave Airlie | abc8113 | 2012-03-18 10:10:50 +0000 | [diff] [blame] | 658 | if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 && |
| 659 | dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 660 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
| 661 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); |
| 662 | |
| 663 | /* set the link rate on the sink */ |
Daniel Vetter | 3b5c662 | 2012-10-18 10:15:31 +0200 | [diff] [blame] | 664 | tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 665 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); |
| 666 | |
| 667 | /* start training on the source */ |
Jerome Glisse | 5a96a89 | 2011-07-25 11:57:43 -0400 | [diff] [blame] | 668 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 669 | atombios_dig_encoder_setup(dp_info->encoder, |
| 670 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); |
| 671 | else |
| 672 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
| 673 | dp_info->dp_clock, dp_info->enc_id, 0); |
| 674 | |
| 675 | /* disable the training pattern on the sink */ |
| 676 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
| 677 | DP_TRAINING_PATTERN_SET, |
| 678 | DP_TRAINING_PATTERN_DISABLE); |
| 679 | |
| 680 | return 0; |
| 681 | } |
| 682 | |
| 683 | static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) |
| 684 | { |
| 685 | udelay(400); |
| 686 | |
| 687 | /* disable the training pattern on the sink */ |
| 688 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
| 689 | DP_TRAINING_PATTERN_SET, |
| 690 | DP_TRAINING_PATTERN_DISABLE); |
| 691 | |
| 692 | /* disable the training pattern on the source */ |
Jerome Glisse | 5a96a89 | 2011-07-25 11:57:43 -0400 | [diff] [blame] | 693 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 694 | atombios_dig_encoder_setup(dp_info->encoder, |
| 695 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); |
| 696 | else |
| 697 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, |
| 698 | dp_info->dp_clock, dp_info->enc_id, 0); |
| 699 | |
| 700 | return 0; |
| 701 | } |
| 702 | |
| 703 | static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) |
| 704 | { |
| 705 | bool clock_recovery; |
| 706 | u8 voltage; |
| 707 | int i; |
| 708 | |
| 709 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); |
| 710 | memset(dp_info->train_set, 0, 4); |
| 711 | radeon_dp_update_vs_emph(dp_info); |
| 712 | |
| 713 | udelay(400); |
| 714 | |
| 715 | /* clock recovery loop */ |
| 716 | clock_recovery = false; |
| 717 | dp_info->tries = 0; |
| 718 | voltage = 0xff; |
| 719 | while (1) { |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 720 | drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 721 | |
Jerome Glisse | 8d1c702 | 2012-07-17 17:17:16 -0400 | [diff] [blame] | 722 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
| 723 | DRM_ERROR("displayport link status failed\n"); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 724 | break; |
Jerome Glisse | 8d1c702 | 2012-07-17 17:17:16 -0400 | [diff] [blame] | 725 | } |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 726 | |
Daniel Vetter | 0191627 | 2012-10-18 10:15:25 +0200 | [diff] [blame] | 727 | if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 728 | clock_recovery = true; |
| 729 | break; |
| 730 | } |
| 731 | |
| 732 | for (i = 0; i < dp_info->dp_lane_count; i++) { |
| 733 | if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 734 | break; |
| 735 | } |
| 736 | if (i == dp_info->dp_lane_count) { |
| 737 | DRM_ERROR("clock recovery reached max voltage\n"); |
| 738 | break; |
| 739 | } |
| 740 | |
| 741 | if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
| 742 | ++dp_info->tries; |
| 743 | if (dp_info->tries == 5) { |
| 744 | DRM_ERROR("clock recovery tried 5 times\n"); |
| 745 | break; |
| 746 | } |
| 747 | } else |
| 748 | dp_info->tries = 0; |
| 749 | |
| 750 | voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
| 751 | |
| 752 | /* Compute new train_set as requested by sink */ |
| 753 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
| 754 | |
| 755 | radeon_dp_update_vs_emph(dp_info); |
| 756 | } |
| 757 | if (!clock_recovery) { |
| 758 | DRM_ERROR("clock recovery failed\n"); |
| 759 | return -1; |
| 760 | } else { |
| 761 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
| 762 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
| 763 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
| 764 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
| 765 | return 0; |
| 766 | } |
| 767 | } |
| 768 | |
| 769 | static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) |
| 770 | { |
| 771 | bool channel_eq; |
| 772 | |
| 773 | if (dp_info->tp3_supported) |
| 774 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); |
| 775 | else |
| 776 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); |
| 777 | |
| 778 | /* channel equalization loop */ |
| 779 | dp_info->tries = 0; |
| 780 | channel_eq = false; |
| 781 | while (1) { |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 782 | drm_dp_link_train_channel_eq_delay(dp_info->dpcd); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 783 | |
Jerome Glisse | 8d1c702 | 2012-07-17 17:17:16 -0400 | [diff] [blame] | 784 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
| 785 | DRM_ERROR("displayport link status failed\n"); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 786 | break; |
Jerome Glisse | 8d1c702 | 2012-07-17 17:17:16 -0400 | [diff] [blame] | 787 | } |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 788 | |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 789 | if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 790 | channel_eq = true; |
| 791 | break; |
| 792 | } |
| 793 | |
| 794 | /* Try 5 times */ |
| 795 | if (dp_info->tries > 5) { |
| 796 | DRM_ERROR("channel eq failed: 5 tries\n"); |
| 797 | break; |
| 798 | } |
| 799 | |
| 800 | /* Compute new train_set as requested by sink */ |
| 801 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
| 802 | |
| 803 | radeon_dp_update_vs_emph(dp_info); |
| 804 | dp_info->tries++; |
| 805 | } |
| 806 | |
| 807 | if (!channel_eq) { |
| 808 | DRM_ERROR("channel eq failed\n"); |
| 809 | return -1; |
| 810 | } else { |
| 811 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
| 812 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
| 813 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) |
| 814 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
| 815 | return 0; |
| 816 | } |
| 817 | } |
| 818 | |
| 819 | void radeon_dp_link_train(struct drm_encoder *encoder, |
| 820 | struct drm_connector *connector) |
| 821 | { |
| 822 | struct drm_device *dev = encoder->dev; |
| 823 | struct radeon_device *rdev = dev->dev_private; |
| 824 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 825 | struct radeon_encoder_atom_dig *dig; |
| 826 | struct radeon_connector *radeon_connector; |
| 827 | struct radeon_connector_atom_dig *dig_connector; |
| 828 | struct radeon_dp_link_train_info dp_info; |
Jerome Glisse | 5a96a89 | 2011-07-25 11:57:43 -0400 | [diff] [blame] | 829 | int index; |
| 830 | u8 tmp, frev, crev; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 831 | |
| 832 | if (!radeon_encoder->enc_priv) |
| 833 | return; |
| 834 | dig = radeon_encoder->enc_priv; |
| 835 | |
| 836 | radeon_connector = to_radeon_connector(connector); |
| 837 | if (!radeon_connector->con_priv) |
| 838 | return; |
| 839 | dig_connector = radeon_connector->con_priv; |
| 840 | |
| 841 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
| 842 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) |
| 843 | return; |
| 844 | |
Jerome Glisse | 5a96a89 | 2011-07-25 11:57:43 -0400 | [diff] [blame] | 845 | /* DPEncoderService newer than 1.1 can't program properly the |
| 846 | * training pattern. When facing such version use the |
| 847 | * DIGXEncoderControl (X== 1 | 2) |
| 848 | */ |
| 849 | dp_info.use_dpencoder = true; |
| 850 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
| 851 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { |
| 852 | if (crev > 1) { |
| 853 | dp_info.use_dpencoder = false; |
| 854 | } |
| 855 | } |
| 856 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 857 | dp_info.enc_id = 0; |
| 858 | if (dig->dig_encoder) |
| 859 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; |
| 860 | else |
| 861 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; |
| 862 | if (dig->linkb) |
| 863 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; |
| 864 | else |
| 865 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; |
| 866 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 867 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT); |
| 868 | if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) |
| 869 | dp_info.tp3_supported = true; |
| 870 | else |
| 871 | dp_info.tp3_supported = false; |
| 872 | |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 873 | memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 874 | dp_info.rdev = rdev; |
| 875 | dp_info.encoder = encoder; |
| 876 | dp_info.connector = connector; |
| 877 | dp_info.radeon_connector = radeon_connector; |
| 878 | dp_info.dp_lane_count = dig_connector->dp_lane_count; |
| 879 | dp_info.dp_clock = dig_connector->dp_clock; |
| 880 | |
| 881 | if (radeon_dp_link_train_init(&dp_info)) |
| 882 | goto done; |
| 883 | if (radeon_dp_link_train_cr(&dp_info)) |
| 884 | goto done; |
| 885 | if (radeon_dp_link_train_ce(&dp_info)) |
| 886 | goto done; |
| 887 | done: |
| 888 | if (radeon_dp_link_train_finish(&dp_info)) |
| 889 | return; |
| 890 | } |