Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __ASM_SH_CACHEFLUSH_H |
| 2 | #define __ASM_SH_CACHEFLUSH_H |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 3 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | #ifdef __KERNEL__ |
| 5 | |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 6 | #ifdef CONFIG_CACHE_OFF |
| 7 | /* |
| 8 | * Nothing to do when the cache is disabled, initial flush and explicit |
| 9 | * disabling is handled at CPU init time. |
| 10 | * |
| 11 | * See arch/sh/kernel/cpu/init.c:cache_init(). |
| 12 | */ |
| 13 | #define p3_cache_init() do { } while (0) |
| 14 | #define flush_cache_all() do { } while (0) |
| 15 | #define flush_cache_mm(mm) do { } while (0) |
| 16 | #define flush_cache_dup_mm(mm) do { } while (0) |
| 17 | #define flush_cache_range(vma, start, end) do { } while (0) |
| 18 | #define flush_cache_page(vma, vmaddr, pfn) do { } while (0) |
| 19 | #define flush_dcache_page(page) do { } while (0) |
| 20 | #define flush_icache_range(start, end) do { } while (0) |
| 21 | #define flush_icache_page(vma,pg) do { } while (0) |
| 22 | #define flush_dcache_mmap_lock(mapping) do { } while (0) |
| 23 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) |
| 24 | #define flush_cache_sigtramp(vaddr) do { } while (0) |
| 25 | #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) |
| 26 | #define __flush_wback_region(start, size) do { (void)(start); } while (0) |
| 27 | #define __flush_purge_region(start, size) do { (void)(start); } while (0) |
| 28 | #define __flush_invalidate_region(start, size) do { (void)(start); } while (0) |
| 29 | #else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include <asm/cpu/cacheflush.h> |
| 31 | |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 32 | /* |
| 33 | * Consistent DMA requires that the __flush_xxx() primitives must be set |
| 34 | * for any of the enabled non-coherent caches (most of the UP CPUs), |
| 35 | * regardless of PIPT or VIPT cache configurations. |
| 36 | */ |
| 37 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | /* Flush (write-back only) a region (smaller than a page) */ |
| 39 | extern void __flush_wback_region(void *start, int size); |
| 40 | /* Flush (write-back & invalidate) a region (smaller than a page) */ |
| 41 | extern void __flush_purge_region(void *start, int size); |
| 42 | /* Flush (invalidate only) a region (smaller than a page) */ |
| 43 | extern void __flush_invalidate_region(void *start, int size); |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 44 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | |
| 46 | #define flush_cache_vmap(start, end) flush_cache_all() |
| 47 | #define flush_cache_vunmap(start, end) flush_cache_all() |
| 48 | |
| 49 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ |
| 50 | do { \ |
| 51 | flush_cache_page(vma, vaddr, page_to_pfn(page));\ |
| 52 | memcpy(dst, src, len); \ |
| 53 | flush_icache_user_range(vma, page, vaddr, len); \ |
| 54 | } while (0) |
| 55 | |
| 56 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |
| 57 | do { \ |
| 58 | flush_cache_page(vma, vaddr, page_to_pfn(page));\ |
| 59 | memcpy(dst, src, len); \ |
| 60 | } while (0) |
| 61 | |
Paul Mundt | f3c2575 | 2006-09-27 18:36:17 +0900 | [diff] [blame] | 62 | #define HAVE_ARCH_UNMAPPED_AREA |
| 63 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | #endif /* __KERNEL__ */ |
| 65 | #endif /* __ASM_SH_CACHEFLUSH_H */ |