blob: 31fd10df43a76a997ae6f8b002388fb1e703fdba [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* $Id: dma.h,v 1.2 1999/04/27 00:46:18 deller Exp $
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 * (c) Copyright 2000, Grant Grundler
7 */
8
9#ifndef _ASM_DMA_H
10#define _ASM_DMA_H
11
12#include <linux/config.h>
13#include <asm/io.h> /* need byte IO */
14#include <asm/system.h>
15
16#define dma_outb outb
17#define dma_inb inb
18
19/*
20** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
21** (or rather not merge) DMA's into managable chunks.
22** On parisc, this is more of the software/tuning constraint
23** rather than the HW. I/O MMU allocation alogorithms can be
24** faster with smaller size is (to some degree).
25*/
26#define DMA_CHUNK_SIZE (BITS_PER_LONG*PAGE_SIZE)
27
28/* The maximum address that we can perform a DMA transfer to on this platform
29** New dynamic DMA interfaces should obsolete this....
30*/
31#define MAX_DMA_ADDRESS (~0UL)
32
33/*
34** We don't have DMA channels... well V-class does but the
35** Dynamic DMA Mapping interface will support them... right? :^)
36** Note: this is not relevant right now for PA-RISC, but we cannot
37** leave this as undefined because some things (e.g. sound)
38** won't compile :-(
39*/
40#define MAX_DMA_CHANNELS 8
41#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
42#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
43#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
44
45#define DMA_AUTOINIT 0x10
46
47/* 8237 DMA controllers */
48#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
49#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
50
51/* DMA controller registers */
52#define DMA1_CMD_REG 0x08 /* command register (w) */
53#define DMA1_STAT_REG 0x08 /* status register (r) */
54#define DMA1_REQ_REG 0x09 /* request register (w) */
55#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
56#define DMA1_MODE_REG 0x0B /* mode register (w) */
57#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
58#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
59#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
60#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
61#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
62#define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
63
64#define DMA2_CMD_REG 0xD0 /* command register (w) */
65#define DMA2_STAT_REG 0xD0 /* status register (r) */
66#define DMA2_REQ_REG 0xD2 /* request register (w) */
67#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
68#define DMA2_MODE_REG 0xD6 /* mode register (w) */
69#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
70#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
71#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
72#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
73#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
74#define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
75
76extern spinlock_t dma_spin_lock;
77
78static __inline__ unsigned long claim_dma_lock(void)
79{
80 unsigned long flags;
81 spin_lock_irqsave(&dma_spin_lock, flags);
82 return flags;
83}
84
85static __inline__ void release_dma_lock(unsigned long flags)
86{
87 spin_unlock_irqrestore(&dma_spin_lock, flags);
88}
89
90
91/* Get DMA residue count. After a DMA transfer, this
92 * should return zero. Reading this while a DMA transfer is
93 * still in progress will return unpredictable results.
94 * If called before the channel has been used, it may return 1.
95 * Otherwise, it returns the number of _bytes_ left to transfer.
96 *
97 * Assumes DMA flip-flop is clear.
98 */
99static __inline__ int get_dma_residue(unsigned int dmanr)
100{
101 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
102 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
103
104 /* using short to get 16-bit wrap around */
105 unsigned short count;
106
107 count = 1 + dma_inb(io_port);
108 count += dma_inb(io_port) << 8;
109
110 return (dmanr<=3)? count : (count<<1);
111}
112
113/* enable/disable a specific DMA channel */
114static __inline__ void enable_dma(unsigned int dmanr)
115{
116#ifdef CONFIG_SUPERIO
117 if (dmanr<=3)
118 dma_outb(dmanr, DMA1_MASK_REG);
119 else
120 dma_outb(dmanr & 3, DMA2_MASK_REG);
121#endif
122}
123
124static __inline__ void disable_dma(unsigned int dmanr)
125{
126#ifdef CONFIG_SUPERIO
127 if (dmanr<=3)
128 dma_outb(dmanr | 4, DMA1_MASK_REG);
129 else
130 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
131#endif
132}
133
134/* reserve a DMA channel */
135#define request_dma(dmanr, device_id) (0)
136
137/* Clear the 'DMA Pointer Flip Flop'.
138 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
139 * Use this once to initialize the FF to a known state.
140 * After that, keep track of it. :-)
141 * --- In order to do that, the DMA routines below should ---
142 * --- only be used while holding the DMA lock ! ---
143 */
144static __inline__ void clear_dma_ff(unsigned int dmanr)
145{
146}
147
148/* set mode (above) for a specific DMA channel */
149static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
150{
151}
152
153/* Set only the page register bits of the transfer address.
154 * This is used for successive transfers when we know the contents of
155 * the lower 16 bits of the DMA current address register, but a 64k boundary
156 * may have been crossed.
157 */
158static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
159{
160}
161
162
163/* Set transfer address & page bits for specific DMA channel.
164 * Assumes dma flipflop is clear.
165 */
166static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
167{
168}
169
170
171/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
172 * a specific DMA channel.
173 * You must ensure the parameters are valid.
174 * NOTE: from a manual: "the number of transfers is one more
175 * than the initial word count"! This is taken into account.
176 * Assumes dma flip-flop is clear.
177 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
178 */
179static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
180{
181}
182
183
184#define free_dma(dmanr)
185
186#ifdef CONFIG_PCI
187extern int isa_dma_bridge_buggy;
188#else
189#define isa_dma_bridge_buggy (0)
190#endif
191
192#endif /* _ASM_DMA_H */