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Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001/*
2 * driver/mfd/asic3.c
3 *
4 * Compaq ASIC3 support.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2004-2005 Phil Blundell
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020012 * Copyright 2007-2008 OpenedHand Ltd.
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080013 *
14 * Authors: Phil Blundell <pb@handhelds.org>,
15 * Samuel Ortiz <sameo@openedhand.com>
16 *
17 */
18
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080019#include <linux/kernel.h>
Philipp Zabel9461f652009-06-15 12:10:24 +020020#include <linux/delay.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080021#include <linux/irq.h>
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020022#include <linux/gpio.h>
Paul Gortmaker5d4a3572011-07-10 12:41:10 -040023#include <linux/export.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080024#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090025#include <linux/slab.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080026#include <linux/spinlock.h>
27#include <linux/platform_device.h>
28
29#include <linux/mfd/asic3.h>
Philipp Zabel9461f652009-06-15 12:10:24 +020030#include <linux/mfd/core.h>
31#include <linux/mfd/ds1wm.h>
Philipp Zabel09f05ce2009-06-15 12:10:25 +020032#include <linux/mfd/tmio.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080033
Philipp Zabele956a2a2009-06-05 18:31:02 +020034enum {
35 ASIC3_CLOCK_SPI,
36 ASIC3_CLOCK_OWM,
37 ASIC3_CLOCK_PWM0,
38 ASIC3_CLOCK_PWM1,
39 ASIC3_CLOCK_LED0,
40 ASIC3_CLOCK_LED1,
41 ASIC3_CLOCK_LED2,
42 ASIC3_CLOCK_SD_HOST,
43 ASIC3_CLOCK_SD_BUS,
44 ASIC3_CLOCK_SMBUS,
45 ASIC3_CLOCK_EX0,
46 ASIC3_CLOCK_EX1,
47};
48
49struct asic3_clk {
50 int enabled;
51 unsigned int cdex;
52 unsigned long rate;
53};
54
55#define INIT_CDEX(_name, _rate) \
56 [ASIC3_CLOCK_##_name] = { \
57 .cdex = CLOCK_CDEX_##_name, \
58 .rate = _rate, \
59 }
60
Mark Brown59f2ad22010-12-11 12:59:35 +000061static struct asic3_clk asic3_clk_init[] __initdata = {
Philipp Zabele956a2a2009-06-05 18:31:02 +020062 INIT_CDEX(SPI, 0),
63 INIT_CDEX(OWM, 5000000),
64 INIT_CDEX(PWM0, 0),
65 INIT_CDEX(PWM1, 0),
66 INIT_CDEX(LED0, 0),
67 INIT_CDEX(LED1, 0),
68 INIT_CDEX(LED2, 0),
69 INIT_CDEX(SD_HOST, 24576000),
70 INIT_CDEX(SD_BUS, 12288000),
71 INIT_CDEX(SMBUS, 0),
72 INIT_CDEX(EX0, 32768),
73 INIT_CDEX(EX1, 24576000),
74};
75
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020076struct asic3 {
77 void __iomem *mapping;
78 unsigned int bus_shift;
79 unsigned int irq_nr;
80 unsigned int irq_base;
81 spinlock_t lock;
82 u16 irq_bothedge[4];
83 struct gpio_chip gpio;
84 struct device *dev;
Ian Molton64e88672010-01-06 13:51:48 +010085 void __iomem *tmio_cnf;
Philipp Zabele956a2a2009-06-05 18:31:02 +020086
87 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020088};
89
90static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
91
Paul Parsons13ca4f62011-05-13 18:53:03 +000092void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080093{
Al Virob32661e2008-03-29 03:10:58 +000094 iowrite16(value, asic->mapping +
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080095 (reg >> asic->bus_shift));
96}
Paul Parsons13ca4f62011-05-13 18:53:03 +000097EXPORT_SYMBOL_GPL(asic3_write_register);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080098
Paul Parsons13ca4f62011-05-13 18:53:03 +000099u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800100{
Al Virob32661e2008-03-29 03:10:58 +0000101 return ioread16(asic->mapping +
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800102 (reg >> asic->bus_shift));
103}
Paul Parsons13ca4f62011-05-13 18:53:03 +0000104EXPORT_SYMBOL_GPL(asic3_read_register);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800105
Mark Brown59f2ad22010-12-11 12:59:35 +0000106static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
Philipp Zabel6483c1b2009-06-05 18:31:01 +0200107{
108 unsigned long flags;
109 u32 val;
110
111 spin_lock_irqsave(&asic->lock, flags);
112 val = asic3_read_register(asic, reg);
113 if (set)
114 val |= bits;
115 else
116 val &= ~bits;
117 asic3_write_register(asic, reg, val);
118 spin_unlock_irqrestore(&asic->lock, flags);
119}
120
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800121/* IRQs */
122#define MAX_ASIC_ISR_LOOPS 20
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200123#define ASIC3_GPIO_BASE_INCR \
124 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800125
126static void asic3_irq_flip_edge(struct asic3 *asic,
127 u32 base, int bit)
128{
129 u16 edge;
130 unsigned long flags;
131
132 spin_lock_irqsave(&asic->lock, flags);
133 edge = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200134 base + ASIC3_GPIO_EDGE_TRIGGER);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800135 edge ^= bit;
136 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200137 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800138 spin_unlock_irqrestore(&asic->lock, flags);
139}
140
141static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
142{
Thomas Gleixner52a7d602011-03-25 11:12:26 +0000143 struct asic3 *asic = irq_desc_get_handler_data(desc);
144 struct irq_data *data = irq_desc_get_irq_data(desc);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800145 int iter, i;
146 unsigned long flags;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800147
Axel Lina09aee82011-04-14 22:43:47 +0800148 data->chip->irq_ack(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800149
150 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
151 u32 status;
152 int bank;
153
154 spin_lock_irqsave(&asic->lock, flags);
155 status = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200156 ASIC3_OFFSET(INTR, P_INT_STAT));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800157 spin_unlock_irqrestore(&asic->lock, flags);
158
159 /* Check all ten register bits */
160 if ((status & 0x3ff) == 0)
161 break;
162
163 /* Handle GPIO IRQs */
164 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
165 if (status & (1 << bank)) {
166 unsigned long base, istat;
167
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200168 base = ASIC3_GPIO_A_BASE
169 + bank * ASIC3_GPIO_BASE_INCR;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800170
171 spin_lock_irqsave(&asic->lock, flags);
172 istat = asic3_read_register(asic,
173 base +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200174 ASIC3_GPIO_INT_STATUS);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800175 /* Clearing IntStatus */
176 asic3_write_register(asic,
177 base +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200178 ASIC3_GPIO_INT_STATUS, 0);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800179 spin_unlock_irqrestore(&asic->lock, flags);
180
181 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
182 int bit = (1 << i);
183 unsigned int irqnr;
184
185 if (!(istat & bit))
186 continue;
187
188 irqnr = asic->irq_base +
189 (ASIC3_GPIOS_PER_BANK * bank)
190 + i;
Thomas Gleixner52a7d602011-03-25 11:12:26 +0000191 generic_handle_irq(irqnr);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800192 if (asic->irq_bothedge[bank] & bit)
193 asic3_irq_flip_edge(asic, base,
194 bit);
195 }
196 }
197 }
198
199 /* Handle remaining IRQs in the status register */
200 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
201 /* They start at bit 4 and go up */
Thomas Gleixner52a7d602011-03-25 11:12:26 +0000202 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
203 generic_handle_irq(asic->irq_base + i);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800204 }
205 }
206
207 if (iter >= MAX_ASIC_ISR_LOOPS)
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200208 dev_err(asic->dev, "interrupt processing overrun\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800209}
210
211static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
212{
213 int n;
214
215 n = (irq - asic->irq_base) >> 4;
216
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200217 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800218}
219
220static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
221{
222 return (irq - asic->irq_base) & 0xf;
223}
224
Mark Brown0f76aae2010-12-11 13:08:57 +0000225static void asic3_mask_gpio_irq(struct irq_data *data)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800226{
Mark Brown0f76aae2010-12-11 13:08:57 +0000227 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800228 u32 val, bank, index;
229 unsigned long flags;
230
Mark Brown0f76aae2010-12-11 13:08:57 +0000231 bank = asic3_irq_to_bank(asic, data->irq);
232 index = asic3_irq_to_index(asic, data->irq);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800233
234 spin_lock_irqsave(&asic->lock, flags);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200235 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800236 val |= 1 << index;
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200237 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800238 spin_unlock_irqrestore(&asic->lock, flags);
239}
240
Mark Brown0f76aae2010-12-11 13:08:57 +0000241static void asic3_mask_irq(struct irq_data *data)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800242{
Mark Brown0f76aae2010-12-11 13:08:57 +0000243 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800244 int regval;
245 unsigned long flags;
246
247 spin_lock_irqsave(&asic->lock, flags);
248 regval = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200249 ASIC3_INTR_BASE +
250 ASIC3_INTR_INT_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800251
252 regval &= ~(ASIC3_INTMASK_MASK0 <<
Mark Brown0f76aae2010-12-11 13:08:57 +0000253 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800254
255 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200256 ASIC3_INTR_BASE +
257 ASIC3_INTR_INT_MASK,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800258 regval);
259 spin_unlock_irqrestore(&asic->lock, flags);
260}
261
Mark Brown0f76aae2010-12-11 13:08:57 +0000262static void asic3_unmask_gpio_irq(struct irq_data *data)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800263{
Mark Brown0f76aae2010-12-11 13:08:57 +0000264 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800265 u32 val, bank, index;
266 unsigned long flags;
267
Mark Brown0f76aae2010-12-11 13:08:57 +0000268 bank = asic3_irq_to_bank(asic, data->irq);
269 index = asic3_irq_to_index(asic, data->irq);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800270
271 spin_lock_irqsave(&asic->lock, flags);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200272 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800273 val &= ~(1 << index);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200274 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800275 spin_unlock_irqrestore(&asic->lock, flags);
276}
277
Mark Brown0f76aae2010-12-11 13:08:57 +0000278static void asic3_unmask_irq(struct irq_data *data)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800279{
Mark Brown0f76aae2010-12-11 13:08:57 +0000280 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800281 int regval;
282 unsigned long flags;
283
284 spin_lock_irqsave(&asic->lock, flags);
285 regval = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200286 ASIC3_INTR_BASE +
287 ASIC3_INTR_INT_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800288
289 regval |= (ASIC3_INTMASK_MASK0 <<
Mark Brown0f76aae2010-12-11 13:08:57 +0000290 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800291
292 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200293 ASIC3_INTR_BASE +
294 ASIC3_INTR_INT_MASK,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800295 regval);
296 spin_unlock_irqrestore(&asic->lock, flags);
297}
298
Mark Brown0f76aae2010-12-11 13:08:57 +0000299static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800300{
Mark Brown0f76aae2010-12-11 13:08:57 +0000301 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800302 u32 bank, index;
303 u16 trigger, level, edge, bit;
304 unsigned long flags;
305
Mark Brown0f76aae2010-12-11 13:08:57 +0000306 bank = asic3_irq_to_bank(asic, data->irq);
307 index = asic3_irq_to_index(asic, data->irq);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800308 bit = 1<<index;
309
310 spin_lock_irqsave(&asic->lock, flags);
311 level = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200312 bank + ASIC3_GPIO_LEVEL_TRIGGER);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800313 edge = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200314 bank + ASIC3_GPIO_EDGE_TRIGGER);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800315 trigger = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200316 bank + ASIC3_GPIO_TRIGGER_TYPE);
Mark Brown0f76aae2010-12-11 13:08:57 +0000317 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800318
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100319 if (type == IRQ_TYPE_EDGE_RISING) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800320 trigger |= bit;
321 edge |= bit;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100322 } else if (type == IRQ_TYPE_EDGE_FALLING) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800323 trigger |= bit;
324 edge &= ~bit;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100325 } else if (type == IRQ_TYPE_EDGE_BOTH) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800326 trigger |= bit;
Mark Brown0f76aae2010-12-11 13:08:57 +0000327 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800328 edge &= ~bit;
329 else
330 edge |= bit;
Mark Brown0f76aae2010-12-11 13:08:57 +0000331 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100332 } else if (type == IRQ_TYPE_LEVEL_LOW) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800333 trigger &= ~bit;
334 level &= ~bit;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100335 } else if (type == IRQ_TYPE_LEVEL_HIGH) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800336 trigger &= ~bit;
337 level |= bit;
338 } else {
339 /*
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100340 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800341 * be careful to not unmask them if mask was also called.
342 * Probably need internal state for mask.
343 */
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200344 dev_notice(asic->dev, "irq type not changed\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800345 }
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200346 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800347 level);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200348 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800349 edge);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200350 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800351 trigger);
352 spin_unlock_irqrestore(&asic->lock, flags);
353 return 0;
354}
355
Paul Parsons2fe372f2012-04-11 00:35:34 +0100356static int asic3_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
357{
358 struct asic3 *asic = irq_data_get_irq_chip_data(data);
359 u32 bank, index;
360 u16 bit;
361
362 bank = asic3_irq_to_bank(asic, data->irq);
363 index = asic3_irq_to_index(asic, data->irq);
364 bit = 1<<index;
365
366 asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on);
367
368 return 0;
369}
370
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800371static struct irq_chip asic3_gpio_irq_chip = {
372 .name = "ASIC3-GPIO",
Mark Brown0f76aae2010-12-11 13:08:57 +0000373 .irq_ack = asic3_mask_gpio_irq,
374 .irq_mask = asic3_mask_gpio_irq,
375 .irq_unmask = asic3_unmask_gpio_irq,
376 .irq_set_type = asic3_gpio_irq_type,
Paul Parsons2fe372f2012-04-11 00:35:34 +0100377 .irq_set_wake = asic3_gpio_irq_set_wake,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800378};
379
380static struct irq_chip asic3_irq_chip = {
381 .name = "ASIC3",
Mark Brown0f76aae2010-12-11 13:08:57 +0000382 .irq_ack = asic3_mask_irq,
383 .irq_mask = asic3_mask_irq,
384 .irq_unmask = asic3_unmask_irq,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800385};
386
Philipp Zabel065032f2008-06-21 00:51:38 +0200387static int __init asic3_irq_probe(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800388{
389 struct asic3 *asic = platform_get_drvdata(pdev);
390 unsigned long clksel = 0;
391 unsigned int irq, irq_base;
Roel Kluinc491b2f2008-07-25 19:44:41 -0700392 int ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800393
Roel Kluinc491b2f2008-07-25 19:44:41 -0700394 ret = platform_get_irq(pdev, 0);
395 if (ret < 0)
396 return ret;
397 asic->irq_nr = ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800398
399 /* turn on clock to IRQ controller */
400 clksel |= CLOCK_SEL_CX;
401 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
402 clksel);
403
404 irq_base = asic->irq_base;
405
406 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
407 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000408 irq_set_chip(irq, &asic3_gpio_irq_chip);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800409 else
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000410 irq_set_chip(irq, &asic3_irq_chip);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800411
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000412 irq_set_chip_data(irq, asic);
413 irq_set_handler(irq, handle_level_irq);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800414 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
415 }
416
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200417 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800418 ASIC3_INTMASK_GINTMASK);
419
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000420 irq_set_chained_handler(asic->irq_nr, asic3_irq_demux);
421 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
422 irq_set_handler_data(asic->irq_nr, asic);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800423
424 return 0;
425}
426
427static void asic3_irq_remove(struct platform_device *pdev)
428{
429 struct asic3 *asic = platform_get_drvdata(pdev);
430 unsigned int irq, irq_base;
431
432 irq_base = asic->irq_base;
433
434 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
435 set_irq_flags(irq, 0);
Thomas Gleixnerd6f7ce9f2011-03-25 11:12:35 +0000436 irq_set_chip_and_handler(irq, NULL, NULL);
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000437 irq_set_chip_data(irq, NULL);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800438 }
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000439 irq_set_chained_handler(asic->irq_nr, NULL);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800440}
441
442/* GPIOs */
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200443static int asic3_gpio_direction(struct gpio_chip *chip,
444 unsigned offset, int out)
445{
446 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
447 unsigned int gpio_base;
448 unsigned long flags;
449 struct asic3 *asic;
450
451 asic = container_of(chip, struct asic3, gpio);
452 gpio_base = ASIC3_GPIO_TO_BASE(offset);
453
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200454 if (gpio_base > ASIC3_GPIO_D_BASE) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200455 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
456 gpio_base, offset);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200457 return -EINVAL;
458 }
459
460 spin_lock_irqsave(&asic->lock, flags);
461
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200462 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200463
464 /* Input is 0, Output is 1 */
465 if (out)
466 out_reg |= mask;
467 else
468 out_reg &= ~mask;
469
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200470 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200471
472 spin_unlock_irqrestore(&asic->lock, flags);
473
474 return 0;
475
476}
477
478static int asic3_gpio_direction_input(struct gpio_chip *chip,
479 unsigned offset)
480{
481 return asic3_gpio_direction(chip, offset, 0);
482}
483
484static int asic3_gpio_direction_output(struct gpio_chip *chip,
485 unsigned offset, int value)
486{
487 return asic3_gpio_direction(chip, offset, 1);
488}
489
490static int asic3_gpio_get(struct gpio_chip *chip,
491 unsigned offset)
492{
493 unsigned int gpio_base;
494 u32 mask = ASIC3_GPIO_TO_MASK(offset);
495 struct asic3 *asic;
496
497 asic = container_of(chip, struct asic3, gpio);
498 gpio_base = ASIC3_GPIO_TO_BASE(offset);
499
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200500 if (gpio_base > ASIC3_GPIO_D_BASE) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200501 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
502 gpio_base, offset);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200503 return -EINVAL;
504 }
505
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200506 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200507}
508
509static void asic3_gpio_set(struct gpio_chip *chip,
510 unsigned offset, int value)
511{
512 u32 mask, out_reg;
513 unsigned int gpio_base;
514 unsigned long flags;
515 struct asic3 *asic;
516
517 asic = container_of(chip, struct asic3, gpio);
518 gpio_base = ASIC3_GPIO_TO_BASE(offset);
519
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200520 if (gpio_base > ASIC3_GPIO_D_BASE) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200521 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
522 gpio_base, offset);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200523 return;
524 }
525
526 mask = ASIC3_GPIO_TO_MASK(offset);
527
528 spin_lock_irqsave(&asic->lock, flags);
529
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200530 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200531
532 if (value)
533 out_reg |= mask;
534 else
535 out_reg &= ~mask;
536
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200537 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200538
539 spin_unlock_irqrestore(&asic->lock, flags);
540
541 return;
542}
543
Paul Parsons450b1152012-01-31 01:18:35 +0000544static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
545{
Dmitry Artamonow02269ab2012-04-12 15:33:34 +0400546 struct asic3 *asic = container_of(chip, struct asic3, gpio);
547
Samuel Ortiz12693f62012-04-16 21:28:29 +0200548 return asic->irq_base + offset;
Paul Parsons450b1152012-01-31 01:18:35 +0000549}
550
Philipp Zabel065032f2008-06-21 00:51:38 +0200551static __init int asic3_gpio_probe(struct platform_device *pdev,
552 u16 *gpio_config, int num)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800553{
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800554 struct asic3 *asic = platform_get_drvdata(pdev);
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200555 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
556 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
557 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
558 int i;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800559
Russell King59f0cb02008-10-27 11:24:09 +0000560 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
561 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
562 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200563
564 /* Enable all GPIOs */
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200565 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
566 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
567 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
568 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800569
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200570 for (i = 0; i < num; i++) {
571 u8 alt, pin, dir, init, bank_num, bit_num;
572 u16 config = gpio_config[i];
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800573
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200574 pin = ASIC3_CONFIG_GPIO_PIN(config);
575 alt = ASIC3_CONFIG_GPIO_ALT(config);
576 dir = ASIC3_CONFIG_GPIO_DIR(config);
577 init = ASIC3_CONFIG_GPIO_INIT(config);
578
579 bank_num = ASIC3_GPIO_TO_BANK(pin);
580 bit_num = ASIC3_GPIO_TO_BIT(pin);
581
582 alt_reg[bank_num] |= (alt << bit_num);
583 out_reg[bank_num] |= (init << bit_num);
584 dir_reg[bank_num] |= (dir << bit_num);
585 }
586
587 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
588 asic3_write_register(asic,
589 ASIC3_BANK_TO_BASE(i) +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200590 ASIC3_GPIO_DIRECTION,
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200591 dir_reg[i]);
592 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200593 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200594 out_reg[i]);
595 asic3_write_register(asic,
596 ASIC3_BANK_TO_BASE(i) +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200597 ASIC3_GPIO_ALT_FUNCTION,
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200598 alt_reg[i]);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800599 }
600
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200601 return gpiochip_add(&asic->gpio);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800602}
603
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200604static int asic3_gpio_remove(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800605{
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200606 struct asic3 *asic = platform_get_drvdata(pdev);
607
abdoulaye berthe88d5e522014-07-12 22:30:14 +0200608 gpiochip_remove(&asic->gpio);
609 return 0;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800610}
611
Paul Parsonsc29a8122011-08-09 16:27:43 +0000612static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
Philipp Zabele956a2a2009-06-05 18:31:02 +0200613{
614 unsigned long flags;
615 u32 cdex;
616
617 spin_lock_irqsave(&asic->lock, flags);
618 if (clk->enabled++ == 0) {
619 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
620 cdex |= clk->cdex;
621 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
622 }
623 spin_unlock_irqrestore(&asic->lock, flags);
Philipp Zabele956a2a2009-06-05 18:31:02 +0200624}
625
626static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
627{
628 unsigned long flags;
629 u32 cdex;
630
631 WARN_ON(clk->enabled == 0);
632
633 spin_lock_irqsave(&asic->lock, flags);
634 if (--clk->enabled == 0) {
635 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
636 cdex &= ~clk->cdex;
637 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
638 }
639 spin_unlock_irqrestore(&asic->lock, flags);
640}
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800641
Philipp Zabel9461f652009-06-15 12:10:24 +0200642/* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
643static struct ds1wm_driver_data ds1wm_pdata = {
644 .active_high = 1,
Jean-François Dagenaisf607e7f2011-07-08 15:39:44 -0700645 .reset_recover_delay = 1,
Philipp Zabel9461f652009-06-15 12:10:24 +0200646};
647
648static struct resource ds1wm_resources[] = {
649 {
650 .start = ASIC3_OWM_BASE,
651 .end = ASIC3_OWM_BASE + 0x13,
652 .flags = IORESOURCE_MEM,
653 },
654 {
655 .start = ASIC3_IRQ_OWM,
Mark Brownfe421422010-12-11 13:00:34 +0000656 .end = ASIC3_IRQ_OWM,
Philipp Zabel9461f652009-06-15 12:10:24 +0200657 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
658 },
659};
660
661static int ds1wm_enable(struct platform_device *pdev)
662{
663 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
664
665 /* Turn on external clocks and the OWM clock */
666 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
667 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
668 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
669 msleep(1);
670
671 /* Reset and enable DS1WM */
672 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
673 ASIC3_EXTCF_OWM_RESET, 1);
674 msleep(1);
675 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
676 ASIC3_EXTCF_OWM_RESET, 0);
677 msleep(1);
678 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
679 ASIC3_EXTCF_OWM_EN, 1);
680 msleep(1);
681
682 return 0;
683}
684
685static int ds1wm_disable(struct platform_device *pdev)
686{
687 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
688
689 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
690 ASIC3_EXTCF_OWM_EN, 0);
691
692 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
693 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
694 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
695
696 return 0;
697}
698
Geert Uytterhoeven5ac98552013-11-18 14:33:06 +0100699static const struct mfd_cell asic3_cell_ds1wm = {
Philipp Zabel9461f652009-06-15 12:10:24 +0200700 .name = "ds1wm",
701 .enable = ds1wm_enable,
702 .disable = ds1wm_disable,
Samuel Ortiz121ea572011-04-06 11:41:03 +0200703 .platform_data = &ds1wm_pdata,
704 .pdata_size = sizeof(ds1wm_pdata),
Philipp Zabel9461f652009-06-15 12:10:24 +0200705 .num_resources = ARRAY_SIZE(ds1wm_resources),
706 .resources = ds1wm_resources,
707};
708
Ian Molton64e88672010-01-06 13:51:48 +0100709static void asic3_mmc_pwr(struct platform_device *pdev, int state)
710{
711 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
712
713 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
714}
715
716static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
717{
718 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
719
720 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
721}
722
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200723static struct tmio_mmc_data asic3_mmc_data = {
Ian Molton64e88672010-01-06 13:51:48 +0100724 .hclk = 24576000,
725 .set_pwr = asic3_mmc_pwr,
726 .set_clk_div = asic3_mmc_clk_div,
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200727};
728
729static struct resource asic3_mmc_resources[] = {
730 {
731 .start = ASIC3_SD_CTRL_BASE,
732 .end = ASIC3_SD_CTRL_BASE + 0x3ff,
733 .flags = IORESOURCE_MEM,
734 },
735 {
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200736 .start = 0,
737 .end = 0,
738 .flags = IORESOURCE_IRQ,
739 },
740};
741
742static int asic3_mmc_enable(struct platform_device *pdev)
743{
744 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
745
746 /* Not sure if it must be done bit by bit, but leaving as-is */
747 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
748 ASIC3_SDHWCTRL_LEVCD, 1);
749 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
750 ASIC3_SDHWCTRL_LEVWP, 1);
751 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
752 ASIC3_SDHWCTRL_SUSPEND, 0);
753 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
754 ASIC3_SDHWCTRL_PCLR, 0);
755
756 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
757 /* CLK32 used for card detection and for interruption detection
758 * when HCLK is stopped.
759 */
760 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
761 msleep(1);
762
763 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
764 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
765 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
766
767 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
768 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
769 msleep(1);
770
771 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
772 ASIC3_EXTCF_SD_MEM_ENABLE, 1);
773
774 /* Enable SD card slot 3.3V power supply */
775 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
776 ASIC3_SDHWCTRL_SDPWR, 1);
777
Ian Molton64e88672010-01-06 13:51:48 +0100778 /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
779 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
780 ASIC3_SD_CTRL_BASE >> 1);
781
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200782 return 0;
783}
784
785static int asic3_mmc_disable(struct platform_device *pdev)
786{
787 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
788
789 /* Put in suspend mode */
790 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
791 ASIC3_SDHWCTRL_SUSPEND, 1);
792
793 /* Disable clocks */
794 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
795 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
796 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
797 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
798 return 0;
799}
800
Geert Uytterhoeven5ac98552013-11-18 14:33:06 +0100801static const struct mfd_cell asic3_cell_mmc = {
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200802 .name = "tmio-mmc",
803 .enable = asic3_mmc_enable,
804 .disable = asic3_mmc_disable,
Paul Parsons3c6e3652011-08-09 16:27:24 +0000805 .suspend = asic3_mmc_disable,
806 .resume = asic3_mmc_enable,
Samuel Ortizec719742011-04-06 11:38:14 +0200807 .platform_data = &asic3_mmc_data,
808 .pdata_size = sizeof(asic3_mmc_data),
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200809 .num_resources = ARRAY_SIZE(asic3_mmc_resources),
810 .resources = asic3_mmc_resources,
811};
812
Paul Parsons13ca4f62011-05-13 18:53:03 +0000813static const int clock_ledn[ASIC3_NUM_LEDS] = {
814 [0] = ASIC3_CLOCK_LED0,
815 [1] = ASIC3_CLOCK_LED1,
816 [2] = ASIC3_CLOCK_LED2,
817};
818
819static int asic3_leds_enable(struct platform_device *pdev)
820{
821 const struct mfd_cell *cell = mfd_get_cell(pdev);
822 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
823
824 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
825
826 return 0;
827}
828
829static int asic3_leds_disable(struct platform_device *pdev)
830{
831 const struct mfd_cell *cell = mfd_get_cell(pdev);
832 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
833
834 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
835
836 return 0;
837}
838
Paul Parsonse0b13b52011-08-09 16:27:33 +0000839static int asic3_leds_suspend(struct platform_device *pdev)
840{
841 const struct mfd_cell *cell = mfd_get_cell(pdev);
842 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
843
844 while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0)
845 msleep(1);
846
847 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
848
849 return 0;
850}
851
Paul Parsons13ca4f62011-05-13 18:53:03 +0000852static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = {
853 [0] = {
854 .name = "leds-asic3",
855 .id = 0,
856 .enable = asic3_leds_enable,
857 .disable = asic3_leds_disable,
Paul Parsonse0b13b52011-08-09 16:27:33 +0000858 .suspend = asic3_leds_suspend,
859 .resume = asic3_leds_enable,
Paul Parsons13ca4f62011-05-13 18:53:03 +0000860 },
861 [1] = {
862 .name = "leds-asic3",
863 .id = 1,
864 .enable = asic3_leds_enable,
865 .disable = asic3_leds_disable,
Paul Parsonse0b13b52011-08-09 16:27:33 +0000866 .suspend = asic3_leds_suspend,
867 .resume = asic3_leds_enable,
Paul Parsons13ca4f62011-05-13 18:53:03 +0000868 },
869 [2] = {
870 .name = "leds-asic3",
871 .id = 2,
872 .enable = asic3_leds_enable,
873 .disable = asic3_leds_disable,
Paul Parsonse0b13b52011-08-09 16:27:33 +0000874 .suspend = asic3_leds_suspend,
875 .resume = asic3_leds_enable,
Paul Parsons13ca4f62011-05-13 18:53:03 +0000876 },
877};
878
Philipp Zabel9461f652009-06-15 12:10:24 +0200879static int __init asic3_mfd_probe(struct platform_device *pdev,
Paul Parsons13ca4f62011-05-13 18:53:03 +0000880 struct asic3_platform_data *pdata,
Philipp Zabel9461f652009-06-15 12:10:24 +0200881 struct resource *mem)
882{
883 struct asic3 *asic = platform_get_drvdata(pdev);
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200884 struct resource *mem_sdio;
885 int irq, ret;
886
887 mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
888 if (!mem_sdio)
889 dev_dbg(asic->dev, "no SDIO MEM resource\n");
890
891 irq = platform_get_irq(pdev, 1);
892 if (irq < 0)
893 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
Philipp Zabel9461f652009-06-15 12:10:24 +0200894
895 /* DS1WM */
896 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
897 ASIC3_EXTCF_OWM_SMB, 0);
898
899 ds1wm_resources[0].start >>= asic->bus_shift;
900 ds1wm_resources[0].end >>= asic->bus_shift;
901
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200902 /* MMC */
Sachin Kamat44b61a92014-06-10 15:30:34 +0530903 if (mem_sdio) {
904 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) +
Paul Parsons74e32d12011-05-15 14:13:11 +0000905 mem_sdio->start,
906 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
Sachin Kamat44b61a92014-06-10 15:30:34 +0530907 if (!asic->tmio_cnf) {
908 ret = -ENOMEM;
909 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
910 goto out;
911 }
Ian Molton64e88672010-01-06 13:51:48 +0100912 }
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200913 asic3_mmc_resources[0].start >>= asic->bus_shift;
914 asic3_mmc_resources[0].end >>= asic->bus_shift;
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200915
Paul Parsons4f304242012-04-09 13:18:31 +0100916 if (pdata->clock_rate) {
917 ds1wm_pdata.clock_rate = pdata->clock_rate;
918 ret = mfd_add_devices(&pdev->dev, pdev->id,
Mark Brown0848c942012-09-11 15:16:36 +0800919 &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL);
Paul Parsons4f304242012-04-09 13:18:31 +0100920 if (ret < 0)
921 goto out;
922 }
Philipp Zabel9461f652009-06-15 12:10:24 +0200923
Paul Parsons13ca4f62011-05-13 18:53:03 +0000924 if (mem_sdio && (irq >= 0)) {
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200925 ret = mfd_add_devices(&pdev->dev, pdev->id,
Mark Brown0848c942012-09-11 15:16:36 +0800926 &asic3_cell_mmc, 1, mem_sdio, irq, NULL);
Paul Parsons13ca4f62011-05-13 18:53:03 +0000927 if (ret < 0)
928 goto out;
929 }
930
Arnd Bergmannb2f0fa82012-08-04 06:20:49 +0000931 ret = 0;
Paul Parsons13ca4f62011-05-13 18:53:03 +0000932 if (pdata->leds) {
933 int i;
934
935 for (i = 0; i < ASIC3_NUM_LEDS; ++i) {
936 asic3_cell_leds[i].platform_data = &pdata->leds[i];
937 asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]);
938 }
939 ret = mfd_add_devices(&pdev->dev, 0,
Mark Brown0848c942012-09-11 15:16:36 +0800940 asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0, NULL);
Paul Parsons13ca4f62011-05-13 18:53:03 +0000941 }
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200942
943 out:
Philipp Zabel9461f652009-06-15 12:10:24 +0200944 return ret;
945}
946
947static void asic3_mfd_remove(struct platform_device *pdev)
948{
Ian Molton64e88672010-01-06 13:51:48 +0100949 struct asic3 *asic = platform_get_drvdata(pdev);
950
Philipp Zabel9461f652009-06-15 12:10:24 +0200951 mfd_remove_devices(&pdev->dev);
Ian Molton64e88672010-01-06 13:51:48 +0100952 iounmap(asic->tmio_cnf);
Philipp Zabel9461f652009-06-15 12:10:24 +0200953}
954
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800955/* Core */
Philipp Zabel065032f2008-06-21 00:51:38 +0200956static int __init asic3_probe(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800957{
Jingoo Han334a41c2013-07-30 17:10:05 +0900958 struct asic3_platform_data *pdata = dev_get_platdata(&pdev->dev);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800959 struct asic3 *asic;
960 struct resource *mem;
961 unsigned long clksel;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200962 int ret = 0;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800963
Lee Jones1cee87f2013-05-23 16:25:09 +0100964 asic = devm_kzalloc(&pdev->dev,
965 sizeof(struct asic3), GFP_KERNEL);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200966 if (asic == NULL) {
967 printk(KERN_ERR "kzalloc failed\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800968 return -ENOMEM;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200969 }
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800970
971 spin_lock_init(&asic->lock);
972 platform_set_drvdata(pdev, asic);
973 asic->dev = &pdev->dev;
974
975 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
976 if (!mem) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200977 dev_err(asic->dev, "no MEM resource\n");
Lee Jones1cee87f2013-05-23 16:25:09 +0100978 return -ENOMEM;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800979 }
980
Philipp Zabelbe584bd2009-06-05 18:31:04 +0200981 asic->mapping = ioremap(mem->start, resource_size(mem));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800982 if (!asic->mapping) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200983 dev_err(asic->dev, "Couldn't ioremap\n");
Lee Jones1cee87f2013-05-23 16:25:09 +0100984 return -ENOMEM;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800985 }
986
987 asic->irq_base = pdata->irq_base;
988
Philipp Zabel99cdb0c2008-07-10 02:17:02 +0200989 /* calculate bus shift from mem resource */
Philipp Zabelbe584bd2009-06-05 18:31:04 +0200990 asic->bus_shift = 2 - (resource_size(mem) >> 12);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800991
992 clksel = 0;
993 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
994
995 ret = asic3_irq_probe(pdev);
996 if (ret < 0) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200997 dev_err(asic->dev, "Couldn't probe IRQs\n");
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200998 goto out_unmap;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800999 }
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001000
Paul Parsonsd8e4a882011-08-09 16:27:50 +00001001 asic->gpio.label = "asic3";
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001002 asic->gpio.base = pdata->gpio_base;
1003 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
1004 asic->gpio.get = asic3_gpio_get;
1005 asic->gpio.set = asic3_gpio_set;
1006 asic->gpio.direction_input = asic3_gpio_direction_input;
1007 asic->gpio.direction_output = asic3_gpio_direction_output;
Paul Parsons450b1152012-01-31 01:18:35 +00001008 asic->gpio.to_irq = asic3_gpio_to_irq;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001009
Samuel Ortiz3b26bf12008-06-20 11:09:51 +02001010 ret = asic3_gpio_probe(pdev,
1011 pdata->gpio_config,
1012 pdata->gpio_config_num);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001013 if (ret < 0) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +02001014 dev_err(asic->dev, "GPIO probe failed\n");
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001015 goto out_irq;
1016 }
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001017
Philipp Zabele956a2a2009-06-05 18:31:02 +02001018 /* Making a per-device copy is only needed for the
1019 * theoretical case of multiple ASIC3s on one board:
1020 */
1021 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
1022
Paul Parsons13ca4f62011-05-13 18:53:03 +00001023 asic3_mfd_probe(pdev, pdata, mem);
Philipp Zabel9461f652009-06-15 12:10:24 +02001024
Paul Parsonsf22a9c62012-04-05 17:45:04 +01001025 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1026 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 1);
1027
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +02001028 dev_info(asic->dev, "ASIC3 Core driver\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001029
1030 return 0;
1031
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001032 out_irq:
1033 asic3_irq_remove(pdev);
1034
1035 out_unmap:
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001036 iounmap(asic->mapping);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001037
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001038 return ret;
1039}
1040
Bill Pemberton4740f732012-11-19 13:26:01 -05001041static int asic3_remove(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001042{
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001043 int ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001044 struct asic3 *asic = platform_get_drvdata(pdev);
1045
Paul Parsonsf22a9c62012-04-05 17:45:04 +01001046 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1047 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 0);
1048
Philipp Zabel9461f652009-06-15 12:10:24 +02001049 asic3_mfd_remove(pdev);
1050
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001051 ret = asic3_gpio_remove(pdev);
1052 if (ret < 0)
1053 return ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001054 asic3_irq_remove(pdev);
1055
1056 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1057
1058 iounmap(asic->mapping);
1059
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001060 return 0;
1061}
1062
1063static void asic3_shutdown(struct platform_device *pdev)
1064{
1065}
1066
1067static struct platform_driver asic3_device_driver = {
1068 .driver = {
1069 .name = "asic3",
1070 },
Bill Pemberton84449212012-11-19 13:20:24 -05001071 .remove = asic3_remove,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001072 .shutdown = asic3_shutdown,
1073};
1074
1075static int __init asic3_init(void)
1076{
1077 int retval = 0;
Philipp Zabel065032f2008-06-21 00:51:38 +02001078 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001079 return retval;
1080}
1081
1082subsys_initcall(asic3_init);