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gerrit-public.fairphone.software / kernel / msm-4.9 / 3a843d7cd30ab6815610d9d6aa66b56df0ee1228 / . / include / asm-powerpc / cputable.h
blob: d1cfa3f515ea2d2162941c42ea534a567d22d7b5 [file] [log] [blame]
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#include <linux/config.h>
David Gibson3ddfbcf2005-11-10 12:56:55 +1100[diff] [blame]5#include <asm/asm-compat.h>
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]6
7#define PPC_FEATURE_32 0x80000000
8#define PPC_FEATURE_64 0x40000000
9#define PPC_FEATURE_601_INSTR 0x20000000
10#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
11#define PPC_FEATURE_HAS_FPU 0x08000000
12#define PPC_FEATURE_HAS_MMU 0x04000000
13#define PPC_FEATURE_HAS_4xxMAC 0x02000000
14#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
15#define PPC_FEATURE_HAS_SPE 0x00800000
16#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
17#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras98599012005-10-22 16:51:34 +1000[diff] [blame]18#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerrasa7ddc5e2005-11-10 14:29:18 +1100[diff] [blame]19#define PPC_FEATURE_POWER4 0x00080000
20#define PPC_FEATURE_POWER5 0x00040000
21#define PPC_FEATURE_POWER5_PLUS 0x00020000
22#define PPC_FEATURE_CELL 0x00010000
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]23
24#ifdef __KERNEL__
25#ifndef __ASSEMBLY__
26
27/* This structure can grow, it's real size is used by head.S code
28 * via the mkdefs mechanism.
29 */
30struct cpu_spec;
31struct op_powerpc_model;
32
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]33typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]34
35struct cpu_spec {
36 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
37 unsigned int pvr_mask;
38 unsigned int pvr_value;
39
40 char *cpu_name;
41 unsigned long cpu_features; /* Kernel features */
42 unsigned int cpu_user_features; /* Userland features */
43
44 /* cache line sizes */
45 unsigned int icache_bsize;
46 unsigned int dcache_bsize;
47
48 /* number of performance monitor counters */
49 unsigned int num_pmcs;
50
51 /* this is called to initialize various CPU bits like L1 cache,
52 * BHT, SPD, etc... from head.S before branching to identify_machine
53 */
54 cpu_setup_t cpu_setup;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]55
56 /* Used by oprofile userspace to select the right counters */
57 char *oprofile_cpu_type;
58
59 /* Processor specific oprofile operations */
60 struct op_powerpc_model *oprofile_model;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]61};
62
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]63extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]64
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000[diff] [blame]65extern void identify_cpu(unsigned long offset, unsigned long cpu);
66extern void do_cpu_ftr_fixups(unsigned long offset);
67
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]68#endif /* __ASSEMBLY__ */
69
70/* CPU kernel features */
71
72/* Retain the 32b definitions all use bottom half of word */
73#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
74#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
75#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
76#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
77#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
78#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
79#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
80#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
81#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
82#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
83#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
84#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
85#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
86#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
87#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
88#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
89#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
90#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
91#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
92#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
Benjamin Herrenschmidt5daf9072005-11-18 14:09:41 +1100[diff] [blame]93#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]94
95#ifdef __powerpc64__
96/* Add the 64b processor unique features in the top half of the word */
97#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
98#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
99#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
100#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]101#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
102#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
103#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
104#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
105#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
106#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
107#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100[diff] [blame]108#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]109#else
110/* ensure on 32b processors the flags are available for compiling but
111 * don't do anything */
112#define CPU_FTR_SLB ASM_CONST(0x0)
113#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
114#define CPU_FTR_TLBIEL ASM_CONST(0x0)
115#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]116#define CPU_FTR_IABR ASM_CONST(0x0)
117#define CPU_FTR_MMCRA ASM_CONST(0x0)
118#define CPU_FTR_CTRL ASM_CONST(0x0)
119#define CPU_FTR_SMT ASM_CONST(0x0)
120#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
121#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
122#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100[diff] [blame]123#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]124#endif
125
126#ifndef __ASSEMBLY__
127
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]128#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
129 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
130 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
131
132/* iSeries doesn't support large pages */
133#ifdef CONFIG_PPC_ISERIES
134#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
135#else
136#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
137#endif /* CONFIG_PPC_ISERIES */
138
139/* We only set the altivec features if the kernel was compiled with altivec
140 * support
141 */
142#ifdef CONFIG_ALTIVEC
143#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
144#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
145#else
146#define CPU_FTR_ALTIVEC_COMP 0
147#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
148#endif
149
150/* We need to mark all pages as being coherent if we're SMP or we
151 * have a 74[45]x and an MPC107 host bridge.
152 */
153#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
154#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
155#else
156#define CPU_FTR_COMMON 0
157#endif
158
159/* The powersave features NAP & DOZE seems to confuse BDI when
160 debugging. So if a BDI is used, disable theses
161 */
162#ifndef CONFIG_BDI_SWITCH
163#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
164#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
165#else
166#define CPU_FTR_MAYBE_CAN_DOZE 0
167#define CPU_FTR_MAYBE_CAN_NAP 0
168#endif
169
170#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
171 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
172 !defined(CONFIG_BOOKE))
173
174enum {
175 CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
176 CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
177 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
178 CPU_FTR_MAYBE_CAN_NAP,
179 CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
180 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
181 CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
182 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
183 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
184 CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
185 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
186 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
187 CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
188 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
189 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
190 CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
191 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
192 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
193 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
194 CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
195 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
196 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
197 CPU_FTR_NO_DPM,
198 CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
199 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
200 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
201 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
202 CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
203 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
204 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
205 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
206 CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
207 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
208 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
209 CPU_FTR_MAYBE_CAN_NAP,
210 CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
211 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
212 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
213 CPU_FTR_MAYBE_CAN_NAP,
214 CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
215 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
216 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
217 CPU_FTR_NEED_COHERENT,
218 CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
219 CPU_FTR_USE_TB |
220 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
221 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
222 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
223 CPU_FTR_NEED_COHERENT,
224 CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
225 CPU_FTR_USE_TB |
226 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
227 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
228 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
229 CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
230 CPU_FTR_USE_TB |
231 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
232 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
233 CPU_FTR_NEED_COHERENT,
234 CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
235 CPU_FTR_USE_TB |
236 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
237 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
238 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
239 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
240 CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
241 CPU_FTR_USE_TB |
242 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
243 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
244 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
245 CPU_FTR_NEED_COHERENT,
246 CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
247 CPU_FTR_USE_TB |
248 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
249 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
250 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
251 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
252 CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
253 CPU_FTR_USE_TB |
254 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
255 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
256 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
257 CPU_FTR_NEED_COHERENT,
258 CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
259 CPU_FTR_USE_TB |
260 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
261 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
262 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
263 CPU_FTR_NEED_COHERENT,
264 CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
265 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
266 CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
267 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
268 CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
269 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
270 CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
271 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
272 CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
273 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
274 CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
Benjamin Herrenschmidt5daf9072005-11-18 14:09:41 +1100[diff] [blame]275 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN,
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]276 CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
277 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
Benjamin Herrenschmidt5daf9072005-11-18 14:09:41 +1100[diff] [blame]278 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN,
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]279 CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
Benjamin Herrenschmidt5daf9072005-11-18 14:09:41 +1100[diff] [blame]280 CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
281 CPU_FTR_NODSISRALIGN,
282 CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
283 CPU_FTR_NODSISRALIGN,
284 CPU_FTRS_E200 = CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN,
285 CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
286 CPU_FTR_NODSISRALIGN,
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]287 CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
Benjamin Herrenschmidt5daf9072005-11-18 14:09:41 +1100[diff] [blame]288 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN,
289 CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN,
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]290#ifdef __powerpc64__
291 CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
292 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
293 CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
294 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
295 CPU_FTR_MMCRA | CPU_FTR_CTRL,
296 CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
297 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
298 CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
299 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
300 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
301 CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
302 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
303 CPU_FTR_MMCRA | CPU_FTR_SMT |
304 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
305 CPU_FTR_MMCRA_SIHV,
306 CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
307 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
308 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
309 CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
310 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
311#endif
312
313 CPU_FTRS_POSSIBLE =
314#if CLASSIC_PPC
315 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
316 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
317 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
318 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
319 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
320 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
321 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
322 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
323#else
324 CPU_FTRS_GENERIC_32 |
325#endif
326#ifdef CONFIG_PPC64BRIDGE
327 CPU_FTRS_POWER3_32 |
328#endif
329#ifdef CONFIG_POWER4
330 CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
331#endif
332#ifdef CONFIG_8xx
333 CPU_FTRS_8XX |
334#endif
335#ifdef CONFIG_40x
336 CPU_FTRS_40X |
337#endif
338#ifdef CONFIG_44x
339 CPU_FTRS_44X |
340#endif
341#ifdef CONFIG_E200
342 CPU_FTRS_E200 |
343#endif
344#ifdef CONFIG_E500
345 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
346#endif
347#ifdef __powerpc64__
348 CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
349 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100[diff] [blame]350 CPU_FTR_CI_LARGE_PAGE |
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]351#endif
352 0,
353
354 CPU_FTRS_ALWAYS =
355#if CLASSIC_PPC
356 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
357 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
358 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
359 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
360 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
361 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
362 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
363 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
364#else
365 CPU_FTRS_GENERIC_32 &
366#endif
367#ifdef CONFIG_PPC64BRIDGE
368 CPU_FTRS_POWER3_32 &
369#endif
370#ifdef CONFIG_POWER4
371 CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
372#endif
373#ifdef CONFIG_8xx
374 CPU_FTRS_8XX &
375#endif
376#ifdef CONFIG_40x
377 CPU_FTRS_40X &
378#endif
379#ifdef CONFIG_44x
380 CPU_FTRS_44X &
381#endif
382#ifdef CONFIG_E200
383 CPU_FTRS_E200 &
384#endif
385#ifdef CONFIG_E500
386 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
387#endif
388#ifdef __powerpc64__
389 CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
390 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
391#endif
392 CPU_FTRS_POSSIBLE,
393};
394
395static inline int cpu_has_feature(unsigned long feature)
396{
397 return (CPU_FTRS_ALWAYS & feature) ||
398 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]399 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]400 & feature);
401}
402
403#endif /* !__ASSEMBLY__ */
404
405#ifdef __ASSEMBLY__
406
407#define BEGIN_FTR_SECTION 98:
408
409#ifndef __powerpc64__
410#define END_FTR_SECTION(msk, val) \
41199: \
412 .section __ftr_fixup,"a"; \
413 .align 2; \
414 .long msk; \
415 .long val; \
416 .long 98b; \
417 .long 99b; \
418 .previous
419#else /* __powerpc64__ */
420#define END_FTR_SECTION(msk, val) \
42199: \
422 .section __ftr_fixup,"a"; \
423 .align 3; \
424 .llong msk; \
425 .llong val; \
426 .llong 98b; \
427 .llong 99b; \
428 .previous
429#endif /* __powerpc64__ */
430
431#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
432#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
433#endif /* __ASSEMBLY__ */
434
435#endif /* __KERNEL__ */
436#endif /* __ASM_POWERPC_CPUTABLE_H */