Dave Airlie | f26c473 | 2006-01-02 17:18:39 +1100 | [diff] [blame] | 1 | /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */ |
| 2 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
| 4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 5 | * Copyright 2007 Advanced Micro Devices, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * All Rights Reserved. |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the "Software"), |
| 10 | * to deal in the Software without restriction, including without limitation |
| 11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 12 | * and/or sell copies of the Software, and to permit persons to whom the |
| 13 | * Software is furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the next |
| 16 | * paragraph) shall be included in all copies or substantial portions of the |
| 17 | * Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 25 | * DEALINGS IN THE SOFTWARE. |
| 26 | * |
| 27 | * Authors: |
| 28 | * Kevin E. Martin <martin@valinux.com> |
| 29 | * Gareth Hughes <gareth@valinux.com> |
Christian König | 14adc89 | 2013-01-21 13:58:46 +0100 | [diff] [blame] | 30 | * |
| 31 | * ------------------------ This file is DEPRECATED! ------------------------- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | */ |
| 33 | |
Paul Gortmaker | e0cd360 | 2011-08-30 11:04:30 -0400 | [diff] [blame] | 34 | #include <linux/module.h> |
| 35 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 36 | #include <drm/drmP.h> |
| 37 | #include <drm/radeon_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | #include "radeon_drv.h" |
Dave Airlie | 414ed53 | 2005-08-16 20:43:16 +1000 | [diff] [blame] | 39 | #include "r300_reg.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | |
| 41 | #define RADEON_FIFO_DEBUG 0 |
| 42 | |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 43 | /* Firmware Names */ |
| 44 | #define FIRMWARE_R100 "radeon/R100_cp.bin" |
| 45 | #define FIRMWARE_R200 "radeon/R200_cp.bin" |
| 46 | #define FIRMWARE_R300 "radeon/R300_cp.bin" |
| 47 | #define FIRMWARE_R420 "radeon/R420_cp.bin" |
| 48 | #define FIRMWARE_RS690 "radeon/RS690_cp.bin" |
| 49 | #define FIRMWARE_RS600 "radeon/RS600_cp.bin" |
| 50 | #define FIRMWARE_R520 "radeon/R520_cp.bin" |
| 51 | |
| 52 | MODULE_FIRMWARE(FIRMWARE_R100); |
| 53 | MODULE_FIRMWARE(FIRMWARE_R200); |
| 54 | MODULE_FIRMWARE(FIRMWARE_R300); |
| 55 | MODULE_FIRMWARE(FIRMWARE_R420); |
| 56 | MODULE_FIRMWARE(FIRMWARE_RS690); |
| 57 | MODULE_FIRMWARE(FIRMWARE_RS600); |
| 58 | MODULE_FIRMWARE(FIRMWARE_R520); |
| 59 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 60 | static int radeon_do_cleanup_cp(struct drm_device * dev); |
Jerome Glisse | 54f961a | 2008-08-13 09:46:31 +1000 | [diff] [blame] | 61 | static void radeon_do_cp_start(drm_radeon_private_t * dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 63 | u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off) |
David Miller | b07fa02 | 2009-02-12 02:15:37 -0800 | [diff] [blame] | 64 | { |
| 65 | u32 val; |
| 66 | |
| 67 | if (dev_priv->flags & RADEON_IS_AGP) { |
| 68 | val = DRM_READ32(dev_priv->ring_rptr, off); |
| 69 | } else { |
| 70 | val = *(((volatile u32 *) |
| 71 | dev_priv->ring_rptr->handle) + |
| 72 | (off / sizeof(u32))); |
| 73 | val = le32_to_cpu(val); |
| 74 | } |
| 75 | return val; |
| 76 | } |
| 77 | |
| 78 | u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv) |
| 79 | { |
| 80 | if (dev_priv->writeback_works) |
| 81 | return radeon_read_ring_rptr(dev_priv, 0); |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 82 | else { |
| 83 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 84 | return RADEON_READ(R600_CP_RB_RPTR); |
| 85 | else |
| 86 | return RADEON_READ(RADEON_CP_RB_RPTR); |
| 87 | } |
David Miller | b07fa02 | 2009-02-12 02:15:37 -0800 | [diff] [blame] | 88 | } |
| 89 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 90 | void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val) |
David Miller | b07fa02 | 2009-02-12 02:15:37 -0800 | [diff] [blame] | 91 | { |
| 92 | if (dev_priv->flags & RADEON_IS_AGP) |
| 93 | DRM_WRITE32(dev_priv->ring_rptr, off, val); |
| 94 | else |
| 95 | *(((volatile u32 *) dev_priv->ring_rptr->handle) + |
| 96 | (off / sizeof(u32))) = cpu_to_le32(val); |
| 97 | } |
| 98 | |
| 99 | void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val) |
| 100 | { |
| 101 | radeon_write_ring_rptr(dev_priv, 0, val); |
| 102 | } |
| 103 | |
| 104 | u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index) |
| 105 | { |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 106 | if (dev_priv->writeback_works) { |
| 107 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 108 | return radeon_read_ring_rptr(dev_priv, |
| 109 | R600_SCRATCHOFF(index)); |
| 110 | else |
| 111 | return radeon_read_ring_rptr(dev_priv, |
| 112 | RADEON_SCRATCHOFF(index)); |
| 113 | } else { |
| 114 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 115 | return RADEON_READ(R600_SCRATCH_REG0 + 4*index); |
| 116 | else |
| 117 | return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index); |
| 118 | } |
David Miller | b07fa02 | 2009-02-12 02:15:37 -0800 | [diff] [blame] | 119 | } |
| 120 | |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 121 | static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 122 | { |
| 123 | u32 ret; |
| 124 | RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); |
| 125 | ret = RADEON_READ(R520_MC_IND_DATA); |
| 126 | RADEON_WRITE(R520_MC_IND_INDEX, 0); |
| 127 | return ret; |
| 128 | } |
| 129 | |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 130 | static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
| 131 | { |
| 132 | u32 ret; |
| 133 | RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); |
| 134 | ret = RADEON_READ(RS480_NB_MC_DATA); |
| 135 | RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); |
| 136 | return ret; |
| 137 | } |
| 138 | |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 139 | static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
| 140 | { |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 141 | u32 ret; |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 142 | RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 143 | ret = RADEON_READ(RS690_MC_DATA); |
| 144 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); |
| 145 | return ret; |
| 146 | } |
| 147 | |
Alex Deucher | c1556f7 | 2009-02-25 16:57:49 -0500 | [diff] [blame] | 148 | static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
| 149 | { |
| 150 | u32 ret; |
| 151 | RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | |
| 152 | RS600_MC_IND_CITF_ARB0)); |
| 153 | ret = RADEON_READ(RS600_MC_DATA); |
| 154 | return ret; |
| 155 | } |
| 156 | |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 157 | static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
| 158 | { |
Alex Deucher | f0738e9 | 2008-10-16 17:12:02 +1000 | [diff] [blame] | 159 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
| 160 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 161 | return RS690_READ_MCIND(dev_priv, addr); |
Alex Deucher | c1556f7 | 2009-02-25 16:57:49 -0500 | [diff] [blame] | 162 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) |
| 163 | return RS600_READ_MCIND(dev_priv, addr); |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 164 | else |
| 165 | return RS480_READ_MCIND(dev_priv, addr); |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 166 | } |
| 167 | |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 168 | u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) |
| 169 | { |
| 170 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 171 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) |
| 172 | return RADEON_READ(R700_MC_VM_FB_LOCATION); |
| 173 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 174 | return RADEON_READ(R600_MC_VM_FB_LOCATION); |
| 175 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 176 | return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); |
Alex Deucher | f0738e9 | 2008-10-16 17:12:02 +1000 | [diff] [blame] | 177 | else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
| 178 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 179 | return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); |
Alex Deucher | c1556f7 | 2009-02-25 16:57:49 -0500 | [diff] [blame] | 180 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) |
| 181 | return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION); |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 182 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 183 | return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 184 | else |
| 185 | return RADEON_READ(RADEON_MC_FB_LOCATION); |
| 186 | } |
| 187 | |
| 188 | static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) |
| 189 | { |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 190 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) |
| 191 | RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc); |
| 192 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 193 | RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc); |
| 194 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 195 | R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); |
Alex Deucher | f0738e9 | 2008-10-16 17:12:02 +1000 | [diff] [blame] | 196 | else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
| 197 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 198 | RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); |
Alex Deucher | c1556f7 | 2009-02-25 16:57:49 -0500 | [diff] [blame] | 199 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) |
| 200 | RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc); |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 201 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 202 | R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 203 | else |
| 204 | RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); |
| 205 | } |
| 206 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 207 | void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 208 | { |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 209 | /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */ |
| 210 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { |
| 211 | RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */ |
| 212 | RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff); |
| 213 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { |
| 214 | RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */ |
| 215 | RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff); |
| 216 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 217 | R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); |
Alex Deucher | f0738e9 | 2008-10-16 17:12:02 +1000 | [diff] [blame] | 218 | else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
| 219 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 220 | RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); |
Alex Deucher | c1556f7 | 2009-02-25 16:57:49 -0500 | [diff] [blame] | 221 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) |
| 222 | RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc); |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 223 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 224 | R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 225 | else |
| 226 | RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); |
| 227 | } |
| 228 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 229 | void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) |
Dave Airlie | 70b13d5 | 2008-06-19 11:40:44 +1000 | [diff] [blame] | 230 | { |
| 231 | u32 agp_base_hi = upper_32_bits(agp_base); |
| 232 | u32 agp_base_lo = agp_base & 0xffffffff; |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 233 | u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff; |
Dave Airlie | 70b13d5 | 2008-06-19 11:40:44 +1000 | [diff] [blame] | 234 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 235 | /* R6xx/R7xx must be aligned to a 4MB boundary */ |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 236 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) |
| 237 | RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base); |
| 238 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 239 | RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base); |
| 240 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { |
Dave Airlie | 70b13d5 | 2008-06-19 11:40:44 +1000 | [diff] [blame] | 241 | R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo); |
| 242 | R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi); |
Alex Deucher | f0738e9 | 2008-10-16 17:12:02 +1000 | [diff] [blame] | 243 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
| 244 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { |
Dave Airlie | 70b13d5 | 2008-06-19 11:40:44 +1000 | [diff] [blame] | 245 | RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); |
| 246 | RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); |
Alex Deucher | c1556f7 | 2009-02-25 16:57:49 -0500 | [diff] [blame] | 247 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { |
| 248 | RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo); |
| 249 | RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi); |
Dave Airlie | 70b13d5 | 2008-06-19 11:40:44 +1000 | [diff] [blame] | 250 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { |
| 251 | R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); |
| 252 | R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); |
Alex Deucher | b2ceddf | 2008-10-17 09:19:33 +1000 | [diff] [blame] | 253 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || |
| 254 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { |
Alex Deucher | 5cfb695 | 2008-06-19 12:38:29 +1000 | [diff] [blame] | 255 | RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); |
Alex Deucher | b2ceddf | 2008-10-17 09:19:33 +1000 | [diff] [blame] | 256 | RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi); |
Dave Airlie | 70b13d5 | 2008-06-19 11:40:44 +1000 | [diff] [blame] | 257 | } else { |
| 258 | RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); |
| 259 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) |
| 260 | RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi); |
| 261 | } |
| 262 | } |
| 263 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 264 | void radeon_enable_bm(struct drm_radeon_private *dev_priv) |
Dave Airlie | dd8d7cb | 2009-02-20 13:28:59 +1000 | [diff] [blame] | 265 | { |
| 266 | u32 tmp; |
| 267 | /* Turn on bus mastering */ |
| 268 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
| 269 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { |
| 270 | /* rs600/rs690/rs740 */ |
| 271 | tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
| 272 | RADEON_WRITE(RADEON_BUS_CNTL, tmp); |
| 273 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) || |
| 274 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || |
| 275 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || |
| 276 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { |
| 277 | /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
| 278 | tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
| 279 | RADEON_WRITE(RADEON_BUS_CNTL, tmp); |
| 280 | } /* PCIE cards appears to not need this */ |
| 281 | } |
| 282 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 283 | static int RADEON_READ_PLL(struct drm_device * dev, int addr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 284 | { |
| 285 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 286 | |
| 287 | RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); |
| 288 | return RADEON_READ(RADEON_CLOCK_CNTL_DATA); |
| 289 | } |
| 290 | |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 291 | static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 292 | { |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 293 | RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); |
| 294 | return RADEON_READ(RADEON_PCIE_DATA); |
| 295 | } |
| 296 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 297 | #if RADEON_FIFO_DEBUG |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 298 | static void radeon_status(drm_radeon_private_t * dev_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | { |
Harvey Harrison | bf9d892 | 2008-04-30 00:55:10 -0700 | [diff] [blame] | 300 | printk("%s:\n", __func__); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 301 | printk("RBBM_STATUS = 0x%08x\n", |
| 302 | (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); |
| 303 | printk("CP_RB_RTPR = 0x%08x\n", |
| 304 | (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); |
| 305 | printk("CP_RB_WTPR = 0x%08x\n", |
| 306 | (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); |
| 307 | printk("AIC_CNTL = 0x%08x\n", |
| 308 | (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); |
| 309 | printk("AIC_STAT = 0x%08x\n", |
| 310 | (unsigned int)RADEON_READ(RADEON_AIC_STAT)); |
| 311 | printk("AIC_PT_BASE = 0x%08x\n", |
| 312 | (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); |
| 313 | printk("TLB_ADDR = 0x%08x\n", |
| 314 | (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); |
| 315 | printk("TLB_DATA = 0x%08x\n", |
| 316 | (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 317 | } |
| 318 | #endif |
| 319 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 320 | /* ================================================================ |
| 321 | * Engine, FIFO control |
| 322 | */ |
| 323 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 324 | static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 325 | { |
| 326 | u32 tmp; |
| 327 | int i; |
| 328 | |
| 329 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
| 330 | |
Alex Deucher | 259434a | 2008-05-28 11:51:12 +1000 | [diff] [blame] | 331 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { |
| 332 | tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); |
| 333 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; |
| 334 | RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 335 | |
Alex Deucher | 259434a | 2008-05-28 11:51:12 +1000 | [diff] [blame] | 336 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
| 337 | if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) |
| 338 | & RADEON_RB3D_DC_BUSY)) { |
| 339 | return 0; |
| 340 | } |
| 341 | DRM_UDELAY(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 342 | } |
Alex Deucher | 259434a | 2008-05-28 11:51:12 +1000 | [diff] [blame] | 343 | } else { |
Jerome Glisse | 54f961a | 2008-08-13 09:46:31 +1000 | [diff] [blame] | 344 | /* don't flush or purge cache here or lockup */ |
| 345 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | #if RADEON_FIFO_DEBUG |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 349 | DRM_ERROR("failed!\n"); |
| 350 | radeon_status(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | #endif |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 352 | return -EBUSY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | } |
| 354 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 355 | static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | { |
| 357 | int i; |
| 358 | |
| 359 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
| 360 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 361 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
| 362 | int slots = (RADEON_READ(RADEON_RBBM_STATUS) |
| 363 | & RADEON_RBBM_FIFOCNT_MASK); |
| 364 | if (slots >= entries) |
| 365 | return 0; |
| 366 | DRM_UDELAY(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | } |
Dave Airlie | 6c7be29 | 2008-09-01 08:51:52 +1000 | [diff] [blame] | 368 | DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n", |
Jerome Glisse | 54f961a | 2008-08-13 09:46:31 +1000 | [diff] [blame] | 369 | RADEON_READ(RADEON_RBBM_STATUS), |
| 370 | RADEON_READ(R300_VAP_CNTL_STATUS)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 371 | |
| 372 | #if RADEON_FIFO_DEBUG |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 373 | DRM_ERROR("failed!\n"); |
| 374 | radeon_status(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 375 | #endif |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 376 | return -EBUSY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 377 | } |
| 378 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 379 | static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 380 | { |
| 381 | int i, ret; |
| 382 | |
| 383 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
| 384 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 385 | ret = radeon_do_wait_for_fifo(dev_priv, 64); |
| 386 | if (ret) |
| 387 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 388 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 389 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
| 390 | if (!(RADEON_READ(RADEON_RBBM_STATUS) |
| 391 | & RADEON_RBBM_ACTIVE)) { |
| 392 | radeon_do_pixcache_flush(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 393 | return 0; |
| 394 | } |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 395 | DRM_UDELAY(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 396 | } |
Dave Airlie | 6c7be29 | 2008-09-01 08:51:52 +1000 | [diff] [blame] | 397 | DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n", |
Jerome Glisse | 54f961a | 2008-08-13 09:46:31 +1000 | [diff] [blame] | 398 | RADEON_READ(RADEON_RBBM_STATUS), |
| 399 | RADEON_READ(R300_VAP_CNTL_STATUS)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 400 | |
| 401 | #if RADEON_FIFO_DEBUG |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 402 | DRM_ERROR("failed!\n"); |
| 403 | radeon_status(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 404 | #endif |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 405 | return -EBUSY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 406 | } |
| 407 | |
Michel Dänzer | 57b54ea | 2010-04-02 16:59:06 +0000 | [diff] [blame] | 408 | static void radeon_init_pipes(struct drm_device *dev) |
Alex Deucher | 5b92c40 | 2008-05-28 11:57:40 +1000 | [diff] [blame] | 409 | { |
Michel Dänzer | 57b54ea | 2010-04-02 16:59:06 +0000 | [diff] [blame] | 410 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Alex Deucher | 5b92c40 | 2008-05-28 11:57:40 +1000 | [diff] [blame] | 411 | uint32_t gb_tile_config, gb_pipe_sel = 0; |
| 412 | |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 413 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) { |
| 414 | uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2); |
| 415 | if ((z_pipe_sel & 3) == 3) |
| 416 | dev_priv->num_z_pipes = 2; |
| 417 | else |
| 418 | dev_priv->num_z_pipes = 1; |
| 419 | } else |
| 420 | dev_priv->num_z_pipes = 1; |
| 421 | |
Alex Deucher | 5b92c40 | 2008-05-28 11:57:40 +1000 | [diff] [blame] | 422 | /* RS4xx/RS6xx/R4xx/R5xx */ |
| 423 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { |
| 424 | gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); |
| 425 | dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
Tormod Volden | 94f7bf6 | 2010-04-22 16:57:32 -0400 | [diff] [blame] | 426 | /* SE cards have 1 pipe */ |
| 427 | if ((dev->pdev->device == 0x5e4c) || |
| 428 | (dev->pdev->device == 0x5e4f)) |
| 429 | dev_priv->num_gb_pipes = 1; |
Alex Deucher | 5b92c40 | 2008-05-28 11:57:40 +1000 | [diff] [blame] | 430 | } else { |
| 431 | /* R3xx */ |
Michel Dänzer | 57b54ea | 2010-04-02 16:59:06 +0000 | [diff] [blame] | 432 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 && |
| 433 | dev->pdev->device != 0x4144) || |
Tormod Volden | 94f7bf6 | 2010-04-22 16:57:32 -0400 | [diff] [blame] | 434 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 && |
| 435 | dev->pdev->device != 0x4148)) { |
Alex Deucher | 5b92c40 | 2008-05-28 11:57:40 +1000 | [diff] [blame] | 436 | dev_priv->num_gb_pipes = 2; |
| 437 | } else { |
Tormod Volden | 94f7bf6 | 2010-04-22 16:57:32 -0400 | [diff] [blame] | 438 | /* RV3xx/R300 AD/R350 AH */ |
Alex Deucher | 5b92c40 | 2008-05-28 11:57:40 +1000 | [diff] [blame] | 439 | dev_priv->num_gb_pipes = 1; |
| 440 | } |
| 441 | } |
| 442 | DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); |
| 443 | |
| 444 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); |
| 445 | |
| 446 | switch (dev_priv->num_gb_pipes) { |
| 447 | case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
| 448 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
| 449 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
| 450 | default: |
| 451 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
| 452 | } |
| 453 | |
| 454 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { |
| 455 | RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
Maciej Cencora | af7ae35 | 2009-03-24 01:48:50 +0100 | [diff] [blame] | 456 | RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); |
Alex Deucher | 5b92c40 | 2008-05-28 11:57:40 +1000 | [diff] [blame] | 457 | } |
| 458 | RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); |
| 459 | radeon_do_wait_for_idle(dev_priv); |
| 460 | RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); |
| 461 | RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) | |
| 462 | R300_DC_AUTOFLUSH_ENABLE | |
| 463 | R300_DC_DC_DISABLE_IGNORE_PE)); |
| 464 | |
| 465 | |
| 466 | } |
| 467 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 468 | /* ================================================================ |
| 469 | * CP control, initialization |
| 470 | */ |
| 471 | |
| 472 | /* Load the microcode for the CP */ |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 473 | static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 474 | { |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 475 | struct platform_device *pdev; |
| 476 | const char *fw_name = NULL; |
| 477 | int err; |
| 478 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 479 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 480 | |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 481 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
| 482 | err = IS_ERR(pdev); |
| 483 | if (err) { |
| 484 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
| 485 | return -EINVAL; |
| 486 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | |
Alex Deucher | 9f18409 | 2008-05-28 11:21:25 +1000 | [diff] [blame] | 488 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || |
| 489 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || |
| 490 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || |
| 491 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || |
| 492 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { |
| 493 | DRM_INFO("Loading R100 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 494 | fw_name = FIRMWARE_R100; |
Alex Deucher | 9f18409 | 2008-05-28 11:21:25 +1000 | [diff] [blame] | 495 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || |
| 496 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || |
| 497 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || |
| 498 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 499 | DRM_INFO("Loading R200 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 500 | fw_name = FIRMWARE_R200; |
Alex Deucher | 9f18409 | 2008-05-28 11:21:25 +1000 | [diff] [blame] | 501 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || |
| 502 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || |
| 503 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || |
| 504 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || |
Alex Deucher | b2ceddf | 2008-10-17 09:19:33 +1000 | [diff] [blame] | 505 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 506 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 507 | DRM_INFO("Loading R300 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 508 | fw_name = FIRMWARE_R300; |
Alex Deucher | 9f18409 | 2008-05-28 11:21:25 +1000 | [diff] [blame] | 509 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || |
Alex Deucher | edc6f38 | 2008-10-17 09:21:45 +1000 | [diff] [blame] | 510 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) || |
Alex Deucher | 9f18409 | 2008-05-28 11:21:25 +1000 | [diff] [blame] | 511 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { |
| 512 | DRM_INFO("Loading R400 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 513 | fw_name = FIRMWARE_R420; |
Alex Deucher | f0738e9 | 2008-10-16 17:12:02 +1000 | [diff] [blame] | 514 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
| 515 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { |
| 516 | DRM_INFO("Loading RS690/RS740 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 517 | fw_name = FIRMWARE_RS690; |
Alex Deucher | c1556f7 | 2009-02-25 16:57:49 -0500 | [diff] [blame] | 518 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { |
| 519 | DRM_INFO("Loading RS600 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 520 | fw_name = FIRMWARE_RS600; |
Alex Deucher | 9f18409 | 2008-05-28 11:21:25 +1000 | [diff] [blame] | 521 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || |
| 522 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || |
| 523 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || |
| 524 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) || |
| 525 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || |
| 526 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { |
| 527 | DRM_INFO("Loading R500 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 528 | fw_name = FIRMWARE_R520; |
| 529 | } |
| 530 | |
| 531 | err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); |
| 532 | platform_device_unregister(pdev); |
| 533 | if (err) { |
| 534 | printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", |
| 535 | fw_name); |
| 536 | } else if (dev_priv->me_fw->size % 8) { |
| 537 | printk(KERN_ERR |
| 538 | "radeon_cp: Bogus length %zu in firmware \"%s\"\n", |
| 539 | dev_priv->me_fw->size, fw_name); |
| 540 | err = -EINVAL; |
| 541 | release_firmware(dev_priv->me_fw); |
| 542 | dev_priv->me_fw = NULL; |
| 543 | } |
| 544 | return err; |
| 545 | } |
| 546 | |
| 547 | static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv) |
| 548 | { |
| 549 | const __be32 *fw_data; |
| 550 | int i, size; |
| 551 | |
| 552 | radeon_do_wait_for_idle(dev_priv); |
| 553 | |
| 554 | if (dev_priv->me_fw) { |
| 555 | size = dev_priv->me_fw->size / 4; |
| 556 | fw_data = (const __be32 *)&dev_priv->me_fw->data[0]; |
| 557 | RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); |
| 558 | for (i = 0; i < size; i += 2) { |
Alex Deucher | 9f18409 | 2008-05-28 11:21:25 +1000 | [diff] [blame] | 559 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 560 | be32_to_cpup(&fw_data[i])); |
Alex Deucher | 9f18409 | 2008-05-28 11:21:25 +1000 | [diff] [blame] | 561 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 562 | be32_to_cpup(&fw_data[i + 1])); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 563 | } |
| 564 | } |
| 565 | } |
| 566 | |
| 567 | /* Flush any pending commands to the CP. This should only be used just |
| 568 | * prior to a wait for idle, as it informs the engine that the command |
| 569 | * stream is ending. |
| 570 | */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 571 | static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 572 | { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 573 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 574 | #if 0 |
| 575 | u32 tmp; |
| 576 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 577 | tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); |
| 578 | RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 579 | #endif |
| 580 | } |
| 581 | |
| 582 | /* Wait for the CP to go idle. |
| 583 | */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 584 | int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 585 | { |
| 586 | RING_LOCALS; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 587 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 588 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 589 | BEGIN_RING(6); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 590 | |
| 591 | RADEON_PURGE_CACHE(); |
| 592 | RADEON_PURGE_ZCACHE(); |
| 593 | RADEON_WAIT_UNTIL_IDLE(); |
| 594 | |
| 595 | ADVANCE_RING(); |
| 596 | COMMIT_RING(); |
| 597 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 598 | return radeon_do_wait_for_idle(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | } |
| 600 | |
| 601 | /* Start the Command Processor. |
| 602 | */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 603 | static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 604 | { |
| 605 | RING_LOCALS; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 606 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 607 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 608 | radeon_do_wait_for_idle(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 609 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 610 | RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 611 | |
| 612 | dev_priv->cp_running = 1; |
| 613 | |
Alex Deucher | aadd4e1 | 2009-09-21 14:48:45 +1000 | [diff] [blame] | 614 | /* on r420, any DMA from CP to system memory while 2D is active |
| 615 | * can cause a hang. workaround is to queue a CP RESYNC token |
| 616 | */ |
| 617 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) { |
| 618 | BEGIN_RING(3); |
| 619 | OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1)); |
| 620 | OUT_RING(5); /* scratch reg 5 */ |
| 621 | OUT_RING(0xdeadbeef); |
| 622 | ADVANCE_RING(); |
| 623 | COMMIT_RING(); |
| 624 | } |
| 625 | |
Jerome Glisse | 54f961a | 2008-08-13 09:46:31 +1000 | [diff] [blame] | 626 | BEGIN_RING(8); |
| 627 | /* isync can only be written through cp on r5xx write it here */ |
| 628 | OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); |
| 629 | OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | |
| 630 | RADEON_ISYNC_ANY3D_IDLE2D | |
| 631 | RADEON_ISYNC_WAIT_IDLEGUI | |
| 632 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 633 | RADEON_PURGE_CACHE(); |
| 634 | RADEON_PURGE_ZCACHE(); |
| 635 | RADEON_WAIT_UNTIL_IDLE(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 636 | ADVANCE_RING(); |
| 637 | COMMIT_RING(); |
Jerome Glisse | 54f961a | 2008-08-13 09:46:31 +1000 | [diff] [blame] | 638 | |
| 639 | dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 640 | } |
| 641 | |
| 642 | /* Reset the Command Processor. This will not flush any pending |
| 643 | * commands, so you must wait for the CP command stream to complete |
| 644 | * before calling this routine. |
| 645 | */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 646 | static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 647 | { |
| 648 | u32 cur_read_ptr; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 649 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 651 | cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); |
| 652 | RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); |
| 653 | SET_RING_HEAD(dev_priv, cur_read_ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 654 | dev_priv->ring.tail = cur_read_ptr; |
| 655 | } |
| 656 | |
| 657 | /* Stop the Command Processor. This will not flush any pending |
| 658 | * commands, so you must flush the command stream and wait for the CP |
| 659 | * to go idle before calling this routine. |
| 660 | */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 661 | static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 662 | { |
Alex Deucher | aadd4e1 | 2009-09-21 14:48:45 +1000 | [diff] [blame] | 663 | RING_LOCALS; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 664 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 665 | |
Alex Deucher | aadd4e1 | 2009-09-21 14:48:45 +1000 | [diff] [blame] | 666 | /* finish the pending CP_RESYNC token */ |
| 667 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) { |
| 668 | BEGIN_RING(2); |
| 669 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
| 670 | OUT_RING(R300_RB3D_DC_FINISH); |
| 671 | ADVANCE_RING(); |
| 672 | COMMIT_RING(); |
| 673 | radeon_do_wait_for_idle(dev_priv); |
| 674 | } |
| 675 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 676 | RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 677 | |
| 678 | dev_priv->cp_running = 0; |
| 679 | } |
| 680 | |
| 681 | /* Reset the engine. This will stop the CP if it is running. |
| 682 | */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 683 | static int radeon_do_engine_reset(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 684 | { |
| 685 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Alex Deucher | d396db3 | 2008-05-28 11:54:06 +1000 | [diff] [blame] | 686 | u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 687 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 688 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 689 | radeon_do_pixcache_flush(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 690 | |
Alex Deucher | d396db3 | 2008-05-28 11:54:06 +1000 | [diff] [blame] | 691 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { |
| 692 | /* may need something similar for newer chips */ |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 693 | clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); |
| 694 | mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 695 | |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 696 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | |
| 697 | RADEON_FORCEON_MCLKA | |
| 698 | RADEON_FORCEON_MCLKB | |
| 699 | RADEON_FORCEON_YCLKA | |
| 700 | RADEON_FORCEON_YCLKB | |
| 701 | RADEON_FORCEON_MC | |
| 702 | RADEON_FORCEON_AIC)); |
Alex Deucher | d396db3 | 2008-05-28 11:54:06 +1000 | [diff] [blame] | 703 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 704 | |
Alex Deucher | d396db3 | 2008-05-28 11:54:06 +1000 | [diff] [blame] | 705 | rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 706 | |
Alex Deucher | d396db3 | 2008-05-28 11:54:06 +1000 | [diff] [blame] | 707 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | |
| 708 | RADEON_SOFT_RESET_CP | |
| 709 | RADEON_SOFT_RESET_HI | |
| 710 | RADEON_SOFT_RESET_SE | |
| 711 | RADEON_SOFT_RESET_RE | |
| 712 | RADEON_SOFT_RESET_PP | |
| 713 | RADEON_SOFT_RESET_E2 | |
| 714 | RADEON_SOFT_RESET_RB)); |
| 715 | RADEON_READ(RADEON_RBBM_SOFT_RESET); |
| 716 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & |
| 717 | ~(RADEON_SOFT_RESET_CP | |
| 718 | RADEON_SOFT_RESET_HI | |
| 719 | RADEON_SOFT_RESET_SE | |
| 720 | RADEON_SOFT_RESET_RE | |
| 721 | RADEON_SOFT_RESET_PP | |
| 722 | RADEON_SOFT_RESET_E2 | |
| 723 | RADEON_SOFT_RESET_RB))); |
| 724 | RADEON_READ(RADEON_RBBM_SOFT_RESET); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 725 | |
Alex Deucher | d396db3 | 2008-05-28 11:54:06 +1000 | [diff] [blame] | 726 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 727 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); |
| 728 | RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); |
| 729 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); |
| 730 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 731 | |
Alex Deucher | 5b92c40 | 2008-05-28 11:57:40 +1000 | [diff] [blame] | 732 | /* setup the raster pipes */ |
| 733 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) |
Michel Dänzer | 57b54ea | 2010-04-02 16:59:06 +0000 | [diff] [blame] | 734 | radeon_init_pipes(dev); |
Alex Deucher | 5b92c40 | 2008-05-28 11:57:40 +1000 | [diff] [blame] | 735 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 736 | /* Reset the CP ring */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 737 | radeon_do_cp_reset(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 738 | |
| 739 | /* The CP is no longer running after an engine reset */ |
| 740 | dev_priv->cp_running = 0; |
| 741 | |
| 742 | /* Reset any pending vertex, indirect buffers */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 743 | radeon_freelist_reset(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 744 | |
| 745 | return 0; |
| 746 | } |
| 747 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 748 | static void radeon_cp_init_ring_buffer(struct drm_device * dev, |
etienne | 3d16118 | 2009-02-20 09:44:45 +1000 | [diff] [blame] | 749 | drm_radeon_private_t *dev_priv, |
| 750 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 751 | { |
etienne | 3d16118 | 2009-02-20 09:44:45 +1000 | [diff] [blame] | 752 | struct drm_radeon_master_private *master_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 753 | u32 ring_start, cur_read_ptr; |
Dave Airlie | bc5f452 | 2007-11-05 12:50:58 +1000 | [diff] [blame] | 754 | |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 755 | /* Initialize the memory controller. With new memory map, the fb location |
| 756 | * is not changed, it should have been properly initialized already. Part |
| 757 | * of the problem is that the code below is bogus, assuming the GART is |
| 758 | * always appended to the fb which is not necessarily the case |
| 759 | */ |
| 760 | if (!dev_priv->new_memmap) |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 761 | radeon_write_fb_location(dev_priv, |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 762 | ((dev_priv->gart_vm_start - 1) & 0xffff0000) |
| 763 | | (dev_priv->fb_location >> 16)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 764 | |
| 765 | #if __OS_HAS_AGP |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 766 | if (dev_priv->flags & RADEON_IS_AGP) { |
Dave Airlie | 70b13d5 | 2008-06-19 11:40:44 +1000 | [diff] [blame] | 767 | radeon_write_agp_base(dev_priv, dev->agp->base); |
| 768 | |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 769 | radeon_write_agp_location(dev_priv, |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 770 | (((dev_priv->gart_vm_start - 1 + |
| 771 | dev_priv->gart_size) & 0xffff0000) | |
| 772 | (dev_priv->gart_vm_start >> 16))); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 773 | |
| 774 | ring_start = (dev_priv->cp_ring->offset |
| 775 | - dev->agp->base |
| 776 | + dev_priv->gart_vm_start); |
Ivan Kokshaysky | b0917bd | 2005-10-26 11:05:25 +0100 | [diff] [blame] | 777 | } else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 778 | #endif |
| 779 | ring_start = (dev_priv->cp_ring->offset |
Ivan Kokshaysky | b0917bd | 2005-10-26 11:05:25 +0100 | [diff] [blame] | 780 | - (unsigned long)dev->sg->virtual |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 781 | + dev_priv->gart_vm_start); |
| 782 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 783 | RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 784 | |
| 785 | /* Set the write pointer delay */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 786 | RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 787 | |
| 788 | /* Initialize the ring buffer's read and write pointers */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 789 | cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); |
| 790 | RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); |
| 791 | SET_RING_HEAD(dev_priv, cur_read_ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 792 | dev_priv->ring.tail = cur_read_ptr; |
| 793 | |
| 794 | #if __OS_HAS_AGP |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 795 | if (dev_priv->flags & RADEON_IS_AGP) { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 796 | RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, |
| 797 | dev_priv->ring_rptr->offset |
| 798 | - dev->agp->base + dev_priv->gart_vm_start); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 799 | } else |
| 800 | #endif |
| 801 | { |
David Miller | e8a8943 | 2009-02-12 02:15:44 -0800 | [diff] [blame] | 802 | RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, |
| 803 | dev_priv->ring_rptr->offset |
| 804 | - ((unsigned long) dev->sg->virtual) |
| 805 | + dev_priv->gart_vm_start); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 806 | } |
| 807 | |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 808 | /* Set ring buffer size */ |
| 809 | #ifdef __BIG_ENDIAN |
| 810 | RADEON_WRITE(RADEON_CP_RB_CNTL, |
Roland Scheidegger | 576cc45 | 2008-02-07 14:59:24 +1000 | [diff] [blame] | 811 | RADEON_BUF_SWAP_32BIT | |
| 812 | (dev_priv->ring.fetch_size_l2ow << 18) | |
| 813 | (dev_priv->ring.rptr_update_l2qw << 8) | |
| 814 | dev_priv->ring.size_l2qw); |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 815 | #else |
Roland Scheidegger | 576cc45 | 2008-02-07 14:59:24 +1000 | [diff] [blame] | 816 | RADEON_WRITE(RADEON_CP_RB_CNTL, |
| 817 | (dev_priv->ring.fetch_size_l2ow << 18) | |
| 818 | (dev_priv->ring.rptr_update_l2qw << 8) | |
| 819 | dev_priv->ring.size_l2qw); |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 820 | #endif |
| 821 | |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 822 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 823 | /* Initialize the scratch register pointer. This will cause |
| 824 | * the scratch register values to be written out to memory |
| 825 | * whenever they are updated. |
| 826 | * |
| 827 | * We simply put this behind the ring read pointer, this works |
| 828 | * with PCI GART as well as (whatever kind of) AGP GART |
| 829 | */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 830 | RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) |
| 831 | + RADEON_SCRATCH_REG_OFFSET); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 832 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 833 | RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 834 | |
Dave Airlie | dd8d7cb | 2009-02-20 13:28:59 +1000 | [diff] [blame] | 835 | radeon_enable_bm(dev_priv); |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 836 | |
David Miller | b07fa02 | 2009-02-12 02:15:37 -0800 | [diff] [blame] | 837 | radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 838 | RADEON_WRITE(RADEON_LAST_FRAME_REG, 0); |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 839 | |
David Miller | b07fa02 | 2009-02-12 02:15:37 -0800 | [diff] [blame] | 840 | radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 841 | RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0); |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 842 | |
David Miller | b07fa02 | 2009-02-12 02:15:37 -0800 | [diff] [blame] | 843 | radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 844 | RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0); |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 845 | |
etienne | 3d16118 | 2009-02-20 09:44:45 +1000 | [diff] [blame] | 846 | /* reset sarea copies of these */ |
| 847 | master_priv = file_priv->master->driver_priv; |
| 848 | if (master_priv->sarea_priv) { |
| 849 | master_priv->sarea_priv->last_frame = 0; |
| 850 | master_priv->sarea_priv->last_dispatch = 0; |
| 851 | master_priv->sarea_priv->last_clear = 0; |
| 852 | } |
| 853 | |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 854 | radeon_do_wait_for_idle(dev_priv); |
| 855 | |
| 856 | /* Sync everything up */ |
| 857 | RADEON_WRITE(RADEON_ISYNC_CNTL, |
| 858 | (RADEON_ISYNC_ANY2D_IDLE3D | |
| 859 | RADEON_ISYNC_ANY3D_IDLE2D | |
| 860 | RADEON_ISYNC_WAIT_IDLEGUI | |
| 861 | RADEON_ISYNC_CPSCRATCH_IDLEGUI)); |
| 862 | |
| 863 | } |
| 864 | |
| 865 | static void radeon_test_writeback(drm_radeon_private_t * dev_priv) |
| 866 | { |
| 867 | u32 tmp; |
| 868 | |
Dave Airlie | 6b79d52 | 2008-09-02 10:10:16 +1000 | [diff] [blame] | 869 | /* Start with assuming that writeback doesn't work */ |
| 870 | dev_priv->writeback_works = 0; |
| 871 | |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 872 | /* Writeback doesn't seem to work everywhere, test it here and possibly |
| 873 | * enable it if it appears to work |
| 874 | */ |
David Miller | b07fa02 | 2009-02-12 02:15:37 -0800 | [diff] [blame] | 875 | radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0); |
| 876 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 877 | RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 878 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 879 | for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { |
David Miller | b07fa02 | 2009-02-12 02:15:37 -0800 | [diff] [blame] | 880 | u32 val; |
| 881 | |
| 882 | val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1)); |
| 883 | if (val == 0xdeadbeef) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 884 | break; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 885 | DRM_UDELAY(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 886 | } |
| 887 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 888 | if (tmp < dev_priv->usec_timeout) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 889 | dev_priv->writeback_works = 1; |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 890 | DRM_INFO("writeback test succeeded in %d usecs\n", tmp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 891 | } else { |
| 892 | dev_priv->writeback_works = 0; |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 893 | DRM_INFO("writeback test failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 894 | } |
Dave Airlie | 689b9d7 | 2005-09-30 17:09:07 +1000 | [diff] [blame] | 895 | if (radeon_no_wb == 1) { |
| 896 | dev_priv->writeback_works = 0; |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 897 | DRM_INFO("writeback forced off\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 898 | } |
Michel Dänzer | ae1b1a48 | 2006-08-07 20:37:46 +1000 | [diff] [blame] | 899 | |
| 900 | if (!dev_priv->writeback_works) { |
| 901 | /* Disable writeback to avoid unnecessary bus master transfer */ |
| 902 | RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | |
| 903 | RADEON_RB_NO_UPDATE); |
| 904 | RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); |
| 905 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 906 | } |
| 907 | |
Dave Airlie | f2b04cd | 2007-05-08 15:19:23 +1000 | [diff] [blame] | 908 | /* Enable or disable IGP GART on the chip */ |
| 909 | static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) |
| 910 | { |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 911 | u32 temp; |
| 912 | |
| 913 | if (on) { |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 914 | DRM_DEBUG("programming igp gart %08X %08lX %08X\n", |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 915 | dev_priv->gart_vm_start, |
| 916 | (long)dev_priv->gart_info.bus_addr, |
| 917 | dev_priv->gart_size); |
| 918 | |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 919 | temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); |
Alex Deucher | f0738e9 | 2008-10-16 17:12:02 +1000 | [diff] [blame] | 920 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
| 921 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 922 | IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | |
| 923 | RS690_BLOCK_GFX_D3_EN)); |
| 924 | else |
| 925 | IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 926 | |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 927 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | |
| 928 | RS480_VA_SIZE_32MB)); |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 929 | |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 930 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); |
| 931 | IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | |
| 932 | RS480_TLB_ENABLE | |
| 933 | RS480_GTW_LAC_EN | |
| 934 | RS480_1LEVEL_GART)); |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 935 | |
Dave Airlie | fa0d71b | 2008-05-28 11:27:01 +1000 | [diff] [blame] | 936 | temp = dev_priv->gart_info.bus_addr & 0xfffff000; |
| 937 | temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 938 | IGP_WRITE_MCIND(RS480_GART_BASE, temp); |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 939 | |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 940 | temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); |
| 941 | IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | |
| 942 | RS480_REQ_TYPE_SNOOP_DIS)); |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 943 | |
Alex Deucher | 5cfb695 | 2008-06-19 12:38:29 +1000 | [diff] [blame] | 944 | radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); |
Dave Airlie | 3722bfc | 2008-05-28 11:28:27 +1000 | [diff] [blame] | 945 | |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 946 | dev_priv->gart_size = 32*1024*1024; |
| 947 | temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & |
| 948 | 0xffff0000) | (dev_priv->gart_vm_start >> 16)); |
| 949 | |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 950 | radeon_write_agp_location(dev_priv, temp); |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 951 | |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 952 | temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); |
| 953 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | |
| 954 | RS480_VA_SIZE_32MB)); |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 955 | |
| 956 | do { |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 957 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); |
| 958 | if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 959 | break; |
| 960 | DRM_UDELAY(1); |
| 961 | } while (1); |
| 962 | |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 963 | IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, |
| 964 | RS480_GART_CACHE_INVALIDATE); |
Alex Deucher | 2735977 | 2008-05-28 12:54:16 +1000 | [diff] [blame] | 965 | |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 966 | do { |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 967 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); |
| 968 | if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 969 | break; |
| 970 | DRM_UDELAY(1); |
| 971 | } while (1); |
| 972 | |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 973 | IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 974 | } else { |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 975 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); |
Maciej Cencora | 60f9268 | 2008-02-19 21:32:45 +1000 | [diff] [blame] | 976 | } |
| 977 | } |
| 978 | |
Alex Deucher | c1556f7 | 2009-02-25 16:57:49 -0500 | [diff] [blame] | 979 | /* Enable or disable IGP GART on the chip */ |
| 980 | static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on) |
| 981 | { |
| 982 | u32 temp; |
| 983 | int i; |
| 984 | |
| 985 | if (on) { |
| 986 | DRM_DEBUG("programming igp gart %08X %08lX %08X\n", |
| 987 | dev_priv->gart_vm_start, |
| 988 | (long)dev_priv->gart_info.bus_addr, |
| 989 | dev_priv->gart_size); |
| 990 | |
| 991 | IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | |
| 992 | RS600_EFFECTIVE_L2_QUEUE_SIZE(6))); |
| 993 | |
| 994 | for (i = 0; i < 19; i++) |
| 995 | IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i, |
| 996 | (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE | |
| 997 | RS600_SYSTEM_ACCESS_MODE_IN_SYS | |
| 998 | RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH | |
| 999 | RS600_EFFECTIVE_L1_CACHE_SIZE(3) | |
| 1000 | RS600_ENABLE_FRAGMENT_PROCESSING | |
| 1001 | RS600_EFFECTIVE_L1_QUEUE_SIZE(3))); |
| 1002 | |
| 1003 | IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE | |
| 1004 | RS600_PAGE_TABLE_TYPE_FLAT)); |
| 1005 | |
| 1006 | /* disable all other contexts */ |
| 1007 | for (i = 1; i < 8; i++) |
| 1008 | IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0); |
| 1009 | |
| 1010 | /* setup the page table aperture */ |
| 1011 | IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
| 1012 | dev_priv->gart_info.bus_addr); |
| 1013 | IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, |
| 1014 | dev_priv->gart_vm_start); |
| 1015 | IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, |
| 1016 | (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); |
| 1017 | IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
| 1018 | |
| 1019 | /* setup the system aperture */ |
| 1020 | IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, |
| 1021 | dev_priv->gart_vm_start); |
| 1022 | IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, |
| 1023 | (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); |
| 1024 | |
| 1025 | /* enable page tables */ |
| 1026 | temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); |
| 1027 | IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT)); |
| 1028 | |
| 1029 | temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); |
| 1030 | IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES)); |
| 1031 | |
| 1032 | /* invalidate the cache */ |
| 1033 | temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); |
| 1034 | |
| 1035 | temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); |
| 1036 | IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); |
| 1037 | temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); |
| 1038 | |
| 1039 | temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE; |
| 1040 | IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); |
| 1041 | temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); |
| 1042 | |
| 1043 | temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); |
| 1044 | IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); |
| 1045 | temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); |
| 1046 | |
| 1047 | } else { |
| 1048 | IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0); |
| 1049 | temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); |
| 1050 | temp &= ~RS600_ENABLE_PAGE_TABLES; |
| 1051 | IGP_WRITE_MCIND(RS600_MC_CNTL1, temp); |
| 1052 | } |
| 1053 | } |
| 1054 | |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 1055 | static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1056 | { |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 1057 | u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); |
| 1058 | if (on) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1059 | |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 1060 | DRM_DEBUG("programming pcie %08X %08lX %08X\n", |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1061 | dev_priv->gart_vm_start, |
| 1062 | (long)dev_priv->gart_info.bus_addr, |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 1063 | dev_priv->gart_size); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1064 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, |
| 1065 | dev_priv->gart_vm_start); |
| 1066 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, |
| 1067 | dev_priv->gart_info.bus_addr); |
| 1068 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, |
| 1069 | dev_priv->gart_vm_start); |
| 1070 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, |
| 1071 | dev_priv->gart_vm_start + |
| 1072 | dev_priv->gart_size - 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1073 | |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 1074 | radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1075 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1076 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
| 1077 | RADEON_PCIE_TX_GART_EN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1078 | } else { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1079 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
| 1080 | tmp & ~RADEON_PCIE_TX_GART_EN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1081 | } |
| 1082 | } |
| 1083 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1084 | /* Enable or disable PCI GART on the chip */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1085 | static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1086 | { |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1087 | u32 tmp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1088 | |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 1089 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
Alex Deucher | f0738e9 | 2008-10-16 17:12:02 +1000 | [diff] [blame] | 1090 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) || |
Alex Deucher | 45e5190 | 2008-05-28 13:28:59 +1000 | [diff] [blame] | 1091 | (dev_priv->flags & RADEON_IS_IGPGART)) { |
Dave Airlie | f2b04cd | 2007-05-08 15:19:23 +1000 | [diff] [blame] | 1092 | radeon_set_igpgart(dev_priv, on); |
| 1093 | return; |
| 1094 | } |
| 1095 | |
Alex Deucher | c1556f7 | 2009-02-25 16:57:49 -0500 | [diff] [blame] | 1096 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { |
| 1097 | rs600_set_igpgart(dev_priv, on); |
| 1098 | return; |
| 1099 | } |
| 1100 | |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1101 | if (dev_priv->flags & RADEON_IS_PCIE) { |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 1102 | radeon_set_pciegart(dev_priv, on); |
| 1103 | return; |
| 1104 | } |
| 1105 | |
Dave Airlie | bc5f452 | 2007-11-05 12:50:58 +1000 | [diff] [blame] | 1106 | tmp = RADEON_READ(RADEON_AIC_CNTL); |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1107 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1108 | if (on) { |
| 1109 | RADEON_WRITE(RADEON_AIC_CNTL, |
| 1110 | tmp | RADEON_PCIGART_TRANSLATE_EN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1111 | |
| 1112 | /* set PCI GART page-table base address |
| 1113 | */ |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 1114 | RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1115 | |
| 1116 | /* set address range for PCI address translate |
| 1117 | */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1118 | RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); |
| 1119 | RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start |
| 1120 | + dev_priv->gart_size - 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1121 | |
| 1122 | /* Turn off AGP aperture -- is this required for PCI GART? |
| 1123 | */ |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 1124 | radeon_write_agp_location(dev_priv, 0xffffffc0); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1125 | RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1126 | } else { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1127 | RADEON_WRITE(RADEON_AIC_CNTL, |
| 1128 | tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1129 | } |
| 1130 | } |
| 1131 | |
David Miller | 6abf6bb | 2009-02-14 01:51:07 -0800 | [diff] [blame] | 1132 | static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv) |
| 1133 | { |
| 1134 | struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; |
| 1135 | struct radeon_virt_surface *vp; |
| 1136 | int i; |
| 1137 | |
| 1138 | for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) { |
| 1139 | if (!dev_priv->virt_surfaces[i].file_priv || |
| 1140 | dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV) |
| 1141 | break; |
| 1142 | } |
| 1143 | if (i >= 2 * RADEON_MAX_SURFACES) |
| 1144 | return -ENOMEM; |
| 1145 | vp = &dev_priv->virt_surfaces[i]; |
| 1146 | |
| 1147 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { |
| 1148 | struct radeon_surface *sp = &dev_priv->surfaces[i]; |
| 1149 | if (sp->refcount) |
| 1150 | continue; |
| 1151 | |
| 1152 | vp->surface_index = i; |
| 1153 | vp->lower = gart_info->bus_addr; |
| 1154 | vp->upper = vp->lower + gart_info->table_size; |
| 1155 | vp->flags = 0; |
| 1156 | vp->file_priv = PCIGART_FILE_PRIV; |
| 1157 | |
| 1158 | sp->refcount = 1; |
| 1159 | sp->lower = vp->lower; |
| 1160 | sp->upper = vp->upper; |
| 1161 | sp->flags = 0; |
| 1162 | |
| 1163 | RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags); |
| 1164 | RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower); |
| 1165 | RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper); |
| 1166 | return 0; |
| 1167 | } |
| 1168 | |
| 1169 | return -ENOMEM; |
| 1170 | } |
| 1171 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1172 | static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, |
| 1173 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1174 | { |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1175 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1176 | struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1177 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1178 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1179 | |
Dave Airlie | f3dd5c3 | 2006-03-25 18:09:46 +1100 | [diff] [blame] | 1180 | /* if we require new memory map but we don't have it fail */ |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1181 | if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { |
Dave Airlie | b15ec36 | 2006-08-19 17:43:52 +1000 | [diff] [blame] | 1182 | DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); |
Dave Airlie | f3dd5c3 | 2006-03-25 18:09:46 +1100 | [diff] [blame] | 1183 | radeon_do_cleanup_cp(dev); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1184 | return -EINVAL; |
Dave Airlie | f3dd5c3 | 2006-03-25 18:09:46 +1100 | [diff] [blame] | 1185 | } |
| 1186 | |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1187 | if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1188 | DRM_DEBUG("Forcing AGP card to PCI mode\n"); |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1189 | dev_priv->flags &= ~RADEON_IS_AGP; |
| 1190 | } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) |
Dave Airlie | b15ec36 | 2006-08-19 17:43:52 +1000 | [diff] [blame] | 1191 | && !init->is_pci) { |
| 1192 | DRM_DEBUG("Restoring AGP flag\n"); |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1193 | dev_priv->flags |= RADEON_IS_AGP; |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1194 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1195 | |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1196 | if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1197 | DRM_ERROR("PCI GART memory not allocated!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1198 | radeon_do_cleanup_cp(dev); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1199 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1200 | } |
| 1201 | |
| 1202 | dev_priv->usec_timeout = init->usec_timeout; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1203 | if (dev_priv->usec_timeout < 1 || |
| 1204 | dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { |
| 1205 | DRM_DEBUG("TIMEOUT problem!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1206 | radeon_do_cleanup_cp(dev); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1207 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1208 | } |
| 1209 | |
Dave Airlie | ddbee33 | 2007-07-11 12:16:01 +1000 | [diff] [blame] | 1210 | /* Enable vblank on CRTC1 for older X servers |
| 1211 | */ |
| 1212 | dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; |
| 1213 | |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1214 | switch(init->func) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1215 | case RADEON_INIT_R200_CP: |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1216 | dev_priv->microcode_version = UCODE_R200; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1217 | break; |
| 1218 | case RADEON_INIT_R300_CP: |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1219 | dev_priv->microcode_version = UCODE_R300; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1220 | break; |
| 1221 | default: |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1222 | dev_priv->microcode_version = UCODE_R100; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1223 | } |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1224 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1225 | dev_priv->do_boxes = 0; |
| 1226 | dev_priv->cp_mode = init->cp_mode; |
| 1227 | |
| 1228 | /* We don't support anything other than bus-mastering ring mode, |
| 1229 | * but the ring can be in either AGP or PCI space for the ring |
| 1230 | * read pointer. |
| 1231 | */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1232 | if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && |
| 1233 | (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { |
| 1234 | DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1235 | radeon_do_cleanup_cp(dev); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1236 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1237 | } |
| 1238 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1239 | switch (init->fb_bpp) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1240 | case 16: |
| 1241 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; |
| 1242 | break; |
| 1243 | case 32: |
| 1244 | default: |
| 1245 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; |
| 1246 | break; |
| 1247 | } |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1248 | dev_priv->front_offset = init->front_offset; |
| 1249 | dev_priv->front_pitch = init->front_pitch; |
| 1250 | dev_priv->back_offset = init->back_offset; |
| 1251 | dev_priv->back_pitch = init->back_pitch; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1252 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1253 | switch (init->depth_bpp) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1254 | case 16: |
| 1255 | dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; |
| 1256 | break; |
| 1257 | case 32: |
| 1258 | default: |
| 1259 | dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; |
| 1260 | break; |
| 1261 | } |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1262 | dev_priv->depth_offset = init->depth_offset; |
| 1263 | dev_priv->depth_pitch = init->depth_pitch; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1264 | |
| 1265 | /* Hardware state for depth clears. Remove this if/when we no |
| 1266 | * longer clear the depth buffer with a 3D rectangle. Hard-code |
| 1267 | * all values to prevent unwanted 3D state from slipping through |
| 1268 | * and screwing with the clear operation. |
| 1269 | */ |
| 1270 | dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | |
| 1271 | (dev_priv->color_fmt << 10) | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1272 | (dev_priv->microcode_version == |
| 1273 | UCODE_R100 ? RADEON_ZBLOCK16 : 0)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1274 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1275 | dev_priv->depth_clear.rb3d_zstencilcntl = |
| 1276 | (dev_priv->depth_fmt | |
| 1277 | RADEON_Z_TEST_ALWAYS | |
| 1278 | RADEON_STENCIL_TEST_ALWAYS | |
| 1279 | RADEON_STENCIL_S_FAIL_REPLACE | |
| 1280 | RADEON_STENCIL_ZPASS_REPLACE | |
| 1281 | RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1282 | |
| 1283 | dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | |
| 1284 | RADEON_BFACE_SOLID | |
| 1285 | RADEON_FFACE_SOLID | |
| 1286 | RADEON_FLAT_SHADE_VTX_LAST | |
| 1287 | RADEON_DIFFUSE_SHADE_FLAT | |
| 1288 | RADEON_ALPHA_SHADE_FLAT | |
| 1289 | RADEON_SPECULAR_SHADE_FLAT | |
| 1290 | RADEON_FOG_SHADE_FLAT | |
| 1291 | RADEON_VTX_PIX_CENTER_OGL | |
| 1292 | RADEON_ROUND_MODE_TRUNC | |
| 1293 | RADEON_ROUND_PREC_8TH_PIX); |
| 1294 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1295 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1296 | dev_priv->ring_offset = init->ring_offset; |
| 1297 | dev_priv->ring_rptr_offset = init->ring_rptr_offset; |
| 1298 | dev_priv->buffers_offset = init->buffers_offset; |
| 1299 | dev_priv->gart_textures_offset = init->gart_textures_offset; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1300 | |
David Herrmann | 9fc5cde | 2014-08-29 12:12:28 +0200 | [diff] [blame] | 1301 | master_priv->sarea = drm_legacy_getsarea(dev); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1302 | if (!master_priv->sarea) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1303 | DRM_ERROR("could not find sarea!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1304 | radeon_do_cleanup_cp(dev); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1305 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1306 | } |
| 1307 | |
Daniel Vetter | 86c1fbd | 2014-09-10 12:43:56 +0200 | [diff] [blame] | 1308 | dev_priv->cp_ring = drm_legacy_findmap(dev, init->ring_offset); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1309 | if (!dev_priv->cp_ring) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1310 | DRM_ERROR("could not find cp ring region!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1311 | radeon_do_cleanup_cp(dev); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1312 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1313 | } |
Daniel Vetter | 86c1fbd | 2014-09-10 12:43:56 +0200 | [diff] [blame] | 1314 | dev_priv->ring_rptr = drm_legacy_findmap(dev, init->ring_rptr_offset); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1315 | if (!dev_priv->ring_rptr) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1316 | DRM_ERROR("could not find ring read pointer!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1317 | radeon_do_cleanup_cp(dev); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1318 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1319 | } |
Dave Airlie | d1f2b55 | 2005-08-05 22:11:22 +1000 | [diff] [blame] | 1320 | dev->agp_buffer_token = init->buffers_offset; |
Daniel Vetter | 86c1fbd | 2014-09-10 12:43:56 +0200 | [diff] [blame] | 1321 | dev->agp_buffer_map = drm_legacy_findmap(dev, init->buffers_offset); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1322 | if (!dev->agp_buffer_map) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1323 | DRM_ERROR("could not find dma buffer region!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1324 | radeon_do_cleanup_cp(dev); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1325 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1326 | } |
| 1327 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1328 | if (init->gart_textures_offset) { |
| 1329 | dev_priv->gart_textures = |
Daniel Vetter | 86c1fbd | 2014-09-10 12:43:56 +0200 | [diff] [blame] | 1330 | drm_legacy_findmap(dev, init->gart_textures_offset); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1331 | if (!dev_priv->gart_textures) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1332 | DRM_ERROR("could not find GART texture region!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1333 | radeon_do_cleanup_cp(dev); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1334 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1335 | } |
| 1336 | } |
| 1337 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1338 | #if __OS_HAS_AGP |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1339 | if (dev_priv->flags & RADEON_IS_AGP) { |
Daniel Vetter | 86c1fbd | 2014-09-10 12:43:56 +0200 | [diff] [blame] | 1340 | drm_legacy_ioremap_wc(dev_priv->cp_ring, dev); |
| 1341 | drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev); |
| 1342 | drm_legacy_ioremap_wc(dev->agp_buffer_map, dev); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1343 | if (!dev_priv->cp_ring->handle || |
| 1344 | !dev_priv->ring_rptr->handle || |
| 1345 | !dev->agp_buffer_map->handle) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1346 | DRM_ERROR("could not find ioremap agp regions!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1347 | radeon_do_cleanup_cp(dev); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1348 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1349 | } |
| 1350 | } else |
| 1351 | #endif |
| 1352 | { |
Benjamin Herrenschmidt | 41c2e75 | 2009-02-02 16:55:47 +1100 | [diff] [blame] | 1353 | dev_priv->cp_ring->handle = |
| 1354 | (void *)(unsigned long)dev_priv->cp_ring->offset; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1355 | dev_priv->ring_rptr->handle = |
Benjamin Herrenschmidt | 41c2e75 | 2009-02-02 16:55:47 +1100 | [diff] [blame] | 1356 | (void *)(unsigned long)dev_priv->ring_rptr->offset; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1357 | dev->agp_buffer_map->handle = |
Benjamin Herrenschmidt | 41c2e75 | 2009-02-02 16:55:47 +1100 | [diff] [blame] | 1358 | (void *)(unsigned long)dev->agp_buffer_map->offset; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1359 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1360 | DRM_DEBUG("dev_priv->cp_ring->handle %p\n", |
| 1361 | dev_priv->cp_ring->handle); |
| 1362 | DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", |
| 1363 | dev_priv->ring_rptr->handle); |
| 1364 | DRM_DEBUG("dev->agp_buffer_map->handle %p\n", |
| 1365 | dev->agp_buffer_map->handle); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1366 | } |
| 1367 | |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 1368 | dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; |
Dave Airlie | bc5f452 | 2007-11-05 12:50:58 +1000 | [diff] [blame] | 1369 | dev_priv->fb_size = |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 1370 | ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 1371 | - dev_priv->fb_location; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1372 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1373 | dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | |
| 1374 | ((dev_priv->front_offset |
| 1375 | + dev_priv->fb_location) >> 10)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1376 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1377 | dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | |
| 1378 | ((dev_priv->back_offset |
| 1379 | + dev_priv->fb_location) >> 10)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1380 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1381 | dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | |
| 1382 | ((dev_priv->depth_offset |
| 1383 | + dev_priv->fb_location) >> 10)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1384 | |
| 1385 | dev_priv->gart_size = init->gart_size; |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 1386 | |
| 1387 | /* New let's set the memory map ... */ |
| 1388 | if (dev_priv->new_memmap) { |
| 1389 | u32 base = 0; |
| 1390 | |
| 1391 | DRM_INFO("Setting GART location based on new memory map\n"); |
| 1392 | |
| 1393 | /* If using AGP, try to locate the AGP aperture at the same |
| 1394 | * location in the card and on the bus, though we have to |
| 1395 | * align it down. |
| 1396 | */ |
| 1397 | #if __OS_HAS_AGP |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1398 | if (dev_priv->flags & RADEON_IS_AGP) { |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 1399 | base = dev->agp->base; |
| 1400 | /* Check if valid */ |
Michel Dänzer | 80b2c38 | 2007-02-18 18:03:21 +1100 | [diff] [blame] | 1401 | if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && |
| 1402 | base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 1403 | DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", |
| 1404 | dev->agp->base); |
| 1405 | base = 0; |
| 1406 | } |
| 1407 | } |
| 1408 | #endif |
| 1409 | /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ |
| 1410 | if (base == 0) { |
| 1411 | base = dev_priv->fb_location + dev_priv->fb_size; |
Michel Dänzer | 80b2c38 | 2007-02-18 18:03:21 +1100 | [diff] [blame] | 1412 | if (base < dev_priv->fb_location || |
| 1413 | ((base + dev_priv->gart_size) & 0xfffffffful) < base) |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 1414 | base = dev_priv->fb_location |
| 1415 | - dev_priv->gart_size; |
Dave Airlie | bc5f452 | 2007-11-05 12:50:58 +1000 | [diff] [blame] | 1416 | } |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 1417 | dev_priv->gart_vm_start = base & 0xffc00000u; |
| 1418 | if (dev_priv->gart_vm_start != base) |
| 1419 | DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", |
| 1420 | base, dev_priv->gart_vm_start); |
| 1421 | } else { |
| 1422 | DRM_INFO("Setting GART location based on old memory map\n"); |
| 1423 | dev_priv->gart_vm_start = dev_priv->fb_location + |
| 1424 | RADEON_READ(RADEON_CONFIG_APER_SIZE); |
| 1425 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1426 | |
| 1427 | #if __OS_HAS_AGP |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1428 | if (dev_priv->flags & RADEON_IS_AGP) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1429 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1430 | - dev->agp->base |
| 1431 | + dev_priv->gart_vm_start); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1432 | else |
| 1433 | #endif |
| 1434 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset |
Ivan Kokshaysky | b0917bd | 2005-10-26 11:05:25 +0100 | [diff] [blame] | 1435 | - (unsigned long)dev->sg->virtual |
| 1436 | + dev_priv->gart_vm_start); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1437 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1438 | DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); |
| 1439 | DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); |
| 1440 | DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", |
| 1441 | dev_priv->gart_buffers_offset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1442 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1443 | dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; |
| 1444 | dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1445 | + init->ring_size / sizeof(u32)); |
| 1446 | dev_priv->ring.size = init->ring_size; |
Daniel Vetter | b72a892 | 2013-07-10 14:11:59 +0200 | [diff] [blame] | 1447 | dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1448 | |
Roland Scheidegger | 576cc45 | 2008-02-07 14:59:24 +1000 | [diff] [blame] | 1449 | dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; |
Daniel Vetter | b72a892 | 2013-07-10 14:11:59 +0200 | [diff] [blame] | 1450 | dev_priv->ring.rptr_update_l2qw = order_base_2( /* init->rptr_update */ 4096 / 8); |
Roland Scheidegger | 576cc45 | 2008-02-07 14:59:24 +1000 | [diff] [blame] | 1451 | |
| 1452 | dev_priv->ring.fetch_size = /* init->fetch_size */ 32; |
Daniel Vetter | b72a892 | 2013-07-10 14:11:59 +0200 | [diff] [blame] | 1453 | dev_priv->ring.fetch_size_l2ow = order_base_2( /* init->fetch_size */ 32 / 16); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1454 | dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1455 | |
| 1456 | dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; |
| 1457 | |
| 1458 | #if __OS_HAS_AGP |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1459 | if (dev_priv->flags & RADEON_IS_AGP) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1460 | /* Turn off PCI GART */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1461 | radeon_set_pcigart(dev_priv, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1462 | } else |
| 1463 | #endif |
| 1464 | { |
David Miller | 6abf6bb | 2009-02-14 01:51:07 -0800 | [diff] [blame] | 1465 | u32 sctrl; |
| 1466 | int ret; |
| 1467 | |
Dave Airlie | b05c238 | 2008-03-17 10:24:24 +1000 | [diff] [blame] | 1468 | dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 1469 | /* if we have an offset set from userspace */ |
Dave Airlie | f2b04cd | 2007-05-08 15:19:23 +1000 | [diff] [blame] | 1470 | if (dev_priv->pcigart_offset_set) { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1471 | dev_priv->gart_info.bus_addr = |
Benjamin Herrenschmidt | 41c2e75 | 2009-02-02 16:55:47 +1100 | [diff] [blame] | 1472 | (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location; |
Dave Airlie | f26c473 | 2006-01-02 17:18:39 +1100 | [diff] [blame] | 1473 | dev_priv->gart_info.mapping.offset = |
Dave Airlie | 7fc8686 | 2007-11-05 10:45:27 +1000 | [diff] [blame] | 1474 | dev_priv->pcigart_offset + dev_priv->fb_aper_offset; |
Dave Airlie | f26c473 | 2006-01-02 17:18:39 +1100 | [diff] [blame] | 1475 | dev_priv->gart_info.mapping.size = |
Dave Airlie | f2b04cd | 2007-05-08 15:19:23 +1000 | [diff] [blame] | 1476 | dev_priv->gart_info.table_size; |
Dave Airlie | f26c473 | 2006-01-02 17:18:39 +1100 | [diff] [blame] | 1477 | |
Daniel Vetter | 86c1fbd | 2014-09-10 12:43:56 +0200 | [diff] [blame] | 1478 | drm_legacy_ioremap_wc(&dev_priv->gart_info.mapping, dev); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1479 | dev_priv->gart_info.addr = |
Dave Airlie | f26c473 | 2006-01-02 17:18:39 +1100 | [diff] [blame] | 1480 | dev_priv->gart_info.mapping.handle; |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 1481 | |
Dave Airlie | f2b04cd | 2007-05-08 15:19:23 +1000 | [diff] [blame] | 1482 | if (dev_priv->flags & RADEON_IS_PCIE) |
| 1483 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; |
| 1484 | else |
| 1485 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1486 | dev_priv->gart_info.gart_table_location = |
| 1487 | DRM_ATI_GART_FB; |
| 1488 | |
Dave Airlie | f26c473 | 2006-01-02 17:18:39 +1100 | [diff] [blame] | 1489 | DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1490 | dev_priv->gart_info.addr, |
| 1491 | dev_priv->pcigart_offset); |
| 1492 | } else { |
Dave Airlie | f2b04cd | 2007-05-08 15:19:23 +1000 | [diff] [blame] | 1493 | if (dev_priv->flags & RADEON_IS_IGPGART) |
| 1494 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; |
| 1495 | else |
| 1496 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1497 | dev_priv->gart_info.gart_table_location = |
| 1498 | DRM_ATI_GART_MAIN; |
Dave Airlie | f26c473 | 2006-01-02 17:18:39 +1100 | [diff] [blame] | 1499 | dev_priv->gart_info.addr = NULL; |
| 1500 | dev_priv->gart_info.bus_addr = 0; |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1501 | if (dev_priv->flags & RADEON_IS_PCIE) { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1502 | DRM_ERROR |
| 1503 | ("Cannot use PCI Express without GART in FB memory\n"); |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 1504 | radeon_do_cleanup_cp(dev); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1505 | return -EINVAL; |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 1506 | } |
| 1507 | } |
| 1508 | |
David Miller | 6abf6bb | 2009-02-14 01:51:07 -0800 | [diff] [blame] | 1509 | sctrl = RADEON_READ(RADEON_SURFACE_CNTL); |
| 1510 | RADEON_WRITE(RADEON_SURFACE_CNTL, 0); |
Alex Deucher | c1556f7 | 2009-02-25 16:57:49 -0500 | [diff] [blame] | 1511 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) |
| 1512 | ret = r600_page_table_init(dev); |
| 1513 | else |
| 1514 | ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info); |
David Miller | 6abf6bb | 2009-02-14 01:51:07 -0800 | [diff] [blame] | 1515 | RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl); |
| 1516 | |
| 1517 | if (!ret) { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1518 | DRM_ERROR("failed to init PCI GART!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1519 | radeon_do_cleanup_cp(dev); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1520 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1521 | } |
| 1522 | |
David Miller | 6abf6bb | 2009-02-14 01:51:07 -0800 | [diff] [blame] | 1523 | ret = radeon_setup_pcigart_surface(dev_priv); |
| 1524 | if (ret) { |
| 1525 | DRM_ERROR("failed to setup GART surface!\n"); |
Alex Deucher | c1556f7 | 2009-02-25 16:57:49 -0500 | [diff] [blame] | 1526 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) |
| 1527 | r600_page_table_cleanup(dev, &dev_priv->gart_info); |
| 1528 | else |
| 1529 | drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info); |
David Miller | 6abf6bb | 2009-02-14 01:51:07 -0800 | [diff] [blame] | 1530 | radeon_do_cleanup_cp(dev); |
| 1531 | return ret; |
| 1532 | } |
| 1533 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1534 | /* Turn on PCI GART */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1535 | radeon_set_pcigart(dev_priv, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1536 | } |
| 1537 | |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 1538 | if (!dev_priv->me_fw) { |
| 1539 | int err = radeon_cp_init_microcode(dev_priv); |
| 1540 | if (err) { |
| 1541 | DRM_ERROR("Failed to load firmware!\n"); |
| 1542 | radeon_do_cleanup_cp(dev); |
| 1543 | return err; |
| 1544 | } |
| 1545 | } |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1546 | radeon_cp_load_microcode(dev_priv); |
etienne | 3d16118 | 2009-02-20 09:44:45 +1000 | [diff] [blame] | 1547 | radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1548 | |
| 1549 | dev_priv->last_buf = 0; |
| 1550 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1551 | radeon_do_engine_reset(dev); |
Dave Airlie | d5ea702 | 2006-03-19 19:37:55 +1100 | [diff] [blame] | 1552 | radeon_test_writeback(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1553 | |
| 1554 | return 0; |
| 1555 | } |
| 1556 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1557 | static int radeon_do_cleanup_cp(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1558 | { |
| 1559 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1560 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1561 | |
| 1562 | /* Make sure interrupts are disabled here because the uninstall ioctl |
| 1563 | * may not have been called from userspace and after dev_private |
| 1564 | * is freed, it's too late. |
| 1565 | */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1566 | if (dev->irq_enabled) |
| 1567 | drm_irq_uninstall(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1568 | |
| 1569 | #if __OS_HAS_AGP |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1570 | if (dev_priv->flags & RADEON_IS_AGP) { |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1571 | if (dev_priv->cp_ring != NULL) { |
Daniel Vetter | 86c1fbd | 2014-09-10 12:43:56 +0200 | [diff] [blame] | 1572 | drm_legacy_ioremapfree(dev_priv->cp_ring, dev); |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1573 | dev_priv->cp_ring = NULL; |
| 1574 | } |
| 1575 | if (dev_priv->ring_rptr != NULL) { |
Daniel Vetter | 86c1fbd | 2014-09-10 12:43:56 +0200 | [diff] [blame] | 1576 | drm_legacy_ioremapfree(dev_priv->ring_rptr, dev); |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1577 | dev_priv->ring_rptr = NULL; |
| 1578 | } |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1579 | if (dev->agp_buffer_map != NULL) { |
Daniel Vetter | 86c1fbd | 2014-09-10 12:43:56 +0200 | [diff] [blame] | 1580 | drm_legacy_ioremapfree(dev->agp_buffer_map, dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1581 | dev->agp_buffer_map = NULL; |
| 1582 | } |
| 1583 | } else |
| 1584 | #endif |
| 1585 | { |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1586 | |
| 1587 | if (dev_priv->gart_info.bus_addr) { |
| 1588 | /* Turn off PCI GART */ |
| 1589 | radeon_set_pcigart(dev_priv, 0); |
Alex Deucher | c1556f7 | 2009-02-25 16:57:49 -0500 | [diff] [blame] | 1590 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) |
| 1591 | r600_page_table_cleanup(dev, &dev_priv->gart_info); |
| 1592 | else { |
| 1593 | if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) |
| 1594 | DRM_ERROR("failed to cleanup PCI GART!\n"); |
| 1595 | } |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1596 | } |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1597 | |
Dave Airlie | d985c10 | 2006-01-02 21:32:48 +1100 | [diff] [blame] | 1598 | if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) |
| 1599 | { |
Daniel Vetter | 86c1fbd | 2014-09-10 12:43:56 +0200 | [diff] [blame] | 1600 | drm_legacy_ioremapfree(&dev_priv->gart_info.mapping, dev); |
Hannes Eder | 8f497aa | 2009-03-05 20:14:18 +0100 | [diff] [blame] | 1601 | dev_priv->gart_info.addr = NULL; |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 1602 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1603 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1604 | /* only clear to the start of flags */ |
| 1605 | memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); |
| 1606 | |
| 1607 | return 0; |
| 1608 | } |
| 1609 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1610 | /* This code will reinit the Radeon CP hardware after a resume from disc. |
| 1611 | * AFAIK, it would be very difficult to pickle the state at suspend time, so |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1612 | * here we make sure that all Radeon hardware initialisation is re-done without |
| 1613 | * affecting running applications. |
| 1614 | * |
| 1615 | * Charl P. Botha <http://cpbotha.net> |
| 1616 | */ |
etienne | 3d16118 | 2009-02-20 09:44:45 +1000 | [diff] [blame] | 1617 | static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1618 | { |
| 1619 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1620 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1621 | if (!dev_priv) { |
| 1622 | DRM_ERROR("Called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1623 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1624 | } |
| 1625 | |
| 1626 | DRM_DEBUG("Starting radeon_do_resume_cp()\n"); |
| 1627 | |
| 1628 | #if __OS_HAS_AGP |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 1629 | if (dev_priv->flags & RADEON_IS_AGP) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1630 | /* Turn off PCI GART */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1631 | radeon_set_pcigart(dev_priv, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1632 | } else |
| 1633 | #endif |
| 1634 | { |
| 1635 | /* Turn on PCI GART */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1636 | radeon_set_pcigart(dev_priv, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1637 | } |
| 1638 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1639 | radeon_cp_load_microcode(dev_priv); |
etienne | 3d16118 | 2009-02-20 09:44:45 +1000 | [diff] [blame] | 1640 | radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1641 | |
Dave Airlie | 566d84d | 2010-02-24 17:17:13 +1000 | [diff] [blame] | 1642 | dev_priv->have_z_offset = 0; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1643 | radeon_do_engine_reset(dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1644 | radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1645 | |
| 1646 | DRM_DEBUG("radeon_do_resume_cp() complete\n"); |
| 1647 | |
| 1648 | return 0; |
| 1649 | } |
| 1650 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1651 | int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1652 | { |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1653 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1654 | drm_radeon_init_t *init = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1655 | |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1656 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1657 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1658 | if (init->func == RADEON_INIT_R300_CP) |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 1659 | r300_init_reg_flags(dev); |
Dave Airlie | 414ed53 | 2005-08-16 20:43:16 +1000 | [diff] [blame] | 1660 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1661 | switch (init->func) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1662 | case RADEON_INIT_CP: |
| 1663 | case RADEON_INIT_R200_CP: |
| 1664 | case RADEON_INIT_R300_CP: |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1665 | return radeon_do_init_cp(dev, init, file_priv); |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1666 | case RADEON_INIT_R600_CP: |
| 1667 | return r600_do_init_cp(dev, init, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1668 | case RADEON_CLEANUP_CP: |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1669 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 1670 | return r600_do_cleanup_cp(dev); |
| 1671 | else |
| 1672 | return radeon_do_cleanup_cp(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1673 | } |
| 1674 | |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1675 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1676 | } |
| 1677 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1678 | int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1679 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1680 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1681 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1682 | |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1683 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1684 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1685 | if (dev_priv->cp_running) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1686 | DRM_DEBUG("while CP running\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1687 | return 0; |
| 1688 | } |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1689 | if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1690 | DRM_DEBUG("called with bogus CP mode (%d)\n", |
| 1691 | dev_priv->cp_mode); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1692 | return 0; |
| 1693 | } |
| 1694 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1695 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 1696 | r600_do_cp_start(dev_priv); |
| 1697 | else |
| 1698 | radeon_do_cp_start(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1699 | |
| 1700 | return 0; |
| 1701 | } |
| 1702 | |
| 1703 | /* Stop the CP. The engine must have been idled before calling this |
| 1704 | * routine. |
| 1705 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1706 | int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1707 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1708 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1709 | drm_radeon_cp_stop_t *stop = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1710 | int ret; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1711 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1712 | |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1713 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1714 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1715 | if (!dev_priv->cp_running) |
| 1716 | return 0; |
| 1717 | |
| 1718 | /* Flush any pending CP commands. This ensures any outstanding |
| 1719 | * commands are exectuted by the engine before we turn it off. |
| 1720 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1721 | if (stop->flush) { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1722 | radeon_do_cp_flush(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1723 | } |
| 1724 | |
| 1725 | /* If we fail to make the engine go idle, we return an error |
| 1726 | * code so that the DRM ioctl wrapper can try again. |
| 1727 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1728 | if (stop->idle) { |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1729 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 1730 | ret = r600_do_cp_idle(dev_priv); |
| 1731 | else |
| 1732 | ret = radeon_do_cp_idle(dev_priv); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1733 | if (ret) |
| 1734 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1735 | } |
| 1736 | |
| 1737 | /* Finally, we can turn off the CP. If the engine isn't idle, |
| 1738 | * we will get some dropped triangles as they won't be fully |
| 1739 | * rendered before the CP is shut down. |
| 1740 | */ |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1741 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 1742 | r600_do_cp_stop(dev_priv); |
| 1743 | else |
| 1744 | radeon_do_cp_stop(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1745 | |
| 1746 | /* Reset the engine */ |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1747 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 1748 | r600_do_engine_reset(dev); |
| 1749 | else |
| 1750 | radeon_do_engine_reset(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1751 | |
| 1752 | return 0; |
| 1753 | } |
| 1754 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1755 | void radeon_do_release(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1756 | { |
| 1757 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1758 | int i, ret; |
| 1759 | |
| 1760 | if (dev_priv) { |
| 1761 | if (dev_priv->cp_running) { |
| 1762 | /* Stop the cp */ |
Dave Airlie | 53c379e | 2009-03-09 12:12:28 +1000 | [diff] [blame] | 1763 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1764 | while ((ret = r600_do_cp_idle(dev_priv)) != 0) { |
| 1765 | DRM_DEBUG("radeon_do_cp_idle %d\n", ret); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1766 | #ifdef __linux__ |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1767 | schedule(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1768 | #else |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1769 | tsleep(&ret, PZERO, "rdnrel", 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1770 | #endif |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1771 | } |
| 1772 | } else { |
| 1773 | while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { |
| 1774 | DRM_DEBUG("radeon_do_cp_idle %d\n", ret); |
| 1775 | #ifdef __linux__ |
| 1776 | schedule(); |
| 1777 | #else |
| 1778 | tsleep(&ret, PZERO, "rdnrel", 1); |
| 1779 | #endif |
| 1780 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1781 | } |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1782 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { |
| 1783 | r600_do_cp_stop(dev_priv); |
| 1784 | r600_do_engine_reset(dev); |
| 1785 | } else { |
| 1786 | radeon_do_cp_stop(dev_priv); |
| 1787 | radeon_do_engine_reset(dev); |
| 1788 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1789 | } |
| 1790 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1791 | if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) { |
| 1792 | /* Disable *all* interrupts */ |
| 1793 | if (dev_priv->mmio) /* remove this after permanent addmaps */ |
| 1794 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1795 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1796 | if (dev_priv->mmio) { /* remove all surfaces */ |
| 1797 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { |
| 1798 | RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); |
| 1799 | RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + |
| 1800 | 16 * i, 0); |
| 1801 | RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + |
| 1802 | 16 * i, 0); |
| 1803 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1804 | } |
| 1805 | } |
| 1806 | |
| 1807 | /* Free memory heap structures */ |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1808 | radeon_mem_takedown(&(dev_priv->gart_heap)); |
| 1809 | radeon_mem_takedown(&(dev_priv->fb_heap)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1810 | |
| 1811 | /* deallocate kernel resources */ |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1812 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 1813 | r600_do_cleanup_cp(dev); |
| 1814 | else |
| 1815 | radeon_do_cleanup_cp(dev); |
Jesper Juhl | c69a6ca | 2012-04-09 22:49:57 +0200 | [diff] [blame] | 1816 | release_firmware(dev_priv->me_fw); |
| 1817 | dev_priv->me_fw = NULL; |
| 1818 | release_firmware(dev_priv->pfp_fw); |
| 1819 | dev_priv->pfp_fw = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1820 | } |
| 1821 | } |
| 1822 | |
| 1823 | /* Just reset the CP ring. Called as part of an X Server engine reset. |
| 1824 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1825 | int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1826 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1827 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1828 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1829 | |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1830 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1831 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1832 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1833 | DRM_DEBUG("called before init done\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1834 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1835 | } |
| 1836 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1837 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 1838 | r600_do_cp_reset(dev_priv); |
| 1839 | else |
| 1840 | radeon_do_cp_reset(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1841 | |
| 1842 | /* The CP is no longer running after an engine reset */ |
| 1843 | dev_priv->cp_running = 0; |
| 1844 | |
| 1845 | return 0; |
| 1846 | } |
| 1847 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1848 | int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1849 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1850 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1851 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1852 | |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1853 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1854 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1855 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 1856 | return r600_do_cp_idle(dev_priv); |
| 1857 | else |
| 1858 | return radeon_do_cp_idle(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1859 | } |
| 1860 | |
| 1861 | /* Added by Charl P. Botha to call radeon_do_resume_cp(). |
| 1862 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1863 | int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1864 | { |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1865 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1866 | DRM_DEBUG("\n"); |
| 1867 | |
| 1868 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 1869 | return r600_do_resume_cp(dev, file_priv); |
| 1870 | else |
| 1871 | return radeon_do_resume_cp(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1872 | } |
| 1873 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1874 | int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1875 | { |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1876 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1877 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1878 | |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1879 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1880 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 1881 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) |
| 1882 | return r600_do_engine_reset(dev); |
| 1883 | else |
| 1884 | return radeon_do_engine_reset(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1885 | } |
| 1886 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1887 | /* ================================================================ |
| 1888 | * Fullscreen mode |
| 1889 | */ |
| 1890 | |
| 1891 | /* KW: Deprecated to say the least: |
| 1892 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1893 | int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1894 | { |
| 1895 | return 0; |
| 1896 | } |
| 1897 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1898 | /* ================================================================ |
| 1899 | * Freelist management |
| 1900 | */ |
| 1901 | |
| 1902 | /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through |
| 1903 | * bufs until freelist code is used. Note this hides a problem with |
| 1904 | * the scratch register * (used to keep track of last buffer |
| 1905 | * completed) being written to before * the last buffer has actually |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1906 | * completed rendering. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1907 | * |
| 1908 | * KW: It's also a good way to find free buffers quickly. |
| 1909 | * |
| 1910 | * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't |
| 1911 | * sleep. However, bugs in older versions of radeon_accel.c mean that |
| 1912 | * we essentially have to do this, else old clients will break. |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1913 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1914 | * However, it does leave open a potential deadlock where all the |
| 1915 | * buffers are held by other clients, which can't release them because |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1916 | * they can't get the lock. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1917 | */ |
| 1918 | |
Dave Airlie | 056219e | 2007-07-11 16:17:42 +1000 | [diff] [blame] | 1919 | struct drm_buf *radeon_freelist_get(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1920 | { |
Dave Airlie | cdd55a2 | 2007-07-11 16:32:08 +1000 | [diff] [blame] | 1921 | struct drm_device_dma *dma = dev->dma; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1922 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1923 | drm_radeon_buf_priv_t *buf_priv; |
Dave Airlie | 056219e | 2007-07-11 16:17:42 +1000 | [diff] [blame] | 1924 | struct drm_buf *buf; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1925 | int i, t; |
| 1926 | int start; |
| 1927 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1928 | if (++dev_priv->last_buf >= dma->buf_count) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1929 | dev_priv->last_buf = 0; |
| 1930 | |
| 1931 | start = dev_priv->last_buf; |
| 1932 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1933 | for (t = 0; t < dev_priv->usec_timeout; t++) { |
David Miller | b07fa02 | 2009-02-12 02:15:37 -0800 | [diff] [blame] | 1934 | u32 done_age = GET_SCRATCH(dev_priv, 1); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1935 | DRM_DEBUG("done_age = %d\n", done_age); |
Robert Noland | 0a5c1e6 | 2009-10-20 07:23:07 -0500 | [diff] [blame] | 1936 | for (i = 0; i < dma->buf_count; i++) { |
| 1937 | buf = dma->buflist[start]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1938 | buf_priv = buf->dev_private; |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1939 | if (buf->file_priv == NULL || (buf->pending && |
| 1940 | buf_priv->age <= |
| 1941 | done_age)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1942 | dev_priv->stats.requested_bufs++; |
| 1943 | buf->pending = 0; |
| 1944 | return buf; |
| 1945 | } |
Robert Noland | 0a5c1e6 | 2009-10-20 07:23:07 -0500 | [diff] [blame] | 1946 | if (++start >= dma->buf_count) |
| 1947 | start = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1948 | } |
| 1949 | |
| 1950 | if (t) { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1951 | DRM_UDELAY(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1952 | dev_priv->stats.freelist_loops++; |
| 1953 | } |
| 1954 | } |
| 1955 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1956 | return NULL; |
| 1957 | } |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1958 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1959 | void radeon_freelist_reset(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1960 | { |
Dave Airlie | cdd55a2 | 2007-07-11 16:32:08 +1000 | [diff] [blame] | 1961 | struct drm_device_dma *dma = dev->dma; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1962 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1963 | int i; |
| 1964 | |
| 1965 | dev_priv->last_buf = 0; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1966 | for (i = 0; i < dma->buf_count; i++) { |
Dave Airlie | 056219e | 2007-07-11 16:17:42 +1000 | [diff] [blame] | 1967 | struct drm_buf *buf = dma->buflist[i]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1968 | drm_radeon_buf_priv_t *buf_priv = buf->dev_private; |
| 1969 | buf_priv->age = 0; |
| 1970 | } |
| 1971 | } |
| 1972 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1973 | /* ================================================================ |
| 1974 | * CP command submission |
| 1975 | */ |
| 1976 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1977 | int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1978 | { |
| 1979 | drm_radeon_ring_buffer_t *ring = &dev_priv->ring; |
| 1980 | int i; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1981 | u32 last_head = GET_RING_HEAD(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1982 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1983 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
| 1984 | u32 head = GET_RING_HEAD(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1985 | |
| 1986 | ring->space = (head - ring->tail) * sizeof(u32); |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1987 | if (ring->space <= 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1988 | ring->space += ring->size; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1989 | if (ring->space > n) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1990 | return 0; |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1991 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1992 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
| 1993 | |
| 1994 | if (head != last_head) |
| 1995 | i = 0; |
| 1996 | last_head = head; |
| 1997 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1998 | DRM_UDELAY(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1999 | } |
| 2000 | |
| 2001 | /* FIXME: This return value is ignored in the BEGIN_RING macro! */ |
| 2002 | #if RADEON_FIFO_DEBUG |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 2003 | radeon_status(dev_priv); |
| 2004 | DRM_ERROR("failed!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2005 | #endif |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 2006 | return -EBUSY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2007 | } |
| 2008 | |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 2009 | static int radeon_cp_get_buffers(struct drm_device *dev, |
| 2010 | struct drm_file *file_priv, |
Dave Airlie | c60ce62 | 2007-07-11 15:27:12 +1000 | [diff] [blame] | 2011 | struct drm_dma * d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2012 | { |
| 2013 | int i; |
Dave Airlie | 056219e | 2007-07-11 16:17:42 +1000 | [diff] [blame] | 2014 | struct drm_buf *buf; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2015 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 2016 | for (i = d->granted_count; i < d->request_count; i++) { |
| 2017 | buf = radeon_freelist_get(dev); |
| 2018 | if (!buf) |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 2019 | return -EBUSY; /* NOTE: broken client */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2020 | |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 2021 | buf->file_priv = file_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2022 | |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 2023 | if (copy_to_user(&d->request_indices[i], &buf->idx, |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 2024 | sizeof(buf->idx))) |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 2025 | return -EFAULT; |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 2026 | if (copy_to_user(&d->request_sizes[i], &buf->total, |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 2027 | sizeof(buf->total))) |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 2028 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2029 | |
| 2030 | d->granted_count++; |
| 2031 | } |
| 2032 | return 0; |
| 2033 | } |
| 2034 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 2035 | int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2036 | { |
Dave Airlie | cdd55a2 | 2007-07-11 16:32:08 +1000 | [diff] [blame] | 2037 | struct drm_device_dma *dma = dev->dma; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2038 | int ret = 0; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 2039 | struct drm_dma *d = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2040 | |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 2041 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2042 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2043 | /* Please don't send us buffers. |
| 2044 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 2045 | if (d->send_count != 0) { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 2046 | DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 2047 | DRM_CURRENTPID, d->send_count); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 2048 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2049 | } |
| 2050 | |
| 2051 | /* We'll send you buffers. |
| 2052 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 2053 | if (d->request_count < 0 || d->request_count > dma->buf_count) { |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 2054 | DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 2055 | DRM_CURRENTPID, d->request_count, dma->buf_count); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 2056 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2057 | } |
| 2058 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 2059 | d->granted_count = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2060 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 2061 | if (d->request_count) { |
| 2062 | ret = radeon_cp_get_buffers(dev, file_priv, d); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2063 | } |
| 2064 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2065 | return ret; |
| 2066 | } |
| 2067 | |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 2068 | int radeon_driver_load(struct drm_device *dev, unsigned long flags) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2069 | { |
| 2070 | drm_radeon_private_t *dev_priv; |
| 2071 | int ret = 0; |
| 2072 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 2073 | dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2074 | if (dev_priv == NULL) |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 2075 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2076 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2077 | dev->dev_private = (void *)dev_priv; |
| 2078 | dev_priv->flags = flags; |
| 2079 | |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 2080 | switch (flags & RADEON_FAMILY_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2081 | case CHIP_R100: |
| 2082 | case CHIP_RV200: |
| 2083 | case CHIP_R200: |
| 2084 | case CHIP_R300: |
Dave Airlie | b15ec36 | 2006-08-19 17:43:52 +1000 | [diff] [blame] | 2085 | case CHIP_R350: |
Dave Airlie | 414ed53 | 2005-08-16 20:43:16 +1000 | [diff] [blame] | 2086 | case CHIP_R420: |
Alex Deucher | edc6f38 | 2008-10-17 09:21:45 +1000 | [diff] [blame] | 2087 | case CHIP_R423: |
Dave Airlie | b15ec36 | 2006-08-19 17:43:52 +1000 | [diff] [blame] | 2088 | case CHIP_RV410: |
Dave Airlie | 3d5e2c1 | 2008-02-07 15:01:05 +1000 | [diff] [blame] | 2089 | case CHIP_RV515: |
| 2090 | case CHIP_R520: |
| 2091 | case CHIP_RV570: |
| 2092 | case CHIP_R580: |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 2093 | dev_priv->flags |= RADEON_HAS_HIERZ; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2094 | break; |
| 2095 | default: |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 2096 | /* all other chips have no hierarchical z buffer */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2097 | break; |
| 2098 | } |
Dave Airlie | 414ed53 | 2005-08-16 20:43:16 +1000 | [diff] [blame] | 2099 | |
Dave Airlie | 466e69b | 2011-12-19 11:15:29 +0000 | [diff] [blame] | 2100 | pci_set_master(dev->pdev); |
| 2101 | |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 2102 | if (drm_pci_device_is_agp(dev)) |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 2103 | dev_priv->flags |= RADEON_IS_AGP; |
Jon Mason | 58b6542 | 2011-06-27 16:07:50 +0000 | [diff] [blame] | 2104 | else if (pci_is_pcie(dev->pdev)) |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 2105 | dev_priv->flags |= RADEON_IS_PCIE; |
Dave Airlie | b15ec36 | 2006-08-19 17:43:52 +1000 | [diff] [blame] | 2106 | else |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 2107 | dev_priv->flags |= RADEON_IS_PCI; |
Dave Airlie | ea98a92 | 2005-09-11 20:28:11 +1000 | [diff] [blame] | 2108 | |
David Herrmann | 9fc5cde | 2014-08-29 12:12:28 +0200 | [diff] [blame] | 2109 | ret = drm_legacy_addmap(dev, pci_resource_start(dev->pdev, 2), |
| 2110 | pci_resource_len(dev->pdev, 2), _DRM_REGISTERS, |
| 2111 | _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio); |
Dave Airlie | 78538bf | 2008-11-11 17:56:16 +1000 | [diff] [blame] | 2112 | if (ret != 0) |
| 2113 | return ret; |
| 2114 | |
Keith Packard | 5244021 | 2008-11-18 09:30:25 -0800 | [diff] [blame] | 2115 | ret = drm_vblank_init(dev, 2); |
| 2116 | if (ret) { |
| 2117 | radeon_driver_unload(dev); |
| 2118 | return ret; |
| 2119 | } |
| 2120 | |
Dave Airlie | 414ed53 | 2005-08-16 20:43:16 +1000 | [diff] [blame] | 2121 | DRM_DEBUG("%s card detected\n", |
Dave Airlie | 54a56ac | 2006-09-22 04:25:09 +1000 | [diff] [blame] | 2122 | ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2123 | return ret; |
| 2124 | } |
| 2125 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 2126 | int radeon_master_create(struct drm_device *dev, struct drm_master *master) |
| 2127 | { |
| 2128 | struct drm_radeon_master_private *master_priv; |
| 2129 | unsigned long sareapage; |
| 2130 | int ret; |
| 2131 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 2132 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 2133 | if (!master_priv) |
| 2134 | return -ENOMEM; |
| 2135 | |
| 2136 | /* prebuild the SAREA */ |
Dave Airlie | bdf539a | 2008-12-18 16:56:11 +1000 | [diff] [blame] | 2137 | sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE); |
David Herrmann | 9fc5cde | 2014-08-29 12:12:28 +0200 | [diff] [blame] | 2138 | ret = drm_legacy_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK, |
| 2139 | &master_priv->sarea); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 2140 | if (ret) { |
| 2141 | DRM_ERROR("SAREA setup failed\n"); |
Jiri Slaby | 5eb2261 | 2010-01-06 17:39:31 +0100 | [diff] [blame] | 2142 | kfree(master_priv); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 2143 | return ret; |
| 2144 | } |
| 2145 | master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea); |
| 2146 | master_priv->sarea_priv->pfCurrentPage = 0; |
| 2147 | |
| 2148 | master->driver_priv = master_priv; |
| 2149 | return 0; |
| 2150 | } |
| 2151 | |
| 2152 | void radeon_master_destroy(struct drm_device *dev, struct drm_master *master) |
| 2153 | { |
| 2154 | struct drm_radeon_master_private *master_priv = master->driver_priv; |
| 2155 | |
| 2156 | if (!master_priv) |
| 2157 | return; |
| 2158 | |
| 2159 | if (master_priv->sarea_priv && |
| 2160 | master_priv->sarea_priv->pfCurrentPage != 0) |
| 2161 | radeon_cp_dispatch_flip(dev, master); |
| 2162 | |
| 2163 | master_priv->sarea_priv = NULL; |
| 2164 | if (master_priv->sarea) |
David Herrmann | 9fc5cde | 2014-08-29 12:12:28 +0200 | [diff] [blame] | 2165 | drm_legacy_rmmap_locked(dev, master_priv->sarea); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 2166 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 2167 | kfree(master_priv); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 2168 | |
| 2169 | master->driver_priv = NULL; |
| 2170 | } |
| 2171 | |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 2172 | /* Create mappings for registers and framebuffer so userland doesn't necessarily |
| 2173 | * have to find them. |
| 2174 | */ |
| 2175 | int radeon_driver_firstopen(struct drm_device *dev) |
Dave Airlie | 836cf04 | 2005-07-10 19:27:04 +1000 | [diff] [blame] | 2176 | { |
| 2177 | int ret; |
| 2178 | drm_local_map_t *map; |
| 2179 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 2180 | |
Dave Airlie | f2b04cd | 2007-05-08 15:19:23 +1000 | [diff] [blame] | 2181 | dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; |
| 2182 | |
Jordan Crouse | 01d73a6 | 2010-05-27 13:40:24 -0600 | [diff] [blame] | 2183 | dev_priv->fb_aper_offset = pci_resource_start(dev->pdev, 0); |
David Herrmann | 9fc5cde | 2014-08-29 12:12:28 +0200 | [diff] [blame] | 2184 | ret = drm_legacy_addmap(dev, dev_priv->fb_aper_offset, |
| 2185 | pci_resource_len(dev->pdev, 0), |
| 2186 | _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, &map); |
Dave Airlie | 836cf04 | 2005-07-10 19:27:04 +1000 | [diff] [blame] | 2187 | if (ret != 0) |
| 2188 | return ret; |
| 2189 | |
| 2190 | return 0; |
| 2191 | } |
| 2192 | |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 2193 | int radeon_driver_unload(struct drm_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2194 | { |
| 2195 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 2196 | |
| 2197 | DRM_DEBUG("\n"); |
Dave Airlie | 78538bf | 2008-11-11 17:56:16 +1000 | [diff] [blame] | 2198 | |
David Herrmann | 9fc5cde | 2014-08-29 12:12:28 +0200 | [diff] [blame] | 2199 | drm_legacy_rmmap(dev, dev_priv->mmio); |
Dave Airlie | 78538bf | 2008-11-11 17:56:16 +1000 | [diff] [blame] | 2200 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 2201 | kfree(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2202 | |
| 2203 | dev->dev_private = NULL; |
| 2204 | return 0; |
| 2205 | } |
Dave Airlie | 4247ca9 | 2009-02-20 13:28:34 +1000 | [diff] [blame] | 2206 | |
| 2207 | void radeon_commit_ring(drm_radeon_private_t *dev_priv) |
| 2208 | { |
| 2209 | int i; |
| 2210 | u32 *ring; |
| 2211 | int tail_aligned; |
| 2212 | |
| 2213 | /* check if the ring is padded out to 16-dword alignment */ |
| 2214 | |
Dave Airlie | 9863871 | 2009-06-04 07:08:13 +1000 | [diff] [blame] | 2215 | tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1); |
Dave Airlie | 4247ca9 | 2009-02-20 13:28:34 +1000 | [diff] [blame] | 2216 | if (tail_aligned) { |
Dave Airlie | 9863871 | 2009-06-04 07:08:13 +1000 | [diff] [blame] | 2217 | int num_p2 = RADEON_RING_ALIGN - tail_aligned; |
Dave Airlie | 4247ca9 | 2009-02-20 13:28:34 +1000 | [diff] [blame] | 2218 | |
| 2219 | ring = dev_priv->ring.start; |
| 2220 | /* pad with some CP_PACKET2 */ |
| 2221 | for (i = 0; i < num_p2; i++) |
| 2222 | ring[dev_priv->ring.tail + i] = CP_PACKET2(); |
| 2223 | |
| 2224 | dev_priv->ring.tail += i; |
| 2225 | |
| 2226 | dev_priv->ring.space -= num_p2 * sizeof(u32); |
| 2227 | } |
| 2228 | |
| 2229 | dev_priv->ring.tail &= dev_priv->ring.tail_mask; |
| 2230 | |
Daniel Vetter | 85b2331 | 2013-12-11 11:34:45 +0100 | [diff] [blame] | 2231 | mb(); |
Dave Airlie | 4247ca9 | 2009-02-20 13:28:34 +1000 | [diff] [blame] | 2232 | GET_RING_HEAD( dev_priv ); |
| 2233 | |
Alex Deucher | c05ce08 | 2009-02-24 16:22:29 -0500 | [diff] [blame] | 2234 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { |
| 2235 | RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail); |
| 2236 | /* read from PCI bus to ensure correct posting */ |
| 2237 | RADEON_READ(R600_CP_RB_RPTR); |
| 2238 | } else { |
| 2239 | RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); |
| 2240 | /* read from PCI bus to ensure correct posting */ |
| 2241 | RADEON_READ(RADEON_CP_RB_RPTR); |
| 2242 | } |
Dave Airlie | 4247ca9 | 2009-02-20 13:28:34 +1000 | [diff] [blame] | 2243 | } |