| Mauro Carvalho Chehab | cd4665c | 2005-11-08 21:36:40 -0800 | [diff] [blame] | 1 | #define TVP5150_VD_IN_SRC_SEL_1 0x00 /* Video input source selection #1 */ |
| 2 | #define TVP5150_ANAL_CHL_CTL 0x01 /* Analog channel controls */ |
| 3 | #define TVP5150_OP_MODE_CTL 0x02 /* Operation mode controls */ |
| 4 | #define TVP5150_MISC_CTL 0x03 /* Miscellaneous controls */ |
| 5 | #define TVP5150_AUTOSW_MSK 0x04 /* Autoswitch mask: TVP5150A / TVP5150AM */ |
| 6 | |
| 7 | /* Reserved 05h */ |
| 8 | |
| 9 | #define TVP5150_COLOR_KIL_THSH_CTL 0x06 /* Color killer threshold control */ |
| 10 | #define TVP5150_LUMA_PROC_CTL_1 0x07 /* Luminance processing control #1 */ |
| 11 | #define TVP5150_LUMA_PROC_CTL_2 0x08 /* Luminance processing control #2 */ |
| 12 | #define TVP5150_BRIGHT_CTL 0x09 /* Brightness control */ |
| 13 | #define TVP5150_SATURATION_CTL 0x0a /* Color saturation control */ |
| 14 | #define TVP5150_HUE_CTL 0x0b /* Hue control */ |
| 15 | #define TVP5150_CONTRAST_CTL 0x0c /* Contrast control */ |
| 16 | #define TVP5150_DATA_RATE_SEL 0x0d /* Outputs and data rates select */ |
| 17 | #define TVP5150_LUMA_PROC_CTL_3 0x0e /* Luminance processing control #3 */ |
| 18 | #define TVP5150_CONF_SHARED_PIN 0x0f /* Configuration shared pins */ |
| 19 | |
| 20 | /* Reserved 10h */ |
| 21 | |
| 22 | #define TVP5150_ACT_VD_CROP_ST_MSB 0x11 /* Active video cropping start MSB */ |
| 23 | #define TVP5150_ACT_VD_CROP_ST_LSB 0x12 /* Active video cropping start LSB */ |
| 24 | #define TVP5150_ACT_VD_CROP_STP_MSB 0x13 /* Active video cropping stop MSB */ |
| 25 | #define TVP5150_ACT_VD_CROP_STP_LSB 0x14 /* Active video cropping stop LSB */ |
| 26 | #define TVP5150_GENLOCK 0x15 /* Genlock/RTC */ |
| 27 | #define TVP5150_HORIZ_SYNC_START 0x16 /* Horizontal sync start */ |
| 28 | |
| 29 | /* Reserved 17h */ |
| 30 | |
| 31 | #define TVP5150_VERT_BLANKING_START 0x18 /* Vertical blanking start */ |
| 32 | #define TVP5150_VERT_BLANKING_STOP 0x19 /* Vertical blanking stop */ |
| 33 | #define TVP5150_CHROMA_PROC_CTL_1 0x1a /* Chrominance processing control #1 */ |
| 34 | #define TVP5150_CHROMA_PROC_CTL_2 0x1b /* Chrominance processing control #2 */ |
| 35 | #define TVP5150_INT_RESET_REG_B 0x1c /* Interrupt reset register B */ |
| 36 | #define TVP5150_INT_ENABLE_REG_B 0x1d /* Interrupt enable register B */ |
| 37 | #define TVP5150_INTT_CONFIG_REG_B 0x1e /* Interrupt configuration register B */ |
| 38 | |
| 39 | /* Reserved 1Fh-27h */ |
| 40 | |
| 41 | #define TVP5150_VIDEO_STD 0x28 /* Video standard */ |
| 42 | |
| 43 | /* Reserved 29h-2bh */ |
| 44 | |
| 45 | #define TVP5150_CB_GAIN_FACT 0x2c /* Cb gain factor */ |
| 46 | #define TVP5150_CR_GAIN_FACTOR 0x2d /* Cr gain factor */ |
| 47 | #define TVP5150_MACROVISION_ON_CTR 0x2e /* Macrovision on counter */ |
| 48 | #define TVP5150_MACROVISION_OFF_CTR 0x2f /* Macrovision off counter */ |
| 49 | #define TVP5150_REV_SELECT 0x30 /* revision select (TVP5150AM1 only) */ |
| 50 | |
| 51 | /* Reserved 31h-7Fh */ |
| 52 | |
| 53 | #define TVP5150_MSB_DEV_ID 0x80 /* MSB of device ID */ |
| 54 | #define TVP5150_LSB_DEV_ID 0x81 /* LSB of device ID */ |
| 55 | #define TVP5150_ROM_MAJOR_VER 0x82 /* ROM major version */ |
| 56 | #define TVP5150_ROM_MINOR_VER 0x83 /* ROM minor version */ |
| 57 | #define TVP5150_VERT_LN_COUNT_MSB 0x84 /* Vertical line count MSB */ |
| 58 | #define TVP5150_VERT_LN_COUNT_LSB 0x85 /* Vertical line count LSB */ |
| 59 | #define TVP5150_INT_STATUS_REG_B 0x86 /* Interrupt status register B */ |
| 60 | #define TVP5150_INT_ACTIVE_REG_B 0x87 /* Interrupt active register B */ |
| 61 | #define TVP5150_STATUS_REG_1 0x88 /* Status register #1 */ |
| 62 | #define TVP5150_STATUS_REG_2 0x89 /* Status register #2 */ |
| 63 | #define TVP5150_STATUS_REG_3 0x8a /* Status register #3 */ |
| 64 | #define TVP5150_STATUS_REG_4 0x8b /* Status register #4 */ |
| 65 | #define TVP5150_STATUS_REG_5 0x8c /* Status register #5 */ |
| 66 | /* Reserved 8Dh-8Fh */ |
| 67 | #define TVP5150_CC_DATA_REG1 0x90 /* Closed caption data registers */ |
| 68 | #define TVP5150_CC_DATA_REG2 0x91 /* Closed caption data registers */ |
| 69 | #define TVP5150_CC_DATA_REG3 0x92 /* Closed caption data registers */ |
| 70 | #define TVP5150_CC_DATA_REG4 0x93 /* Closed caption data registers */ |
| 71 | #define TVP5150_WSS_DATA_REG1 0X94 /* WSS data registers */ |
| 72 | #define TVP5150_WSS_DATA_REG2 0X95 /* WSS data registers */ |
| 73 | #define TVP5150_WSS_DATA_REG3 0X96 /* WSS data registers */ |
| 74 | #define TVP5150_WSS_DATA_REG4 0X97 /* WSS data registers */ |
| 75 | #define TVP5150_WSS_DATA_REG5 0X98 /* WSS data registers */ |
| 76 | #define TVP5150_WSS_DATA_REG6 0X99 /* WSS data registers */ |
| 77 | #define TVP5150_VPS_DATA_REG1 0x9a /* VPS data registers */ |
| 78 | #define TVP5150_VPS_DATA_REG2 0x9b /* VPS data registers */ |
| 79 | #define TVP5150_VPS_DATA_REG3 0x9c /* VPS data registers */ |
| 80 | #define TVP5150_VPS_DATA_REG4 0x9d /* VPS data registers */ |
| 81 | #define TVP5150_VPS_DATA_REG5 0x9e /* VPS data registers */ |
| 82 | #define TVP5150_VPS_DATA_REG6 0x9f /* VPS data registers */ |
| 83 | #define TVP5150_VPS_DATA_REG7 0xa0 /* VPS data registers */ |
| 84 | #define TVP5150_VPS_DATA_REG8 0xa1 /* VPS data registers */ |
| 85 | #define TVP5150_VPS_DATA_REG9 0xa2 /* VPS data registers */ |
| 86 | #define TVP5150_VPS_DATA_REG10 0xa3 /* VPS data registers */ |
| 87 | #define TVP5150_VPS_DATA_REG11 0xa4 /* VPS data registers */ |
| 88 | #define TVP5150_VPS_DATA_REG12 0xa5 /* VPS data registers */ |
| 89 | #define TVP5150_VPS_DATA_REG13 0xa6 /* VPS data registers */ |
| 90 | #define TVP5150_VITC_DATA_REG1 0xa7 /* VITC data registers */ |
| 91 | #define TVP5150_VITC_DATA_REG2 0xa8 /* VITC data registers */ |
| 92 | #define TVP5150_VITC_DATA_REG3 0xa9 /* VITC data registers */ |
| 93 | #define TVP5150_VITC_DATA_REG4 0xaa /* VITC data registers */ |
| 94 | #define TVP5150_VITC_DATA_REG5 0xab /* VITC data registers */ |
| 95 | #define TVP5150_VITC_DATA_REG6 0xac /* VITC data registers */ |
| 96 | #define TVP5150_VITC_DATA_REG7 0xad /* VITC data registers */ |
| 97 | #define TVP5150_VITC_DATA_REG8 0xae /* VITC data registers */ |
| 98 | #define TVP5150_VITC_DATA_REG9 0xaf /* VITC data registers */ |
| 99 | #define TVP5150_VBI_FIFO_READ_DATA 0xb0 /* VBI FIFO read data */ |
| 100 | #define TVP5150_TELETEXT_FIL_1_1 0xb1 /* Teletext filter 1 */ |
| 101 | #define TVP5150_TELETEXT_FIL_1_2 0xb2 /* Teletext filter 1 */ |
| 102 | #define TVP5150_TELETEXT_FIL_1_3 0xb3 /* Teletext filter 1 */ |
| 103 | #define TVP5150_TELETEXT_FIL_1_4 0xb4 /* Teletext filter 1 */ |
| 104 | #define TVP5150_TELETEXT_FIL_1_5 0xb5 /* Teletext filter 1 */ |
| 105 | #define TVP5150_TELETEXT_FIL_2_1 0xb6 /* Teletext filter 2 */ |
| 106 | #define TVP5150_TELETEXT_FIL_2_2 0xb7 /* Teletext filter 2 */ |
| 107 | #define TVP5150_TELETEXT_FIL_2_3 0xb8 /* Teletext filter 2 */ |
| 108 | #define TVP5150_TELETEXT_FIL_2_4 0xb9 /* Teletext filter 2 */ |
| 109 | #define TVP5150_TELETEXT_FIL_2_5 0xba /* Teletext filter 2 */ |
| 110 | #define TVP5150_TELETEXT_FIL_ENA 0xbb /* Teletext filter enable */ |
| 111 | /* Reserved BCh-BFh */ |
| 112 | #define TVP5150_INT_STATUS_REG_A 0xc0 /* Interrupt status register A */ |
| 113 | #define TVP5150_INT_ENABLE_REG_A 0xc1 /* Interrupt enable register A */ |
| 114 | #define TVP5150_INT_CONF 0xc2 /* Interrupt configuration */ |
| 115 | #define TVP5150_VDP_CONF_RAM_DATA 0xc3 /* VDP configuration RAM data */ |
| 116 | #define TVP5150_CONF_RAM_ADDR_LOW 0xc4 /* Configuration RAM address low byte */ |
| 117 | #define TVP5150_CONF_RAM_ADDR_HIGH 0xc5 /* Configuration RAM address high byte */ |
| 118 | #define TVP5150_VDP_STATUS_REG 0xc6 /* VDP status register */ |
| 119 | #define TVP5150_FIFO_WORD_COUNT 0xc7 /* FIFO word count */ |
| 120 | #define TVP5150_FIFO_INT_THRESHOLD 0xc8 /* FIFO interrupt threshold */ |
| 121 | #define TVP5150_FIFO_RESET 0xc9 /* FIFO reset */ |
| 122 | #define TVP5150_LINE_NUMBER_INT 0xca /* Line number interrupt */ |
| 123 | #define TVP5150_PIX_ALIGN_REG_LOW 0xcb /* Pixel alignment register low byte */ |
| 124 | #define TVP5150_PIX_ALIGN_REG_HIGH 0xcc /* Pixel alignment register high byte */ |
| 125 | #define TVP5150_FIFO_OUT_CTRL 0xcd /* FIFO output control */ |
| 126 | /* Reserved CEh */ |
| 127 | #define TVP5150_FULL_FIELD_ENA_1 0xcf /* Full field enable 1 */ |
| 128 | #define TVP5150_FULL_FIELD_ENA_2 0xd0 /* Full field enable 2 */ |
| 129 | #define TVP5150_LINE_MODE_REG_1 0xd1 /* Line mode registers */ |
| 130 | #define TVP5150_LINE_MODE_REG_2 0xd2 /* Line mode registers */ |
| 131 | #define TVP5150_LINE_MODE_REG_3 0xd3 /* Line mode registers */ |
| 132 | #define TVP5150_LINE_MODE_REG_4 0xd4 /* Line mode registers */ |
| 133 | #define TVP5150_LINE_MODE_REG_5 0xd5 /* Line mode registers */ |
| 134 | #define TVP5150_LINE_MODE_REG_6 0xd6 /* Line mode registers */ |
| 135 | #define TVP5150_LINE_MODE_REG_7 0xd7 /* Line mode registers */ |
| 136 | #define TVP5150_LINE_MODE_REG_8 0xd8 /* Line mode registers */ |
| 137 | #define TVP5150_LINE_MODE_REG_9 0xd9 /* Line mode registers */ |
| 138 | #define TVP5150_LINE_MODE_REG_10 0xda /* Line mode registers */ |
| 139 | #define TVP5150_LINE_MODE_REG_11 0xdb /* Line mode registers */ |
| 140 | #define TVP5150_LINE_MODE_REG_12 0xdc /* Line mode registers */ |
| 141 | #define TVP5150_LINE_MODE_REG_13 0xdd /* Line mode registers */ |
| 142 | #define TVP5150_LINE_MODE_REG_14 0xde /* Line mode registers */ |
| 143 | #define TVP5150_LINE_MODE_REG_15 0xdf /* Line mode registers */ |
| 144 | #define TVP5150_LINE_MODE_REG_16 0xe0 /* Line mode registers */ |
| 145 | #define TVP5150_LINE_MODE_REG_17 0xe1 /* Line mode registers */ |
| 146 | #define TVP5150_LINE_MODE_REG_18 0xe2 /* Line mode registers */ |
| 147 | #define TVP5150_LINE_MODE_REG_19 0xe3 /* Line mode registers */ |
| 148 | #define TVP5150_LINE_MODE_REG_20 0xe4 /* Line mode registers */ |
| 149 | #define TVP5150_LINE_MODE_REG_21 0xe5 /* Line mode registers */ |
| 150 | #define TVP5150_LINE_MODE_REG_22 0xe6 /* Line mode registers */ |
| 151 | #define TVP5150_LINE_MODE_REG_23 0xe7 /* Line mode registers */ |
| 152 | #define TVP5150_LINE_MODE_REG_24 0xe8 /* Line mode registers */ |
| 153 | #define TVP5150_LINE_MODE_REG_25 0xe9 /* Line mode registers */ |
| 154 | #define TVP5150_LINE_MODE_REG_27 0xea /* Line mode registers */ |
| 155 | #define TVP5150_LINE_MODE_REG_28 0xeb /* Line mode registers */ |
| 156 | #define TVP5150_LINE_MODE_REG_29 0xec /* Line mode registers */ |
| 157 | #define TVP5150_LINE_MODE_REG_30 0xed /* Line mode registers */ |
| 158 | #define TVP5150_LINE_MODE_REG_31 0xee /* Line mode registers */ |
| 159 | #define TVP5150_LINE_MODE_REG_32 0xef /* Line mode registers */ |
| 160 | #define TVP5150_LINE_MODE_REG_33 0xf0 /* Line mode registers */ |
| 161 | #define TVP5150_LINE_MODE_REG_34 0xf1 /* Line mode registers */ |
| 162 | #define TVP5150_LINE_MODE_REG_35 0xf2 /* Line mode registers */ |
| 163 | #define TVP5150_LINE_MODE_REG_36 0xf3 /* Line mode registers */ |
| 164 | #define TVP5150_LINE_MODE_REG_37 0xf4 /* Line mode registers */ |
| 165 | #define TVP5150_LINE_MODE_REG_38 0xf5 /* Line mode registers */ |
| 166 | #define TVP5150_LINE_MODE_REG_39 0xf6 /* Line mode registers */ |
| 167 | #define TVP5150_LINE_MODE_REG_40 0xf7 /* Line mode registers */ |
| 168 | #define TVP5150_LINE_MODE_REG_41 0xf8 /* Line mode registers */ |
| 169 | #define TVP5150_LINE_MODE_REG_42 0xf9 /* Line mode registers */ |
| 170 | #define TVP5150_LINE_MODE_REG_43 0xfa /* Line mode registers */ |
| 171 | #define TVP5150_LINE_MODE_REG_44 0xfb /* Line mode registers */ |
| 172 | #define TVP5150_FULL_FIELD_MODE_REG 0xfc /* Full field mode register */ |
| 173 | /* Reserved FDh-FFh */ |