Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2005-2011 Atheros Communications Inc. |
| 3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. |
| 4 | * |
| 5 | * Permission to use, copy, modify, and/or distribute this software for any |
| 6 | * purpose with or without fee is hereby granted, provided that the above |
| 7 | * copyright notice and this permission notice appear in all copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 16 | */ |
| 17 | |
| 18 | #include "hif.h" |
| 19 | #include "pci.h" |
| 20 | #include "ce.h" |
| 21 | #include "debug.h" |
| 22 | |
| 23 | /* |
| 24 | * Support for Copy Engine hardware, which is mainly used for |
| 25 | * communication between Host and Target over a PCIe interconnect. |
| 26 | */ |
| 27 | |
| 28 | /* |
| 29 | * A single CopyEngine (CE) comprises two "rings": |
| 30 | * a source ring |
| 31 | * a destination ring |
| 32 | * |
| 33 | * Each ring consists of a number of descriptors which specify |
| 34 | * an address, length, and meta-data. |
| 35 | * |
| 36 | * Typically, one side of the PCIe interconnect (Host or Target) |
| 37 | * controls one ring and the other side controls the other ring. |
| 38 | * The source side chooses when to initiate a transfer and it |
| 39 | * chooses what to send (buffer address, length). The destination |
| 40 | * side keeps a supply of "anonymous receive buffers" available and |
| 41 | * it handles incoming data as it arrives (when the destination |
| 42 | * recieves an interrupt). |
| 43 | * |
| 44 | * The sender may send a simple buffer (address/length) or it may |
| 45 | * send a small list of buffers. When a small list is sent, hardware |
| 46 | * "gathers" these and they end up in a single destination buffer |
| 47 | * with a single interrupt. |
| 48 | * |
| 49 | * There are several "contexts" managed by this layer -- more, it |
| 50 | * may seem -- than should be needed. These are provided mainly for |
| 51 | * maximum flexibility and especially to facilitate a simpler HIF |
| 52 | * implementation. There are per-CopyEngine recv, send, and watermark |
| 53 | * contexts. These are supplied by the caller when a recv, send, |
| 54 | * or watermark handler is established and they are echoed back to |
| 55 | * the caller when the respective callbacks are invoked. There is |
| 56 | * also a per-transfer context supplied by the caller when a buffer |
| 57 | * (or sendlist) is sent and when a buffer is enqueued for recv. |
| 58 | * These per-transfer contexts are echoed back to the caller when |
| 59 | * the buffer is sent/received. |
| 60 | */ |
| 61 | |
| 62 | static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar, |
| 63 | u32 ce_ctrl_addr, |
| 64 | unsigned int n) |
| 65 | { |
| 66 | ath10k_pci_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n); |
| 67 | } |
| 68 | |
| 69 | static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar, |
| 70 | u32 ce_ctrl_addr) |
| 71 | { |
| 72 | return ath10k_pci_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS); |
| 73 | } |
| 74 | |
| 75 | static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar, |
| 76 | u32 ce_ctrl_addr, |
| 77 | unsigned int n) |
| 78 | { |
Bartosz Markowski | 57a8930 | 2013-08-07 15:17:45 +0200 | [diff] [blame] | 79 | ath10k_pci_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 80 | } |
| 81 | |
| 82 | static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar, |
| 83 | u32 ce_ctrl_addr) |
| 84 | { |
| 85 | return ath10k_pci_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS); |
| 86 | } |
| 87 | |
| 88 | static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar, |
| 89 | u32 ce_ctrl_addr) |
| 90 | { |
| 91 | return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS); |
| 92 | } |
| 93 | |
| 94 | static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar, |
| 95 | u32 ce_ctrl_addr, |
| 96 | unsigned int addr) |
| 97 | { |
| 98 | ath10k_pci_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr); |
| 99 | } |
| 100 | |
| 101 | static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar, |
| 102 | u32 ce_ctrl_addr, |
| 103 | unsigned int n) |
| 104 | { |
| 105 | ath10k_pci_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n); |
| 106 | } |
| 107 | |
| 108 | static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar, |
| 109 | u32 ce_ctrl_addr, |
| 110 | unsigned int n) |
| 111 | { |
| 112 | u32 ctrl1_addr = ath10k_pci_read32((ar), |
| 113 | (ce_ctrl_addr) + CE_CTRL1_ADDRESS); |
| 114 | |
| 115 | ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS, |
| 116 | (ctrl1_addr & ~CE_CTRL1_DMAX_LENGTH_MASK) | |
| 117 | CE_CTRL1_DMAX_LENGTH_SET(n)); |
| 118 | } |
| 119 | |
| 120 | static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar, |
| 121 | u32 ce_ctrl_addr, |
| 122 | unsigned int n) |
| 123 | { |
| 124 | u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS); |
| 125 | |
| 126 | ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS, |
| 127 | (ctrl1_addr & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | |
| 128 | CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n)); |
| 129 | } |
| 130 | |
| 131 | static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar, |
| 132 | u32 ce_ctrl_addr, |
| 133 | unsigned int n) |
| 134 | { |
| 135 | u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS); |
| 136 | |
| 137 | ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS, |
| 138 | (ctrl1_addr & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | |
| 139 | CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n)); |
| 140 | } |
| 141 | |
| 142 | static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar, |
| 143 | u32 ce_ctrl_addr) |
| 144 | { |
| 145 | return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS); |
| 146 | } |
| 147 | |
| 148 | static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar, |
| 149 | u32 ce_ctrl_addr, |
| 150 | u32 addr) |
| 151 | { |
| 152 | ath10k_pci_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr); |
| 153 | } |
| 154 | |
| 155 | static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar, |
| 156 | u32 ce_ctrl_addr, |
| 157 | unsigned int n) |
| 158 | { |
| 159 | ath10k_pci_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n); |
| 160 | } |
| 161 | |
| 162 | static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar, |
| 163 | u32 ce_ctrl_addr, |
| 164 | unsigned int n) |
| 165 | { |
| 166 | u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS); |
| 167 | |
| 168 | ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS, |
| 169 | (addr & ~SRC_WATERMARK_HIGH_MASK) | |
| 170 | SRC_WATERMARK_HIGH_SET(n)); |
| 171 | } |
| 172 | |
| 173 | static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar, |
| 174 | u32 ce_ctrl_addr, |
| 175 | unsigned int n) |
| 176 | { |
| 177 | u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS); |
| 178 | |
| 179 | ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS, |
| 180 | (addr & ~SRC_WATERMARK_LOW_MASK) | |
| 181 | SRC_WATERMARK_LOW_SET(n)); |
| 182 | } |
| 183 | |
| 184 | static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar, |
| 185 | u32 ce_ctrl_addr, |
| 186 | unsigned int n) |
| 187 | { |
| 188 | u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS); |
| 189 | |
| 190 | ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS, |
| 191 | (addr & ~DST_WATERMARK_HIGH_MASK) | |
| 192 | DST_WATERMARK_HIGH_SET(n)); |
| 193 | } |
| 194 | |
| 195 | static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar, |
| 196 | u32 ce_ctrl_addr, |
| 197 | unsigned int n) |
| 198 | { |
| 199 | u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS); |
| 200 | |
| 201 | ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS, |
| 202 | (addr & ~DST_WATERMARK_LOW_MASK) | |
| 203 | DST_WATERMARK_LOW_SET(n)); |
| 204 | } |
| 205 | |
| 206 | static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar, |
| 207 | u32 ce_ctrl_addr) |
| 208 | { |
| 209 | u32 host_ie_addr = ath10k_pci_read32(ar, |
| 210 | ce_ctrl_addr + HOST_IE_ADDRESS); |
| 211 | |
| 212 | ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS, |
| 213 | host_ie_addr | HOST_IE_COPY_COMPLETE_MASK); |
| 214 | } |
| 215 | |
| 216 | static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar, |
| 217 | u32 ce_ctrl_addr) |
| 218 | { |
| 219 | u32 host_ie_addr = ath10k_pci_read32(ar, |
| 220 | ce_ctrl_addr + HOST_IE_ADDRESS); |
| 221 | |
| 222 | ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS, |
| 223 | host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK); |
| 224 | } |
| 225 | |
| 226 | static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar, |
| 227 | u32 ce_ctrl_addr) |
| 228 | { |
| 229 | u32 host_ie_addr = ath10k_pci_read32(ar, |
| 230 | ce_ctrl_addr + HOST_IE_ADDRESS); |
| 231 | |
| 232 | ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS, |
| 233 | host_ie_addr & ~CE_WATERMARK_MASK); |
| 234 | } |
| 235 | |
| 236 | static inline void ath10k_ce_error_intr_enable(struct ath10k *ar, |
| 237 | u32 ce_ctrl_addr) |
| 238 | { |
| 239 | u32 misc_ie_addr = ath10k_pci_read32(ar, |
| 240 | ce_ctrl_addr + MISC_IE_ADDRESS); |
| 241 | |
| 242 | ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS, |
| 243 | misc_ie_addr | CE_ERROR_MASK); |
| 244 | } |
| 245 | |
| 246 | static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar, |
| 247 | u32 ce_ctrl_addr, |
| 248 | unsigned int mask) |
| 249 | { |
| 250 | ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask); |
| 251 | } |
| 252 | |
| 253 | |
| 254 | /* |
| 255 | * Guts of ath10k_ce_send, used by both ath10k_ce_send and |
| 256 | * ath10k_ce_sendlist_send. |
| 257 | * The caller takes responsibility for any needed locking. |
| 258 | */ |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 259 | static int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 260 | void *per_transfer_context, |
| 261 | u32 buffer, |
| 262 | unsigned int nbytes, |
| 263 | unsigned int transfer_id, |
| 264 | unsigned int flags) |
| 265 | { |
| 266 | struct ath10k *ar = ce_state->ar; |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 267 | struct ath10k_ce_ring *src_ring = ce_state->src_ring; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 268 | struct ce_desc *desc, *sdesc; |
| 269 | unsigned int nentries_mask = src_ring->nentries_mask; |
| 270 | unsigned int sw_index = src_ring->sw_index; |
| 271 | unsigned int write_index = src_ring->write_index; |
| 272 | u32 ctrl_addr = ce_state->ctrl_addr; |
| 273 | u32 desc_flags = 0; |
| 274 | int ret = 0; |
| 275 | |
| 276 | if (nbytes > ce_state->src_sz_max) |
| 277 | ath10k_warn("%s: send more we can (nbytes: %d, max: %d)\n", |
| 278 | __func__, nbytes, ce_state->src_sz_max); |
| 279 | |
| 280 | ath10k_pci_wake(ar); |
| 281 | |
| 282 | if (unlikely(CE_RING_DELTA(nentries_mask, |
| 283 | write_index, sw_index - 1) <= 0)) { |
| 284 | ret = -EIO; |
| 285 | goto exit; |
| 286 | } |
| 287 | |
| 288 | desc = CE_SRC_RING_TO_DESC(src_ring->base_addr_owner_space, |
| 289 | write_index); |
| 290 | sdesc = CE_SRC_RING_TO_DESC(src_ring->shadow_base, write_index); |
| 291 | |
| 292 | desc_flags |= SM(transfer_id, CE_DESC_FLAGS_META_DATA); |
| 293 | |
| 294 | if (flags & CE_SEND_FLAG_GATHER) |
| 295 | desc_flags |= CE_DESC_FLAGS_GATHER; |
| 296 | if (flags & CE_SEND_FLAG_BYTE_SWAP) |
| 297 | desc_flags |= CE_DESC_FLAGS_BYTE_SWAP; |
| 298 | |
| 299 | sdesc->addr = __cpu_to_le32(buffer); |
| 300 | sdesc->nbytes = __cpu_to_le16(nbytes); |
| 301 | sdesc->flags = __cpu_to_le16(desc_flags); |
| 302 | |
| 303 | *desc = *sdesc; |
| 304 | |
| 305 | src_ring->per_transfer_context[write_index] = per_transfer_context; |
| 306 | |
| 307 | /* Update Source Ring Write Index */ |
| 308 | write_index = CE_RING_IDX_INCR(nentries_mask, write_index); |
| 309 | |
| 310 | /* WORKAROUND */ |
| 311 | if (!(flags & CE_SEND_FLAG_GATHER)) |
| 312 | ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, write_index); |
| 313 | |
| 314 | src_ring->write_index = write_index; |
| 315 | exit: |
| 316 | ath10k_pci_sleep(ar); |
| 317 | return ret; |
| 318 | } |
| 319 | |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 320 | int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 321 | void *per_transfer_context, |
| 322 | u32 buffer, |
| 323 | unsigned int nbytes, |
| 324 | unsigned int transfer_id, |
| 325 | unsigned int flags) |
| 326 | { |
| 327 | struct ath10k *ar = ce_state->ar; |
| 328 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 329 | int ret; |
| 330 | |
| 331 | spin_lock_bh(&ar_pci->ce_lock); |
| 332 | ret = ath10k_ce_send_nolock(ce_state, per_transfer_context, |
| 333 | buffer, nbytes, transfer_id, flags); |
| 334 | spin_unlock_bh(&ar_pci->ce_lock); |
| 335 | |
| 336 | return ret; |
| 337 | } |
| 338 | |
| 339 | void ath10k_ce_sendlist_buf_add(struct ce_sendlist *sendlist, u32 buffer, |
| 340 | unsigned int nbytes, u32 flags) |
| 341 | { |
| 342 | unsigned int num_items = sendlist->num_items; |
| 343 | struct ce_sendlist_item *item; |
| 344 | |
| 345 | item = &sendlist->item[num_items]; |
| 346 | item->data = buffer; |
| 347 | item->u.nbytes = nbytes; |
| 348 | item->flags = flags; |
| 349 | sendlist->num_items++; |
| 350 | } |
| 351 | |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 352 | int ath10k_ce_sendlist_send(struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 353 | void *per_transfer_context, |
| 354 | struct ce_sendlist *sendlist, |
| 355 | unsigned int transfer_id) |
| 356 | { |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 357 | struct ath10k_ce_ring *src_ring = ce_state->src_ring; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 358 | struct ce_sendlist_item *item; |
| 359 | struct ath10k *ar = ce_state->ar; |
| 360 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 361 | unsigned int nentries_mask = src_ring->nentries_mask; |
| 362 | unsigned int num_items = sendlist->num_items; |
| 363 | unsigned int sw_index; |
| 364 | unsigned int write_index; |
| 365 | int i, delta, ret = -ENOMEM; |
| 366 | |
| 367 | spin_lock_bh(&ar_pci->ce_lock); |
| 368 | |
| 369 | sw_index = src_ring->sw_index; |
| 370 | write_index = src_ring->write_index; |
| 371 | |
| 372 | delta = CE_RING_DELTA(nentries_mask, write_index, sw_index - 1); |
| 373 | |
| 374 | if (delta >= num_items) { |
| 375 | /* |
| 376 | * Handle all but the last item uniformly. |
| 377 | */ |
| 378 | for (i = 0; i < num_items - 1; i++) { |
| 379 | item = &sendlist->item[i]; |
| 380 | ret = ath10k_ce_send_nolock(ce_state, |
| 381 | CE_SENDLIST_ITEM_CTXT, |
| 382 | (u32) item->data, |
| 383 | item->u.nbytes, transfer_id, |
| 384 | item->flags | |
| 385 | CE_SEND_FLAG_GATHER); |
| 386 | if (ret) |
| 387 | ath10k_warn("CE send failed for item: %d\n", i); |
| 388 | } |
| 389 | /* |
| 390 | * Provide valid context pointer for final item. |
| 391 | */ |
| 392 | item = &sendlist->item[i]; |
| 393 | ret = ath10k_ce_send_nolock(ce_state, per_transfer_context, |
| 394 | (u32) item->data, item->u.nbytes, |
| 395 | transfer_id, item->flags); |
| 396 | if (ret) |
| 397 | ath10k_warn("CE send failed for last item: %d\n", i); |
| 398 | } |
| 399 | |
| 400 | spin_unlock_bh(&ar_pci->ce_lock); |
| 401 | |
| 402 | return ret; |
| 403 | } |
| 404 | |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 405 | int ath10k_ce_recv_buf_enqueue(struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 406 | void *per_recv_context, |
| 407 | u32 buffer) |
| 408 | { |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 409 | struct ath10k_ce_ring *dest_ring = ce_state->dest_ring; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 410 | u32 ctrl_addr = ce_state->ctrl_addr; |
| 411 | struct ath10k *ar = ce_state->ar; |
| 412 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 413 | unsigned int nentries_mask = dest_ring->nentries_mask; |
| 414 | unsigned int write_index; |
| 415 | unsigned int sw_index; |
| 416 | int ret; |
| 417 | |
| 418 | spin_lock_bh(&ar_pci->ce_lock); |
| 419 | write_index = dest_ring->write_index; |
| 420 | sw_index = dest_ring->sw_index; |
| 421 | |
| 422 | ath10k_pci_wake(ar); |
| 423 | |
| 424 | if (CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) > 0) { |
| 425 | struct ce_desc *base = dest_ring->base_addr_owner_space; |
| 426 | struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index); |
| 427 | |
| 428 | /* Update destination descriptor */ |
| 429 | desc->addr = __cpu_to_le32(buffer); |
| 430 | desc->nbytes = 0; |
| 431 | |
| 432 | dest_ring->per_transfer_context[write_index] = |
| 433 | per_recv_context; |
| 434 | |
| 435 | /* Update Destination Ring Write Index */ |
| 436 | write_index = CE_RING_IDX_INCR(nentries_mask, write_index); |
| 437 | ath10k_ce_dest_ring_write_index_set(ar, ctrl_addr, write_index); |
| 438 | dest_ring->write_index = write_index; |
| 439 | ret = 0; |
| 440 | } else { |
| 441 | ret = -EIO; |
| 442 | } |
| 443 | ath10k_pci_sleep(ar); |
| 444 | spin_unlock_bh(&ar_pci->ce_lock); |
| 445 | |
| 446 | return ret; |
| 447 | } |
| 448 | |
| 449 | /* |
| 450 | * Guts of ath10k_ce_completed_recv_next. |
| 451 | * The caller takes responsibility for any necessary locking. |
| 452 | */ |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 453 | static int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 454 | void **per_transfer_contextp, |
| 455 | u32 *bufferp, |
| 456 | unsigned int *nbytesp, |
| 457 | unsigned int *transfer_idp, |
| 458 | unsigned int *flagsp) |
| 459 | { |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 460 | struct ath10k_ce_ring *dest_ring = ce_state->dest_ring; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 461 | unsigned int nentries_mask = dest_ring->nentries_mask; |
| 462 | unsigned int sw_index = dest_ring->sw_index; |
| 463 | |
| 464 | struct ce_desc *base = dest_ring->base_addr_owner_space; |
| 465 | struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, sw_index); |
| 466 | struct ce_desc sdesc; |
| 467 | u16 nbytes; |
| 468 | |
| 469 | /* Copy in one go for performance reasons */ |
| 470 | sdesc = *desc; |
| 471 | |
| 472 | nbytes = __le16_to_cpu(sdesc.nbytes); |
| 473 | if (nbytes == 0) { |
| 474 | /* |
| 475 | * This closes a relatively unusual race where the Host |
| 476 | * sees the updated DRRI before the update to the |
| 477 | * corresponding descriptor has completed. We treat this |
| 478 | * as a descriptor that is not yet done. |
| 479 | */ |
| 480 | return -EIO; |
| 481 | } |
| 482 | |
| 483 | desc->nbytes = 0; |
| 484 | |
| 485 | /* Return data from completed destination descriptor */ |
| 486 | *bufferp = __le32_to_cpu(sdesc.addr); |
| 487 | *nbytesp = nbytes; |
| 488 | *transfer_idp = MS(__le16_to_cpu(sdesc.flags), CE_DESC_FLAGS_META_DATA); |
| 489 | |
| 490 | if (__le16_to_cpu(sdesc.flags) & CE_DESC_FLAGS_BYTE_SWAP) |
| 491 | *flagsp = CE_RECV_FLAG_SWAPPED; |
| 492 | else |
| 493 | *flagsp = 0; |
| 494 | |
| 495 | if (per_transfer_contextp) |
| 496 | *per_transfer_contextp = |
| 497 | dest_ring->per_transfer_context[sw_index]; |
| 498 | |
| 499 | /* sanity */ |
| 500 | dest_ring->per_transfer_context[sw_index] = NULL; |
| 501 | |
| 502 | /* Update sw_index */ |
| 503 | sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); |
| 504 | dest_ring->sw_index = sw_index; |
| 505 | |
| 506 | return 0; |
| 507 | } |
| 508 | |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 509 | int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 510 | void **per_transfer_contextp, |
| 511 | u32 *bufferp, |
| 512 | unsigned int *nbytesp, |
| 513 | unsigned int *transfer_idp, |
| 514 | unsigned int *flagsp) |
| 515 | { |
| 516 | struct ath10k *ar = ce_state->ar; |
| 517 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 518 | int ret; |
| 519 | |
| 520 | spin_lock_bh(&ar_pci->ce_lock); |
| 521 | ret = ath10k_ce_completed_recv_next_nolock(ce_state, |
| 522 | per_transfer_contextp, |
| 523 | bufferp, nbytesp, |
| 524 | transfer_idp, flagsp); |
| 525 | spin_unlock_bh(&ar_pci->ce_lock); |
| 526 | |
| 527 | return ret; |
| 528 | } |
| 529 | |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 530 | int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 531 | void **per_transfer_contextp, |
| 532 | u32 *bufferp) |
| 533 | { |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 534 | struct ath10k_ce_ring *dest_ring; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 535 | unsigned int nentries_mask; |
| 536 | unsigned int sw_index; |
| 537 | unsigned int write_index; |
| 538 | int ret; |
| 539 | struct ath10k *ar; |
| 540 | struct ath10k_pci *ar_pci; |
| 541 | |
| 542 | dest_ring = ce_state->dest_ring; |
| 543 | |
| 544 | if (!dest_ring) |
| 545 | return -EIO; |
| 546 | |
| 547 | ar = ce_state->ar; |
| 548 | ar_pci = ath10k_pci_priv(ar); |
| 549 | |
| 550 | spin_lock_bh(&ar_pci->ce_lock); |
| 551 | |
| 552 | nentries_mask = dest_ring->nentries_mask; |
| 553 | sw_index = dest_ring->sw_index; |
| 554 | write_index = dest_ring->write_index; |
| 555 | if (write_index != sw_index) { |
| 556 | struct ce_desc *base = dest_ring->base_addr_owner_space; |
| 557 | struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, sw_index); |
| 558 | |
| 559 | /* Return data from completed destination descriptor */ |
| 560 | *bufferp = __le32_to_cpu(desc->addr); |
| 561 | |
| 562 | if (per_transfer_contextp) |
| 563 | *per_transfer_contextp = |
| 564 | dest_ring->per_transfer_context[sw_index]; |
| 565 | |
| 566 | /* sanity */ |
| 567 | dest_ring->per_transfer_context[sw_index] = NULL; |
| 568 | |
| 569 | /* Update sw_index */ |
| 570 | sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); |
| 571 | dest_ring->sw_index = sw_index; |
| 572 | ret = 0; |
| 573 | } else { |
| 574 | ret = -EIO; |
| 575 | } |
| 576 | |
| 577 | spin_unlock_bh(&ar_pci->ce_lock); |
| 578 | |
| 579 | return ret; |
| 580 | } |
| 581 | |
| 582 | /* |
| 583 | * Guts of ath10k_ce_completed_send_next. |
| 584 | * The caller takes responsibility for any necessary locking. |
| 585 | */ |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 586 | static int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 587 | void **per_transfer_contextp, |
| 588 | u32 *bufferp, |
| 589 | unsigned int *nbytesp, |
| 590 | unsigned int *transfer_idp) |
| 591 | { |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 592 | struct ath10k_ce_ring *src_ring = ce_state->src_ring; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 593 | u32 ctrl_addr = ce_state->ctrl_addr; |
| 594 | struct ath10k *ar = ce_state->ar; |
| 595 | unsigned int nentries_mask = src_ring->nentries_mask; |
| 596 | unsigned int sw_index = src_ring->sw_index; |
Kalle Valo | a40d3e4 | 2013-09-01 10:02:00 +0300 | [diff] [blame^] | 597 | struct ce_desc *sdesc, *sbase; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 598 | unsigned int read_index; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 599 | |
| 600 | if (src_ring->hw_index == sw_index) { |
| 601 | /* |
| 602 | * The SW completion index has caught up with the cached |
| 603 | * version of the HW completion index. |
| 604 | * Update the cached HW completion index to see whether |
| 605 | * the SW has really caught up to the HW, or if the cached |
| 606 | * value of the HW index has become stale. |
| 607 | */ |
| 608 | ath10k_pci_wake(ar); |
| 609 | src_ring->hw_index = |
| 610 | ath10k_ce_src_ring_read_index_get(ar, ctrl_addr); |
Michal Kazior | 432358e | 2013-07-31 10:55:11 +0200 | [diff] [blame] | 611 | src_ring->hw_index &= nentries_mask; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 612 | ath10k_pci_sleep(ar); |
| 613 | } |
Kalle Valo | a40d3e4 | 2013-09-01 10:02:00 +0300 | [diff] [blame^] | 614 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 615 | read_index = src_ring->hw_index; |
| 616 | |
Kalle Valo | a40d3e4 | 2013-09-01 10:02:00 +0300 | [diff] [blame^] | 617 | if ((read_index == sw_index) || (read_index == 0xffffffff)) |
| 618 | return -EIO; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 619 | |
Kalle Valo | a40d3e4 | 2013-09-01 10:02:00 +0300 | [diff] [blame^] | 620 | sbase = src_ring->shadow_base; |
| 621 | sdesc = CE_SRC_RING_TO_DESC(sbase, sw_index); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 622 | |
Kalle Valo | a40d3e4 | 2013-09-01 10:02:00 +0300 | [diff] [blame^] | 623 | /* Return data from completed source descriptor */ |
| 624 | *bufferp = __le32_to_cpu(sdesc->addr); |
| 625 | *nbytesp = __le16_to_cpu(sdesc->nbytes); |
| 626 | *transfer_idp = MS(__le16_to_cpu(sdesc->flags), |
| 627 | CE_DESC_FLAGS_META_DATA); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 628 | |
Kalle Valo | a40d3e4 | 2013-09-01 10:02:00 +0300 | [diff] [blame^] | 629 | if (per_transfer_contextp) |
| 630 | *per_transfer_contextp = |
| 631 | src_ring->per_transfer_context[sw_index]; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 632 | |
Kalle Valo | a40d3e4 | 2013-09-01 10:02:00 +0300 | [diff] [blame^] | 633 | /* sanity */ |
| 634 | src_ring->per_transfer_context[sw_index] = NULL; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 635 | |
Kalle Valo | a40d3e4 | 2013-09-01 10:02:00 +0300 | [diff] [blame^] | 636 | /* Update sw_index */ |
| 637 | sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); |
| 638 | src_ring->sw_index = sw_index; |
| 639 | |
| 640 | return 0; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 641 | } |
| 642 | |
| 643 | /* NB: Modeled after ath10k_ce_completed_send_next */ |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 644 | int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 645 | void **per_transfer_contextp, |
| 646 | u32 *bufferp, |
| 647 | unsigned int *nbytesp, |
| 648 | unsigned int *transfer_idp) |
| 649 | { |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 650 | struct ath10k_ce_ring *src_ring; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 651 | unsigned int nentries_mask; |
| 652 | unsigned int sw_index; |
| 653 | unsigned int write_index; |
| 654 | int ret; |
| 655 | struct ath10k *ar; |
| 656 | struct ath10k_pci *ar_pci; |
| 657 | |
| 658 | src_ring = ce_state->src_ring; |
| 659 | |
| 660 | if (!src_ring) |
| 661 | return -EIO; |
| 662 | |
| 663 | ar = ce_state->ar; |
| 664 | ar_pci = ath10k_pci_priv(ar); |
| 665 | |
| 666 | spin_lock_bh(&ar_pci->ce_lock); |
| 667 | |
| 668 | nentries_mask = src_ring->nentries_mask; |
| 669 | sw_index = src_ring->sw_index; |
| 670 | write_index = src_ring->write_index; |
| 671 | |
| 672 | if (write_index != sw_index) { |
| 673 | struct ce_desc *base = src_ring->base_addr_owner_space; |
| 674 | struct ce_desc *desc = CE_SRC_RING_TO_DESC(base, sw_index); |
| 675 | |
| 676 | /* Return data from completed source descriptor */ |
| 677 | *bufferp = __le32_to_cpu(desc->addr); |
| 678 | *nbytesp = __le16_to_cpu(desc->nbytes); |
| 679 | *transfer_idp = MS(__le16_to_cpu(desc->flags), |
| 680 | CE_DESC_FLAGS_META_DATA); |
| 681 | |
| 682 | if (per_transfer_contextp) |
| 683 | *per_transfer_contextp = |
| 684 | src_ring->per_transfer_context[sw_index]; |
| 685 | |
| 686 | /* sanity */ |
| 687 | src_ring->per_transfer_context[sw_index] = NULL; |
| 688 | |
| 689 | /* Update sw_index */ |
| 690 | sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); |
| 691 | src_ring->sw_index = sw_index; |
| 692 | ret = 0; |
| 693 | } else { |
| 694 | ret = -EIO; |
| 695 | } |
| 696 | |
| 697 | spin_unlock_bh(&ar_pci->ce_lock); |
| 698 | |
| 699 | return ret; |
| 700 | } |
| 701 | |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 702 | int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 703 | void **per_transfer_contextp, |
| 704 | u32 *bufferp, |
| 705 | unsigned int *nbytesp, |
| 706 | unsigned int *transfer_idp) |
| 707 | { |
| 708 | struct ath10k *ar = ce_state->ar; |
| 709 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 710 | int ret; |
| 711 | |
| 712 | spin_lock_bh(&ar_pci->ce_lock); |
| 713 | ret = ath10k_ce_completed_send_next_nolock(ce_state, |
| 714 | per_transfer_contextp, |
| 715 | bufferp, nbytesp, |
| 716 | transfer_idp); |
| 717 | spin_unlock_bh(&ar_pci->ce_lock); |
| 718 | |
| 719 | return ret; |
| 720 | } |
| 721 | |
| 722 | /* |
| 723 | * Guts of interrupt handler for per-engine interrupts on a particular CE. |
| 724 | * |
| 725 | * Invokes registered callbacks for recv_complete, |
| 726 | * send_complete, and watermarks. |
| 727 | */ |
| 728 | void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) |
| 729 | { |
| 730 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 731 | struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 732 | u32 ctrl_addr = ce_state->ctrl_addr; |
| 733 | void *transfer_context; |
| 734 | u32 buf; |
| 735 | unsigned int nbytes; |
| 736 | unsigned int id; |
| 737 | unsigned int flags; |
| 738 | |
| 739 | ath10k_pci_wake(ar); |
| 740 | spin_lock_bh(&ar_pci->ce_lock); |
| 741 | |
| 742 | /* Clear the copy-complete interrupts that will be handled here. */ |
| 743 | ath10k_ce_engine_int_status_clear(ar, ctrl_addr, |
| 744 | HOST_IS_COPY_COMPLETE_MASK); |
| 745 | |
| 746 | if (ce_state->recv_cb) { |
| 747 | /* |
| 748 | * Pop completed recv buffers and call the registered |
| 749 | * recv callback for each |
| 750 | */ |
| 751 | while (ath10k_ce_completed_recv_next_nolock(ce_state, |
| 752 | &transfer_context, |
| 753 | &buf, &nbytes, |
| 754 | &id, &flags) == 0) { |
| 755 | spin_unlock_bh(&ar_pci->ce_lock); |
| 756 | ce_state->recv_cb(ce_state, transfer_context, buf, |
| 757 | nbytes, id, flags); |
| 758 | spin_lock_bh(&ar_pci->ce_lock); |
| 759 | } |
| 760 | } |
| 761 | |
| 762 | if (ce_state->send_cb) { |
| 763 | /* |
| 764 | * Pop completed send buffers and call the registered |
| 765 | * send callback for each |
| 766 | */ |
| 767 | while (ath10k_ce_completed_send_next_nolock(ce_state, |
| 768 | &transfer_context, |
| 769 | &buf, |
| 770 | &nbytes, |
| 771 | &id) == 0) { |
| 772 | spin_unlock_bh(&ar_pci->ce_lock); |
| 773 | ce_state->send_cb(ce_state, transfer_context, |
| 774 | buf, nbytes, id); |
| 775 | spin_lock_bh(&ar_pci->ce_lock); |
| 776 | } |
| 777 | } |
| 778 | |
| 779 | /* |
| 780 | * Misc CE interrupts are not being handled, but still need |
| 781 | * to be cleared. |
| 782 | */ |
| 783 | ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK); |
| 784 | |
| 785 | spin_unlock_bh(&ar_pci->ce_lock); |
| 786 | ath10k_pci_sleep(ar); |
| 787 | } |
| 788 | |
| 789 | /* |
| 790 | * Handler for per-engine interrupts on ALL active CEs. |
| 791 | * This is used in cases where the system is sharing a |
| 792 | * single interrput for all CEs |
| 793 | */ |
| 794 | |
| 795 | void ath10k_ce_per_engine_service_any(struct ath10k *ar) |
| 796 | { |
| 797 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 798 | int ce_id; |
| 799 | u32 intr_summary; |
| 800 | |
| 801 | ath10k_pci_wake(ar); |
| 802 | intr_summary = CE_INTERRUPT_SUMMARY(ar); |
| 803 | |
| 804 | for (ce_id = 0; intr_summary && (ce_id < ar_pci->ce_count); ce_id++) { |
| 805 | if (intr_summary & (1 << ce_id)) |
| 806 | intr_summary &= ~(1 << ce_id); |
| 807 | else |
| 808 | /* no intr pending on this CE */ |
| 809 | continue; |
| 810 | |
| 811 | ath10k_ce_per_engine_service(ar, ce_id); |
| 812 | } |
| 813 | |
| 814 | ath10k_pci_sleep(ar); |
| 815 | } |
| 816 | |
| 817 | /* |
| 818 | * Adjust interrupts for the copy complete handler. |
| 819 | * If it's needed for either send or recv, then unmask |
| 820 | * this interrupt; otherwise, mask it. |
| 821 | * |
| 822 | * Called with ce_lock held. |
| 823 | */ |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 824 | static void ath10k_ce_per_engine_handler_adjust(struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 825 | int disable_copy_compl_intr) |
| 826 | { |
| 827 | u32 ctrl_addr = ce_state->ctrl_addr; |
| 828 | struct ath10k *ar = ce_state->ar; |
| 829 | |
| 830 | ath10k_pci_wake(ar); |
| 831 | |
| 832 | if ((!disable_copy_compl_intr) && |
| 833 | (ce_state->send_cb || ce_state->recv_cb)) |
| 834 | ath10k_ce_copy_complete_inter_enable(ar, ctrl_addr); |
| 835 | else |
| 836 | ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr); |
| 837 | |
| 838 | ath10k_ce_watermark_intr_disable(ar, ctrl_addr); |
| 839 | |
| 840 | ath10k_pci_sleep(ar); |
| 841 | } |
| 842 | |
| 843 | void ath10k_ce_disable_interrupts(struct ath10k *ar) |
| 844 | { |
| 845 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 846 | int ce_id; |
| 847 | |
| 848 | ath10k_pci_wake(ar); |
| 849 | for (ce_id = 0; ce_id < ar_pci->ce_count; ce_id++) { |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 850 | struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 851 | u32 ctrl_addr = ce_state->ctrl_addr; |
| 852 | |
| 853 | ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr); |
| 854 | } |
| 855 | ath10k_pci_sleep(ar); |
| 856 | } |
| 857 | |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 858 | void ath10k_ce_send_cb_register(struct ath10k_ce_pipe *ce_state, |
| 859 | void (*send_cb)(struct ath10k_ce_pipe *ce_state, |
| 860 | void *transfer_context, |
| 861 | u32 buffer, |
| 862 | unsigned int nbytes, |
| 863 | unsigned int transfer_id), |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 864 | int disable_interrupts) |
| 865 | { |
| 866 | struct ath10k *ar = ce_state->ar; |
| 867 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 868 | |
| 869 | spin_lock_bh(&ar_pci->ce_lock); |
| 870 | ce_state->send_cb = send_cb; |
| 871 | ath10k_ce_per_engine_handler_adjust(ce_state, disable_interrupts); |
| 872 | spin_unlock_bh(&ar_pci->ce_lock); |
| 873 | } |
| 874 | |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 875 | void ath10k_ce_recv_cb_register(struct ath10k_ce_pipe *ce_state, |
| 876 | void (*recv_cb)(struct ath10k_ce_pipe *ce_state, |
| 877 | void *transfer_context, |
| 878 | u32 buffer, |
| 879 | unsigned int nbytes, |
| 880 | unsigned int transfer_id, |
| 881 | unsigned int flags)) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 882 | { |
| 883 | struct ath10k *ar = ce_state->ar; |
| 884 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 885 | |
| 886 | spin_lock_bh(&ar_pci->ce_lock); |
| 887 | ce_state->recv_cb = recv_cb; |
| 888 | ath10k_ce_per_engine_handler_adjust(ce_state, 0); |
| 889 | spin_unlock_bh(&ar_pci->ce_lock); |
| 890 | } |
| 891 | |
| 892 | static int ath10k_ce_init_src_ring(struct ath10k *ar, |
| 893 | unsigned int ce_id, |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 894 | struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 895 | const struct ce_attr *attr) |
| 896 | { |
| 897 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 898 | struct ath10k_ce_ring *src_ring; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 899 | unsigned int nentries = attr->src_nentries; |
| 900 | unsigned int ce_nbytes; |
| 901 | u32 ctrl_addr = ath10k_ce_base_address(ce_id); |
| 902 | dma_addr_t base_addr; |
| 903 | char *ptr; |
| 904 | |
| 905 | nentries = roundup_pow_of_two(nentries); |
| 906 | |
| 907 | if (ce_state->src_ring) { |
| 908 | WARN_ON(ce_state->src_ring->nentries != nentries); |
| 909 | return 0; |
| 910 | } |
| 911 | |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 912 | ce_nbytes = sizeof(struct ath10k_ce_ring) + (nentries * sizeof(void *)); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 913 | ptr = kzalloc(ce_nbytes, GFP_KERNEL); |
| 914 | if (ptr == NULL) |
| 915 | return -ENOMEM; |
| 916 | |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 917 | ce_state->src_ring = (struct ath10k_ce_ring *)ptr; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 918 | src_ring = ce_state->src_ring; |
| 919 | |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 920 | ptr += sizeof(struct ath10k_ce_ring); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 921 | src_ring->nentries = nentries; |
| 922 | src_ring->nentries_mask = nentries - 1; |
| 923 | |
| 924 | ath10k_pci_wake(ar); |
| 925 | src_ring->sw_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr); |
Michal Kazior | 432358e | 2013-07-31 10:55:11 +0200 | [diff] [blame] | 926 | src_ring->sw_index &= src_ring->nentries_mask; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 927 | src_ring->hw_index = src_ring->sw_index; |
| 928 | |
| 929 | src_ring->write_index = |
| 930 | ath10k_ce_src_ring_write_index_get(ar, ctrl_addr); |
Michal Kazior | 432358e | 2013-07-31 10:55:11 +0200 | [diff] [blame] | 931 | src_ring->write_index &= src_ring->nentries_mask; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 932 | ath10k_pci_sleep(ar); |
| 933 | |
| 934 | src_ring->per_transfer_context = (void **)ptr; |
| 935 | |
| 936 | /* |
| 937 | * Legacy platforms that do not support cache |
| 938 | * coherent DMA are unsupported |
| 939 | */ |
| 940 | src_ring->base_addr_owner_space_unaligned = |
| 941 | pci_alloc_consistent(ar_pci->pdev, |
| 942 | (nentries * sizeof(struct ce_desc) + |
| 943 | CE_DESC_RING_ALIGN), |
| 944 | &base_addr); |
Janusz Dziedzic | 9c5ae69 | 2013-08-09 08:39:13 +0200 | [diff] [blame] | 945 | if (!src_ring->base_addr_owner_space_unaligned) { |
| 946 | kfree(ce_state->src_ring); |
| 947 | ce_state->src_ring = NULL; |
| 948 | return -ENOMEM; |
| 949 | } |
| 950 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 951 | src_ring->base_addr_ce_space_unaligned = base_addr; |
| 952 | |
| 953 | src_ring->base_addr_owner_space = PTR_ALIGN( |
| 954 | src_ring->base_addr_owner_space_unaligned, |
| 955 | CE_DESC_RING_ALIGN); |
| 956 | src_ring->base_addr_ce_space = ALIGN( |
| 957 | src_ring->base_addr_ce_space_unaligned, |
| 958 | CE_DESC_RING_ALIGN); |
| 959 | |
| 960 | /* |
| 961 | * Also allocate a shadow src ring in regular |
| 962 | * mem to use for faster access. |
| 963 | */ |
| 964 | src_ring->shadow_base_unaligned = |
| 965 | kmalloc((nentries * sizeof(struct ce_desc) + |
| 966 | CE_DESC_RING_ALIGN), GFP_KERNEL); |
Janusz Dziedzic | 9c5ae69 | 2013-08-09 08:39:13 +0200 | [diff] [blame] | 967 | if (!src_ring->shadow_base_unaligned) { |
| 968 | pci_free_consistent(ar_pci->pdev, |
| 969 | (nentries * sizeof(struct ce_desc) + |
| 970 | CE_DESC_RING_ALIGN), |
| 971 | src_ring->base_addr_owner_space, |
| 972 | src_ring->base_addr_ce_space); |
| 973 | kfree(ce_state->src_ring); |
| 974 | ce_state->src_ring = NULL; |
| 975 | return -ENOMEM; |
| 976 | } |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 977 | |
| 978 | src_ring->shadow_base = PTR_ALIGN( |
| 979 | src_ring->shadow_base_unaligned, |
| 980 | CE_DESC_RING_ALIGN); |
| 981 | |
| 982 | ath10k_pci_wake(ar); |
| 983 | ath10k_ce_src_ring_base_addr_set(ar, ctrl_addr, |
| 984 | src_ring->base_addr_ce_space); |
| 985 | ath10k_ce_src_ring_size_set(ar, ctrl_addr, nentries); |
| 986 | ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, attr->src_sz_max); |
| 987 | ath10k_ce_src_ring_byte_swap_set(ar, ctrl_addr, 0); |
| 988 | ath10k_ce_src_ring_lowmark_set(ar, ctrl_addr, 0); |
| 989 | ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, nentries); |
| 990 | ath10k_pci_sleep(ar); |
| 991 | |
| 992 | return 0; |
| 993 | } |
| 994 | |
| 995 | static int ath10k_ce_init_dest_ring(struct ath10k *ar, |
| 996 | unsigned int ce_id, |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 997 | struct ath10k_ce_pipe *ce_state, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 998 | const struct ce_attr *attr) |
| 999 | { |
| 1000 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 1001 | struct ath10k_ce_ring *dest_ring; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1002 | unsigned int nentries = attr->dest_nentries; |
| 1003 | unsigned int ce_nbytes; |
| 1004 | u32 ctrl_addr = ath10k_ce_base_address(ce_id); |
| 1005 | dma_addr_t base_addr; |
| 1006 | char *ptr; |
| 1007 | |
| 1008 | nentries = roundup_pow_of_two(nentries); |
| 1009 | |
| 1010 | if (ce_state->dest_ring) { |
| 1011 | WARN_ON(ce_state->dest_ring->nentries != nentries); |
| 1012 | return 0; |
| 1013 | } |
| 1014 | |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 1015 | ce_nbytes = sizeof(struct ath10k_ce_ring) + (nentries * sizeof(void *)); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1016 | ptr = kzalloc(ce_nbytes, GFP_KERNEL); |
| 1017 | if (ptr == NULL) |
| 1018 | return -ENOMEM; |
| 1019 | |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 1020 | ce_state->dest_ring = (struct ath10k_ce_ring *)ptr; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1021 | dest_ring = ce_state->dest_ring; |
| 1022 | |
Michal Kazior | d21fb95 | 2013-08-27 13:08:03 +0200 | [diff] [blame] | 1023 | ptr += sizeof(struct ath10k_ce_ring); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1024 | dest_ring->nentries = nentries; |
| 1025 | dest_ring->nentries_mask = nentries - 1; |
| 1026 | |
| 1027 | ath10k_pci_wake(ar); |
| 1028 | dest_ring->sw_index = ath10k_ce_dest_ring_read_index_get(ar, ctrl_addr); |
Michal Kazior | 432358e | 2013-07-31 10:55:11 +0200 | [diff] [blame] | 1029 | dest_ring->sw_index &= dest_ring->nentries_mask; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1030 | dest_ring->write_index = |
| 1031 | ath10k_ce_dest_ring_write_index_get(ar, ctrl_addr); |
Michal Kazior | 432358e | 2013-07-31 10:55:11 +0200 | [diff] [blame] | 1032 | dest_ring->write_index &= dest_ring->nentries_mask; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1033 | ath10k_pci_sleep(ar); |
| 1034 | |
| 1035 | dest_ring->per_transfer_context = (void **)ptr; |
| 1036 | |
| 1037 | /* |
| 1038 | * Legacy platforms that do not support cache |
| 1039 | * coherent DMA are unsupported |
| 1040 | */ |
| 1041 | dest_ring->base_addr_owner_space_unaligned = |
| 1042 | pci_alloc_consistent(ar_pci->pdev, |
| 1043 | (nentries * sizeof(struct ce_desc) + |
| 1044 | CE_DESC_RING_ALIGN), |
| 1045 | &base_addr); |
Janusz Dziedzic | 9c5ae69 | 2013-08-09 08:39:13 +0200 | [diff] [blame] | 1046 | if (!dest_ring->base_addr_owner_space_unaligned) { |
| 1047 | kfree(ce_state->dest_ring); |
| 1048 | ce_state->dest_ring = NULL; |
| 1049 | return -ENOMEM; |
| 1050 | } |
| 1051 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1052 | dest_ring->base_addr_ce_space_unaligned = base_addr; |
| 1053 | |
| 1054 | /* |
| 1055 | * Correctly initialize memory to 0 to prevent garbage |
| 1056 | * data crashing system when download firmware |
| 1057 | */ |
| 1058 | memset(dest_ring->base_addr_owner_space_unaligned, 0, |
| 1059 | nentries * sizeof(struct ce_desc) + CE_DESC_RING_ALIGN); |
| 1060 | |
| 1061 | dest_ring->base_addr_owner_space = PTR_ALIGN( |
| 1062 | dest_ring->base_addr_owner_space_unaligned, |
| 1063 | CE_DESC_RING_ALIGN); |
| 1064 | dest_ring->base_addr_ce_space = ALIGN( |
| 1065 | dest_ring->base_addr_ce_space_unaligned, |
| 1066 | CE_DESC_RING_ALIGN); |
| 1067 | |
| 1068 | ath10k_pci_wake(ar); |
| 1069 | ath10k_ce_dest_ring_base_addr_set(ar, ctrl_addr, |
| 1070 | dest_ring->base_addr_ce_space); |
| 1071 | ath10k_ce_dest_ring_size_set(ar, ctrl_addr, nentries); |
| 1072 | ath10k_ce_dest_ring_byte_swap_set(ar, ctrl_addr, 0); |
| 1073 | ath10k_ce_dest_ring_lowmark_set(ar, ctrl_addr, 0); |
| 1074 | ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, nentries); |
| 1075 | ath10k_pci_sleep(ar); |
| 1076 | |
| 1077 | return 0; |
| 1078 | } |
| 1079 | |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 1080 | static struct ath10k_ce_pipe *ath10k_ce_init_state(struct ath10k *ar, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1081 | unsigned int ce_id, |
| 1082 | const struct ce_attr *attr) |
| 1083 | { |
| 1084 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 1085 | struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1086 | u32 ctrl_addr = ath10k_ce_base_address(ce_id); |
| 1087 | |
| 1088 | spin_lock_bh(&ar_pci->ce_lock); |
| 1089 | |
Michal Kazior | 39e4086 | 2013-08-27 13:07:58 +0200 | [diff] [blame] | 1090 | ce_state->ar = ar; |
| 1091 | ce_state->id = ce_id; |
| 1092 | ce_state->ctrl_addr = ctrl_addr; |
Michal Kazior | 39e4086 | 2013-08-27 13:07:58 +0200 | [diff] [blame] | 1093 | ce_state->attr_flags = attr->flags; |
| 1094 | ce_state->src_sz_max = attr->src_sz_max; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1095 | |
| 1096 | spin_unlock_bh(&ar_pci->ce_lock); |
| 1097 | |
| 1098 | return ce_state; |
| 1099 | } |
| 1100 | |
| 1101 | /* |
| 1102 | * Initialize a Copy Engine based on caller-supplied attributes. |
| 1103 | * This may be called once to initialize both source and destination |
| 1104 | * rings or it may be called twice for separate source and destination |
| 1105 | * initialization. It may be that only one side or the other is |
| 1106 | * initialized by software/firmware. |
| 1107 | */ |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 1108 | struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1109 | unsigned int ce_id, |
| 1110 | const struct ce_attr *attr) |
| 1111 | { |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 1112 | struct ath10k_ce_pipe *ce_state; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1113 | u32 ctrl_addr = ath10k_ce_base_address(ce_id); |
Michal Kazior | ba7ee55 | 2013-08-13 07:54:57 +0200 | [diff] [blame] | 1114 | int ret; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1115 | |
| 1116 | ce_state = ath10k_ce_init_state(ar, ce_id, attr); |
| 1117 | if (!ce_state) { |
| 1118 | ath10k_err("Failed to initialize CE state for ID: %d\n", ce_id); |
| 1119 | return NULL; |
| 1120 | } |
| 1121 | |
| 1122 | if (attr->src_nentries) { |
Michal Kazior | ba7ee55 | 2013-08-13 07:54:57 +0200 | [diff] [blame] | 1123 | ret = ath10k_ce_init_src_ring(ar, ce_id, ce_state, attr); |
| 1124 | if (ret) { |
| 1125 | ath10k_err("Failed to initialize CE src ring for ID: %d (%d)\n", |
| 1126 | ce_id, ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1127 | ath10k_ce_deinit(ce_state); |
| 1128 | return NULL; |
| 1129 | } |
| 1130 | } |
| 1131 | |
| 1132 | if (attr->dest_nentries) { |
Michal Kazior | ba7ee55 | 2013-08-13 07:54:57 +0200 | [diff] [blame] | 1133 | ret = ath10k_ce_init_dest_ring(ar, ce_id, ce_state, attr); |
| 1134 | if (ret) { |
| 1135 | ath10k_err("Failed to initialize CE dest ring for ID: %d (%d)\n", |
| 1136 | ce_id, ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1137 | ath10k_ce_deinit(ce_state); |
| 1138 | return NULL; |
| 1139 | } |
| 1140 | } |
| 1141 | |
| 1142 | /* Enable CE error interrupts */ |
| 1143 | ath10k_pci_wake(ar); |
| 1144 | ath10k_ce_error_intr_enable(ar, ctrl_addr); |
| 1145 | ath10k_pci_sleep(ar); |
| 1146 | |
| 1147 | return ce_state; |
| 1148 | } |
| 1149 | |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 1150 | void ath10k_ce_deinit(struct ath10k_ce_pipe *ce_state) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1151 | { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1152 | struct ath10k *ar = ce_state->ar; |
| 1153 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 1154 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1155 | if (ce_state->src_ring) { |
| 1156 | kfree(ce_state->src_ring->shadow_base_unaligned); |
| 1157 | pci_free_consistent(ar_pci->pdev, |
| 1158 | (ce_state->src_ring->nentries * |
| 1159 | sizeof(struct ce_desc) + |
| 1160 | CE_DESC_RING_ALIGN), |
| 1161 | ce_state->src_ring->base_addr_owner_space, |
| 1162 | ce_state->src_ring->base_addr_ce_space); |
| 1163 | kfree(ce_state->src_ring); |
| 1164 | } |
| 1165 | |
| 1166 | if (ce_state->dest_ring) { |
| 1167 | pci_free_consistent(ar_pci->pdev, |
| 1168 | (ce_state->dest_ring->nentries * |
| 1169 | sizeof(struct ce_desc) + |
| 1170 | CE_DESC_RING_ALIGN), |
| 1171 | ce_state->dest_ring->base_addr_owner_space, |
| 1172 | ce_state->dest_ring->base_addr_ce_space); |
| 1173 | kfree(ce_state->dest_ring); |
| 1174 | } |
Michal Kazior | 39e4086 | 2013-08-27 13:07:58 +0200 | [diff] [blame] | 1175 | |
Michal Kazior | 39e4086 | 2013-08-27 13:07:58 +0200 | [diff] [blame] | 1176 | ce_state->src_ring = NULL; |
| 1177 | ce_state->dest_ring = NULL; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1178 | } |