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Tony Lindgrenc5957132008-03-18 14:53:17 +02001/*
2 * OMAP3430 Power/Reset Management register bits
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
Paul Walmsley59fb6592010-12-21 15:30:55 -070013#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
14#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
Tony Lindgrenc5957132008-03-18 14:53:17 +020015
Paul Walmsley59fb6592010-12-21 15:30:55 -070016
Paul Walmsley139563a2012-10-21 01:01:10 -060017#include "prm3xxx.h"
Tony Lindgrenc5957132008-03-18 14:53:17 +020018
Tony Lindgrenc5957132008-03-18 14:53:17 +020019#define OMAP3430_ERROROFFSET_MASK (0xff << 24)
Tony Lindgrenc5957132008-03-18 14:53:17 +020020#define OMAP3430_ERRORGAIN_MASK (0xff << 16)
Tony Lindgrenc5957132008-03-18 14:53:17 +020021#define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060022#define OMAP3430_TIMEOUTEN_MASK (1 << 3)
23#define OMAP3430_INITVDD_MASK (1 << 2)
24#define OMAP3430_FORCEUPDATE_MASK (1 << 1)
25#define OMAP3430_VPENABLE_MASK (1 << 0)
Tony Lindgrenc5957132008-03-18 14:53:17 +020026#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
Tony Lindgrenc5957132008-03-18 14:53:17 +020027#define OMAP3430_VSTEPMIN_SHIFT 0
Tony Lindgrenc5957132008-03-18 14:53:17 +020028#define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
Tony Lindgrenc5957132008-03-18 14:53:17 +020029#define OMAP3430_VSTEPMAX_SHIFT 0
Tony Lindgrenc5957132008-03-18 14:53:17 +020030#define OMAP3430_VDDMAX_SHIFT 24
Tony Lindgrenc5957132008-03-18 14:53:17 +020031#define OMAP3430_VDDMIN_SHIFT 16
Tony Lindgrenc5957132008-03-18 14:53:17 +020032#define OMAP3430_TIMEOUT_SHIFT 0
Tony Lindgrenc5957132008-03-18 14:53:17 +020033#define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030034#define OMAP3430_EN_PER_SHIFT 7
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060035#define OMAP3430_LOGICSTATEST_MASK (1 << 2)
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060036#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2)
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060037#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
Govindraj.Re5863682010-09-27 20:20:25 +053038#define OMAP3630_GRPSEL_UART4_MASK (1 << 18)
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060039#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17)
40#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16)
41#define OMAP3430_GRPSEL_GPIO4_MASK (1 << 15)
42#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14)
43#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13)
44#define OMAP3430_GRPSEL_UART3_MASK (1 << 11)
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060045#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2)
46#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1)
47#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0)
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060048#define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3)
49#define OMAP3430_GRPSEL_GPT12_MASK (1 << 1)
50#define OMAP3430_GRPSEL_GPT1_MASK (1 << 0)
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060051#define OMAP3430_RST3_IVA2_MASK (1 << 2)
52#define OMAP3430_RST2_IVA2_MASK (1 << 1)
53#define OMAP3430_RST1_IVA2_MASK (1 << 0)
Tony Lindgrenc5957132008-03-18 14:53:17 +020054#define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
Tony Lindgrenc5957132008-03-18 14:53:17 +020055#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
Tony Lindgrenc5957132008-03-18 14:53:17 +020056#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
Tony Lindgrenc5957132008-03-18 14:53:17 +020057#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060058#define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11)
59#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10)
60#define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9)
61#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8)
Tony Lindgrenc5957132008-03-18 14:53:17 +020062#define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
Tony Lindgrenc5957132008-03-18 14:53:17 +020063#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
Tony Lindgrenc5957132008-03-18 14:53:17 +020064#define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
Tony Lindgrenc5957132008-03-18 14:53:17 +020065#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
Tony Lindgrenc5957132008-03-18 14:53:17 +020066#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
Tony Lindgrenc5957132008-03-18 14:53:17 +020067#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
Tony Lindgrenc5957132008-03-18 14:53:17 +020068#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060069#define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21)
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060070#define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15)
Tony Lindgrenc5957132008-03-18 14:53:17 +020071#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
Tony Lindgrenc5957132008-03-18 14:53:17 +020072#define OMAP3430_MPU_DPLL_ST_SHIFT 7
Tony Lindgrenc5957132008-03-18 14:53:17 +020073#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
Tony Lindgrenc5957132008-03-18 14:53:17 +020074#define OMAP3430_CORE_DPLL_ST_SHIFT 5
Tony Lindgrenc5957132008-03-18 14:53:17 +020075#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
Tony Lindgrenc5957132008-03-18 14:53:17 +020076#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
Tony Lindgrenc5957132008-03-18 14:53:17 +020077#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
Tony Lindgrenc5957132008-03-18 14:53:17 +020078#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
Tony Lindgrenc5957132008-03-18 14:53:17 +020079#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030080#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030081#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060082#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1)
83#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0)
Tony Lindgrenc5957132008-03-18 14:53:17 +020084#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
Tony Lindgrenc5957132008-03-18 14:53:17 +020085#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060086#define OMAP3430_EN_IO_CHAIN_MASK (1 << 16)
87#define OMAP3430_EN_IO_MASK (1 << 8)
88#define OMAP3430_EN_GPIO1_MASK (1 << 3)
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060089#define OMAP3430_ST_IO_CHAIN_MASK (1 << 16)
90#define OMAP3430_ST_IO_MASK (1 << 8)
Tony Lindgrenc5957132008-03-18 14:53:17 +020091#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
Rajendra Nayak99e79382012-11-02 05:02:58 -060092#define OMAP3430_SYS_CLKIN_SEL_WIDTH 3
Tony Lindgrenc5957132008-03-18 14:53:17 +020093#define OMAP3430_CLKOUT_EN_SHIFT 7
Paul Walmsley2bc4ef72010-05-18 18:47:24 -060094#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0)
Kalle Jokiniemi8dbe4392009-05-16 08:28:17 -070095#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4
Tony Lindgrenc5957132008-03-18 14:53:17 +020096#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
97#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
98#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
99#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
Tony Lindgrenc5957132008-03-18 14:53:17 +0200100#define OMAP3430_VOLRA1_MASK (0xff << 16)
Tony Lindgrenc5957132008-03-18 14:53:17 +0200101#define OMAP3430_VOLRA0_MASK (0xff << 0)
Tony Lindgrenc5957132008-03-18 14:53:17 +0200102#define OMAP3430_CMDRA1_MASK (0xff << 16)
Tony Lindgrenc5957132008-03-18 14:53:17 +0200103#define OMAP3430_CMDRA0_MASK (0xff << 0)
Jouni Hogander027d8de2008-05-16 13:58:18 +0300104#define OMAP3430_VC_CMD_ON_SHIFT 24
105#define OMAP3430_VC_CMD_ON_MASK (0xFF << 24)
106#define OMAP3430_VC_CMD_ONLP_SHIFT 16
Jouni Hogander027d8de2008-05-16 13:58:18 +0300107#define OMAP3430_VC_CMD_RET_SHIFT 8
Jouni Hogander027d8de2008-05-16 13:58:18 +0300108#define OMAP3430_VC_CMD_OFF_SHIFT 0
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600109#define OMAP3430_HSEN_MASK (1 << 3)
Tony Lindgrenc5957132008-03-18 14:53:17 +0200110#define OMAP3430_MCODE_MASK (0x7 << 0)
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600111#define OMAP3430_VALID_MASK (1 << 24)
Tony Lindgrenc5957132008-03-18 14:53:17 +0200112#define OMAP3430_DATA_SHIFT 16
Tony Lindgrenc5957132008-03-18 14:53:17 +0200113#define OMAP3430_REGADDR_SHIFT 8
Tony Lindgrenc5957132008-03-18 14:53:17 +0200114#define OMAP3430_SLAVEADDR_SHIFT 0
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600115#define OMAP3430_ICECRUSHER_RST_SHIFT 10
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600116#define OMAP3430_ICEPICK_RST_SHIFT 9
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600117#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600118#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600119#define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600120#define OMAP3430_SECURE_WD_RST_SHIFT 5
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600121#define OMAP3430_MPU_WD_RST_SHIFT 4
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600122#define OMAP3430_SECURITY_VIOL_RST_SHIFT 3
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600123#define OMAP3430_GLOBAL_SW_RST_SHIFT 1
Paul Walmsley2bb2a5d2012-10-21 01:01:13 -0600124#define OMAP3430_GLOBAL_COLD_RST_SHIFT 0
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600125#define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0)
Tony Lindgren3b8c4eb2014-05-05 17:27:35 -0700126#define OMAP3430_PRM_VOLTCTRL_SEL_VMODE (1 << 4)
127#define OMAP3430_PRM_VOLTCTRL_SEL_OFF (1 << 3)
128#define OMAP3430_PRM_VOLTCTRL_AUTO_OFF (1 << 2)
129#define OMAP3430_PRM_VOLTCTRL_AUTO_RET (1 << 1)
130#define OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP (1 << 0)
Tony Lindgrenc5957132008-03-18 14:53:17 +0200131#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
Tony Lindgrenc5957132008-03-18 14:53:17 +0200132#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
Tony Lindgren3b8c4eb2014-05-05 17:27:35 -0700133#define OMAP3430_PRM_POLCTRL_OFFMODE_POL (1 << 3)
134#define OMAP3430_PRM_POLCTRL_CLKOUT_POL (1 << 2)
135#define OMAP3430_PRM_POLCTRL_CLKREQ_POL (1 << 1)
136#define OMAP3430_PRM_POLCTRL_EXTVOL_POL (1 << 0)
Tony Lindgrenc5957132008-03-18 14:53:17 +0200137#endif