Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 34 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 36 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include <linux/pci.h> |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 38 | #include <linux/dma-buf.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 39 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 40 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 43 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
| 44 | unsigned alignment, |
| 45 | bool map_and_fenceable); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 46 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 47 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 48 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 49 | struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 50 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 52 | struct drm_i915_gem_object *obj); |
| 53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 54 | struct drm_i915_fence_reg *fence, |
| 55 | bool enable); |
| 56 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 58 | struct shrink_control *sc); |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 59 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 60 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 61 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 62 | { |
| 63 | if (obj->tiling_mode) |
| 64 | i915_gem_release_mmap(obj); |
| 65 | |
| 66 | /* As we do not have an associated fence register, we will force |
| 67 | * a tiling change if we ever need to acquire one. |
| 68 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 69 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 70 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 71 | } |
| 72 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 73 | /* some bookkeeping */ |
| 74 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 75 | size_t size) |
| 76 | { |
| 77 | dev_priv->mm.object_count++; |
| 78 | dev_priv->mm.object_memory += size; |
| 79 | } |
| 80 | |
| 81 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 82 | size_t size) |
| 83 | { |
| 84 | dev_priv->mm.object_count--; |
| 85 | dev_priv->mm.object_memory -= size; |
| 86 | } |
| 87 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 88 | static int |
| 89 | i915_gem_wait_for_error(struct drm_device *dev) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 90 | { |
| 91 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 92 | struct completion *x = &dev_priv->error_completion; |
| 93 | unsigned long flags; |
| 94 | int ret; |
| 95 | |
| 96 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 97 | return 0; |
| 98 | |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 99 | /* |
| 100 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 101 | * userspace. If it takes that long something really bad is going on and |
| 102 | * we should simply try to bail out and fail as gracefully as possible. |
| 103 | */ |
| 104 | ret = wait_for_completion_interruptible_timeout(x, 10*HZ); |
| 105 | if (ret == 0) { |
| 106 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 107 | return -EIO; |
| 108 | } else if (ret < 0) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 109 | return ret; |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 110 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 111 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 112 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 113 | /* GPU is hung, bump the completion count to account for |
| 114 | * the token we just consumed so that we never hit zero and |
| 115 | * end up waiting upon a subsequent completion event that |
| 116 | * will never happen. |
| 117 | */ |
| 118 | spin_lock_irqsave(&x->wait.lock, flags); |
| 119 | x->done++; |
| 120 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 121 | } |
| 122 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 123 | } |
| 124 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 125 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 126 | { |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 127 | int ret; |
| 128 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 129 | ret = i915_gem_wait_for_error(dev); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 130 | if (ret) |
| 131 | return ret; |
| 132 | |
| 133 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 134 | if (ret) |
| 135 | return ret; |
| 136 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 137 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 138 | return 0; |
| 139 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 140 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 141 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 142 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 143 | { |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 144 | return !obj->active; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 145 | } |
| 146 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 147 | int |
| 148 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 149 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 150 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 151 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 152 | |
Daniel Vetter | 7bb6fb8 | 2012-04-24 08:22:52 +0200 | [diff] [blame] | 153 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 154 | return -ENODEV; |
| 155 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 156 | if (args->gtt_start >= args->gtt_end || |
| 157 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 158 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 159 | |
Daniel Vetter | f534bc0 | 2012-03-26 22:37:04 +0200 | [diff] [blame] | 160 | /* GEM with user mode setting was never supported on ilk and later. */ |
| 161 | if (INTEL_INFO(dev)->gen >= 5) |
| 162 | return -ENODEV; |
| 163 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 164 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 165 | i915_gem_init_global_gtt(dev, args->gtt_start, |
| 166 | args->gtt_end, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 167 | mutex_unlock(&dev->struct_mutex); |
| 168 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 169 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 170 | } |
| 171 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 172 | int |
| 173 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 174 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 175 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 176 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 177 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 178 | struct drm_i915_gem_object *obj; |
| 179 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 180 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 181 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 182 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 183 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) |
| 184 | if (obj->pin_count) |
| 185 | pinned += obj->gtt_space->size; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 186 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 187 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 188 | args->aper_size = dev_priv->mm.gtt_total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 189 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 190 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 191 | return 0; |
| 192 | } |
| 193 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 194 | static int |
| 195 | i915_gem_create(struct drm_file *file, |
| 196 | struct drm_device *dev, |
| 197 | uint64_t size, |
| 198 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 199 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 200 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 201 | int ret; |
| 202 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 203 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 204 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 205 | if (size == 0) |
| 206 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 207 | |
| 208 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 209 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 210 | if (obj == NULL) |
| 211 | return -ENOMEM; |
| 212 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 213 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 214 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 215 | drm_gem_object_release(&obj->base); |
| 216 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 217 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 218 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 219 | } |
| 220 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 221 | /* drop reference from allocate - handle holds it now */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 222 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 223 | trace_i915_gem_object_create(obj); |
| 224 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 225 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 226 | return 0; |
| 227 | } |
| 228 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 229 | int |
| 230 | i915_gem_dumb_create(struct drm_file *file, |
| 231 | struct drm_device *dev, |
| 232 | struct drm_mode_create_dumb *args) |
| 233 | { |
| 234 | /* have to work out size/pitch and return them */ |
Chris Wilson | ed0291f | 2011-03-19 08:21:45 +0000 | [diff] [blame] | 235 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 236 | args->size = args->pitch * args->height; |
| 237 | return i915_gem_create(file, dev, |
| 238 | args->size, &args->handle); |
| 239 | } |
| 240 | |
| 241 | int i915_gem_dumb_destroy(struct drm_file *file, |
| 242 | struct drm_device *dev, |
| 243 | uint32_t handle) |
| 244 | { |
| 245 | return drm_gem_handle_delete(file, handle); |
| 246 | } |
| 247 | |
| 248 | /** |
| 249 | * Creates a new mm object and returns a handle to it. |
| 250 | */ |
| 251 | int |
| 252 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 253 | struct drm_file *file) |
| 254 | { |
| 255 | struct drm_i915_gem_create *args = data; |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 256 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 257 | return i915_gem_create(file, dev, |
| 258 | args->size, &args->handle); |
| 259 | } |
| 260 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 261 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 262 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 263 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 264 | |
| 265 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 266 | obj->tiling_mode != I915_TILING_NONE; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 267 | } |
| 268 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 269 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 270 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 271 | const char *gpu_vaddr, int gpu_offset, |
| 272 | int length) |
| 273 | { |
| 274 | int ret, cpu_offset = 0; |
| 275 | |
| 276 | while (length > 0) { |
| 277 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 278 | int this_length = min(cacheline_end - gpu_offset, length); |
| 279 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 280 | |
| 281 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 282 | gpu_vaddr + swizzled_gpu_offset, |
| 283 | this_length); |
| 284 | if (ret) |
| 285 | return ret + length; |
| 286 | |
| 287 | cpu_offset += this_length; |
| 288 | gpu_offset += this_length; |
| 289 | length -= this_length; |
| 290 | } |
| 291 | |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | static inline int |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 296 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 297 | const char __user *cpu_vaddr, |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 298 | int length) |
| 299 | { |
| 300 | int ret, cpu_offset = 0; |
| 301 | |
| 302 | while (length > 0) { |
| 303 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 304 | int this_length = min(cacheline_end - gpu_offset, length); |
| 305 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 306 | |
| 307 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 308 | cpu_vaddr + cpu_offset, |
| 309 | this_length); |
| 310 | if (ret) |
| 311 | return ret + length; |
| 312 | |
| 313 | cpu_offset += this_length; |
| 314 | gpu_offset += this_length; |
| 315 | length -= this_length; |
| 316 | } |
| 317 | |
| 318 | return 0; |
| 319 | } |
| 320 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 321 | /* Per-page copy function for the shmem pread fastpath. |
| 322 | * Flushes invalid cachelines before reading the target if |
| 323 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 324 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 325 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 326 | char __user *user_data, |
| 327 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 328 | { |
| 329 | char *vaddr; |
| 330 | int ret; |
| 331 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 332 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 333 | return -EINVAL; |
| 334 | |
| 335 | vaddr = kmap_atomic(page); |
| 336 | if (needs_clflush) |
| 337 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 338 | page_length); |
| 339 | ret = __copy_to_user_inatomic(user_data, |
| 340 | vaddr + shmem_page_offset, |
| 341 | page_length); |
| 342 | kunmap_atomic(vaddr); |
| 343 | |
| 344 | return ret; |
| 345 | } |
| 346 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 347 | static void |
| 348 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 349 | bool swizzled) |
| 350 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 351 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 352 | unsigned long start = (unsigned long) addr; |
| 353 | unsigned long end = (unsigned long) addr + length; |
| 354 | |
| 355 | /* For swizzling simply ensure that we always flush both |
| 356 | * channels. Lame, but simple and it works. Swizzled |
| 357 | * pwrite/pread is far from a hotpath - current userspace |
| 358 | * doesn't use it at all. */ |
| 359 | start = round_down(start, 128); |
| 360 | end = round_up(end, 128); |
| 361 | |
| 362 | drm_clflush_virt_range((void *)start, end - start); |
| 363 | } else { |
| 364 | drm_clflush_virt_range(addr, length); |
| 365 | } |
| 366 | |
| 367 | } |
| 368 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 369 | /* Only difference to the fast-path function is that this can handle bit17 |
| 370 | * and uses non-atomic copy and kmap functions. */ |
| 371 | static int |
| 372 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 373 | char __user *user_data, |
| 374 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 375 | { |
| 376 | char *vaddr; |
| 377 | int ret; |
| 378 | |
| 379 | vaddr = kmap(page); |
| 380 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 381 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 382 | page_length, |
| 383 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 384 | |
| 385 | if (page_do_bit17_swizzling) |
| 386 | ret = __copy_to_user_swizzled(user_data, |
| 387 | vaddr, shmem_page_offset, |
| 388 | page_length); |
| 389 | else |
| 390 | ret = __copy_to_user(user_data, |
| 391 | vaddr + shmem_page_offset, |
| 392 | page_length); |
| 393 | kunmap(page); |
| 394 | |
| 395 | return ret; |
| 396 | } |
| 397 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 398 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 399 | i915_gem_shmem_pread(struct drm_device *dev, |
| 400 | struct drm_i915_gem_object *obj, |
| 401 | struct drm_i915_gem_pread *args, |
| 402 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 403 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 404 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 405 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 406 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 407 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 408 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 409 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 410 | int hit_slowpath = 0; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 411 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 412 | int needs_clflush = 0; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 413 | int release_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 414 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 415 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 416 | remain = args->size; |
| 417 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 418 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 419 | |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 420 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 421 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 422 | * read domain and manually flush cachelines (if required). This |
| 423 | * optimizes for the case when the gpu will dirty the data |
| 424 | * anyway again before the next pread happens. */ |
| 425 | if (obj->cache_level == I915_CACHE_NONE) |
| 426 | needs_clflush = 1; |
| 427 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
| 428 | if (ret) |
| 429 | return ret; |
| 430 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 431 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 432 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 433 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 434 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 435 | struct page *page; |
| 436 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 437 | /* Operation in this page |
| 438 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 439 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 440 | * page_length = bytes to copy for this page |
| 441 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 442 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 443 | page_length = remain; |
| 444 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 445 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 446 | |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 447 | if (obj->pages) { |
| 448 | page = obj->pages[offset >> PAGE_SHIFT]; |
| 449 | release_page = 0; |
| 450 | } else { |
| 451 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
| 452 | if (IS_ERR(page)) { |
| 453 | ret = PTR_ERR(page); |
| 454 | goto out; |
| 455 | } |
| 456 | release_page = 1; |
Jesper Juhl | b65552f | 2011-06-12 20:53:44 +0000 | [diff] [blame] | 457 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 458 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 459 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 460 | (page_to_phys(page) & (1 << 17)) != 0; |
| 461 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 462 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 463 | user_data, page_do_bit17_swizzling, |
| 464 | needs_clflush); |
| 465 | if (ret == 0) |
| 466 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 467 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 468 | hit_slowpath = 1; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 469 | page_cache_get(page); |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 470 | mutex_unlock(&dev->struct_mutex); |
| 471 | |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 472 | if (!prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 473 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 474 | /* Userspace is tricking us, but we've already clobbered |
| 475 | * its pages with the prefault and promised to write the |
| 476 | * data up to the first fault. Hence ignore any errors |
| 477 | * and just continue. */ |
| 478 | (void)ret; |
| 479 | prefaulted = 1; |
| 480 | } |
| 481 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 482 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 483 | user_data, page_do_bit17_swizzling, |
| 484 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 485 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 486 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 487 | page_cache_release(page); |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 488 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 489 | mark_page_accessed(page); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 490 | if (release_page) |
| 491 | page_cache_release(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 492 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 493 | if (ret) { |
| 494 | ret = -EFAULT; |
| 495 | goto out; |
| 496 | } |
| 497 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 498 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 499 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 500 | offset += page_length; |
| 501 | } |
| 502 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 503 | out: |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 504 | if (hit_slowpath) { |
| 505 | /* Fixup: Kill any reinstated backing storage pages */ |
| 506 | if (obj->madv == __I915_MADV_PURGED) |
| 507 | i915_gem_object_truncate(obj); |
| 508 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 509 | |
| 510 | return ret; |
| 511 | } |
| 512 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 513 | /** |
| 514 | * Reads data from the object referenced by handle. |
| 515 | * |
| 516 | * On error, the contents of *data are undefined. |
| 517 | */ |
| 518 | int |
| 519 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 520 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 521 | { |
| 522 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 523 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 524 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 525 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 526 | if (args->size == 0) |
| 527 | return 0; |
| 528 | |
| 529 | if (!access_ok(VERIFY_WRITE, |
| 530 | (char __user *)(uintptr_t)args->data_ptr, |
| 531 | args->size)) |
| 532 | return -EFAULT; |
| 533 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 534 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 535 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 536 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 537 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 538 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 539 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 540 | ret = -ENOENT; |
| 541 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 542 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 543 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 544 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 545 | if (args->offset > obj->base.size || |
| 546 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 547 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 548 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 549 | } |
| 550 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 551 | /* prime objects have no backing filp to GEM pread/pwrite |
| 552 | * pages from. |
| 553 | */ |
| 554 | if (!obj->base.filp) { |
| 555 | ret = -EINVAL; |
| 556 | goto out; |
| 557 | } |
| 558 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 559 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 560 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 561 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 562 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 563 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 564 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 565 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 566 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 567 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 568 | } |
| 569 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 570 | /* This is the fast write path which cannot handle |
| 571 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 572 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 573 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 574 | static inline int |
| 575 | fast_user_write(struct io_mapping *mapping, |
| 576 | loff_t page_base, int page_offset, |
| 577 | char __user *user_data, |
| 578 | int length) |
| 579 | { |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 580 | void __iomem *vaddr_atomic; |
| 581 | void *vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 582 | unsigned long unwritten; |
| 583 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 584 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 585 | /* We can use the cpu mem copy function because this is X86. */ |
| 586 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 587 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 588 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 589 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 590 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 591 | } |
| 592 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 593 | /** |
| 594 | * This is the fast pwrite path, where we copy the data directly from the |
| 595 | * user into the GTT, uncached. |
| 596 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 597 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 598 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 599 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 600 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 601 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 602 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 603 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 604 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 605 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 606 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 607 | int page_offset, page_length, ret; |
| 608 | |
| 609 | ret = i915_gem_object_pin(obj, 0, true); |
| 610 | if (ret) |
| 611 | goto out; |
| 612 | |
| 613 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 614 | if (ret) |
| 615 | goto out_unpin; |
| 616 | |
| 617 | ret = i915_gem_object_put_fence(obj); |
| 618 | if (ret) |
| 619 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 620 | |
| 621 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 622 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 623 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 624 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 625 | |
| 626 | while (remain > 0) { |
| 627 | /* Operation in this page |
| 628 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 629 | * page_base = page offset within aperture |
| 630 | * page_offset = offset within page |
| 631 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 632 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 633 | page_base = offset & PAGE_MASK; |
| 634 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 635 | page_length = remain; |
| 636 | if ((page_offset + remain) > PAGE_SIZE) |
| 637 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 638 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 639 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 640 | * source page isn't available. Return the error and we'll |
| 641 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 642 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 643 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 644 | page_offset, user_data, page_length)) { |
| 645 | ret = -EFAULT; |
| 646 | goto out_unpin; |
| 647 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 648 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 649 | remain -= page_length; |
| 650 | user_data += page_length; |
| 651 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 652 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 653 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 654 | out_unpin: |
| 655 | i915_gem_object_unpin(obj); |
| 656 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 657 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 658 | } |
| 659 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 660 | /* Per-page copy function for the shmem pwrite fastpath. |
| 661 | * Flushes invalid cachelines before writing to the target if |
| 662 | * needs_clflush_before is set and flushes out any written cachelines after |
| 663 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 664 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 665 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 666 | char __user *user_data, |
| 667 | bool page_do_bit17_swizzling, |
| 668 | bool needs_clflush_before, |
| 669 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 670 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 671 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 672 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 673 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 674 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 675 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 676 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 677 | vaddr = kmap_atomic(page); |
| 678 | if (needs_clflush_before) |
| 679 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 680 | page_length); |
| 681 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, |
| 682 | user_data, |
| 683 | page_length); |
| 684 | if (needs_clflush_after) |
| 685 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 686 | page_length); |
| 687 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 688 | |
| 689 | return ret; |
| 690 | } |
| 691 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 692 | /* Only difference to the fast-path function is that this can handle bit17 |
| 693 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 694 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 695 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 696 | char __user *user_data, |
| 697 | bool page_do_bit17_swizzling, |
| 698 | bool needs_clflush_before, |
| 699 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 700 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 701 | char *vaddr; |
| 702 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 703 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 704 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 705 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 706 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 707 | page_length, |
| 708 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 709 | if (page_do_bit17_swizzling) |
| 710 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 711 | user_data, |
| 712 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 713 | else |
| 714 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 715 | user_data, |
| 716 | page_length); |
| 717 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 718 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 719 | page_length, |
| 720 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 721 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 722 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 723 | return ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 724 | } |
| 725 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 726 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 727 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 728 | struct drm_i915_gem_object *obj, |
| 729 | struct drm_i915_gem_pwrite *args, |
| 730 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 731 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 732 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 733 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 734 | loff_t offset; |
| 735 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 736 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 737 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 738 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 739 | int needs_clflush_after = 0; |
| 740 | int needs_clflush_before = 0; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 741 | int release_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 742 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 743 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 744 | remain = args->size; |
| 745 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 746 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 747 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 748 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 749 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 750 | * write domain and manually flush cachelines (if required). This |
| 751 | * optimizes for the case when the gpu will use the data |
| 752 | * right away and we therefore have to clflush anyway. */ |
| 753 | if (obj->cache_level == I915_CACHE_NONE) |
| 754 | needs_clflush_after = 1; |
| 755 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 756 | if (ret) |
| 757 | return ret; |
| 758 | } |
| 759 | /* Same trick applies for invalidate partially written cachelines before |
| 760 | * writing. */ |
| 761 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) |
| 762 | && obj->cache_level == I915_CACHE_NONE) |
| 763 | needs_clflush_before = 1; |
| 764 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 765 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 766 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 767 | |
| 768 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 769 | struct page *page; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 770 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 771 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 772 | /* Operation in this page |
| 773 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 774 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 775 | * page_length = bytes to copy for this page |
| 776 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 777 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 778 | |
| 779 | page_length = remain; |
| 780 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 781 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 782 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 783 | /* If we don't overwrite a cacheline completely we need to be |
| 784 | * careful to have up-to-date data by first clflushing. Don't |
| 785 | * overcomplicate things and flush the entire patch. */ |
| 786 | partial_cacheline_write = needs_clflush_before && |
| 787 | ((shmem_page_offset | page_length) |
| 788 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 789 | |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 790 | if (obj->pages) { |
| 791 | page = obj->pages[offset >> PAGE_SHIFT]; |
| 792 | release_page = 0; |
| 793 | } else { |
| 794 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
| 795 | if (IS_ERR(page)) { |
| 796 | ret = PTR_ERR(page); |
| 797 | goto out; |
| 798 | } |
| 799 | release_page = 1; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 800 | } |
| 801 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 802 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 803 | (page_to_phys(page) & (1 << 17)) != 0; |
| 804 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 805 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 806 | user_data, page_do_bit17_swizzling, |
| 807 | partial_cacheline_write, |
| 808 | needs_clflush_after); |
| 809 | if (ret == 0) |
| 810 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 811 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 812 | hit_slowpath = 1; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 813 | page_cache_get(page); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 814 | mutex_unlock(&dev->struct_mutex); |
| 815 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 816 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 817 | user_data, page_do_bit17_swizzling, |
| 818 | partial_cacheline_write, |
| 819 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 820 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 821 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 822 | page_cache_release(page); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 823 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 824 | set_page_dirty(page); |
| 825 | mark_page_accessed(page); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 826 | if (release_page) |
| 827 | page_cache_release(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 828 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 829 | if (ret) { |
| 830 | ret = -EFAULT; |
| 831 | goto out; |
| 832 | } |
| 833 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 834 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 835 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 836 | offset += page_length; |
| 837 | } |
| 838 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 839 | out: |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 840 | if (hit_slowpath) { |
| 841 | /* Fixup: Kill any reinstated backing storage pages */ |
| 842 | if (obj->madv == __I915_MADV_PURGED) |
| 843 | i915_gem_object_truncate(obj); |
| 844 | /* and flush dirty cachelines in case the object isn't in the cpu write |
| 845 | * domain anymore. */ |
| 846 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 847 | i915_gem_clflush_object(obj); |
| 848 | intel_gtt_chipset_flush(); |
| 849 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 850 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 851 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 852 | if (needs_clflush_after) |
| 853 | intel_gtt_chipset_flush(); |
| 854 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 855 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 856 | } |
| 857 | |
| 858 | /** |
| 859 | * Writes data to the object referenced by handle. |
| 860 | * |
| 861 | * On error, the contents of the buffer that were to be modified are undefined. |
| 862 | */ |
| 863 | int |
| 864 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 865 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 866 | { |
| 867 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 868 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 869 | int ret; |
| 870 | |
| 871 | if (args->size == 0) |
| 872 | return 0; |
| 873 | |
| 874 | if (!access_ok(VERIFY_READ, |
| 875 | (char __user *)(uintptr_t)args->data_ptr, |
| 876 | args->size)) |
| 877 | return -EFAULT; |
| 878 | |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 879 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 880 | args->size); |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 881 | if (ret) |
| 882 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 883 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 884 | ret = i915_mutex_lock_interruptible(dev); |
| 885 | if (ret) |
| 886 | return ret; |
| 887 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 888 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 889 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 890 | ret = -ENOENT; |
| 891 | goto unlock; |
| 892 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 893 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 894 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 895 | if (args->offset > obj->base.size || |
| 896 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 897 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 898 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 899 | } |
| 900 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 901 | /* prime objects have no backing filp to GEM pread/pwrite |
| 902 | * pages from. |
| 903 | */ |
| 904 | if (!obj->base.filp) { |
| 905 | ret = -EINVAL; |
| 906 | goto out; |
| 907 | } |
| 908 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 909 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 910 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 911 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 912 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 913 | * it would end up going through the fenced access, and we'll get |
| 914 | * different detiling behavior between reading and writing. |
| 915 | * pread/pwrite currently are reading and writing from the CPU |
| 916 | * perspective, requiring manual detiling by the client. |
| 917 | */ |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 918 | if (obj->phys_obj) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 919 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 920 | goto out; |
| 921 | } |
| 922 | |
| 923 | if (obj->gtt_space && |
Daniel Vetter | 3ae5378 | 2012-03-25 19:47:33 +0200 | [diff] [blame] | 924 | obj->cache_level == I915_CACHE_NONE && |
Daniel Vetter | c07496f | 2012-04-13 15:51:51 +0200 | [diff] [blame] | 925 | obj->tiling_mode == I915_TILING_NONE && |
Daniel Vetter | ffc6297 | 2012-03-25 19:47:38 +0200 | [diff] [blame] | 926 | obj->map_and_fenceable && |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 927 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 928 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 929 | /* Note that the gtt paths might fail with non-page-backed user |
| 930 | * pointers (e.g. gtt mappings when moving data between |
| 931 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 932 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 933 | |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 934 | if (ret == -EFAULT) |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 935 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 936 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 937 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 938 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 939 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 940 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 941 | return ret; |
| 942 | } |
| 943 | |
| 944 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 945 | * Called when user space prepares to use an object with the CPU, either |
| 946 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 947 | */ |
| 948 | int |
| 949 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 950 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 951 | { |
| 952 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 953 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 954 | uint32_t read_domains = args->read_domains; |
| 955 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 956 | int ret; |
| 957 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 958 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 959 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 960 | return -EINVAL; |
| 961 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 962 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 963 | return -EINVAL; |
| 964 | |
| 965 | /* Having something in the write domain implies it's in the read |
| 966 | * domain, and only that read domain. Enforce that in the request. |
| 967 | */ |
| 968 | if (write_domain != 0 && read_domains != write_domain) |
| 969 | return -EINVAL; |
| 970 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 971 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 972 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 973 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 974 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 975 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 976 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 977 | ret = -ENOENT; |
| 978 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 979 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 980 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 981 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 982 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 983 | |
| 984 | /* Silently promote "you're not bound, there was nothing to do" |
| 985 | * to success, since the client was just asking us to |
| 986 | * make sure everything was done. |
| 987 | */ |
| 988 | if (ret == -EINVAL) |
| 989 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 990 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 991 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 992 | } |
| 993 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 994 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 995 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 996 | mutex_unlock(&dev->struct_mutex); |
| 997 | return ret; |
| 998 | } |
| 999 | |
| 1000 | /** |
| 1001 | * Called when user space has done writes to this buffer |
| 1002 | */ |
| 1003 | int |
| 1004 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1005 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1006 | { |
| 1007 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1008 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1009 | int ret = 0; |
| 1010 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1011 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1012 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1013 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1014 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1015 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1016 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1017 | ret = -ENOENT; |
| 1018 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1019 | } |
| 1020 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1021 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1022 | if (obj->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1023 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1024 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1025 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1026 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1027 | mutex_unlock(&dev->struct_mutex); |
| 1028 | return ret; |
| 1029 | } |
| 1030 | |
| 1031 | /** |
| 1032 | * Maps the contents of an object, returning the address it is mapped |
| 1033 | * into. |
| 1034 | * |
| 1035 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1036 | * imply a ref on the object itself. |
| 1037 | */ |
| 1038 | int |
| 1039 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1040 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1041 | { |
| 1042 | struct drm_i915_gem_mmap *args = data; |
| 1043 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1044 | unsigned long addr; |
| 1045 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1046 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1047 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1048 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1049 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1050 | /* prime objects have no backing filp to GEM mmap |
| 1051 | * pages from. |
| 1052 | */ |
| 1053 | if (!obj->filp) { |
| 1054 | drm_gem_object_unreference_unlocked(obj); |
| 1055 | return -EINVAL; |
| 1056 | } |
| 1057 | |
Linus Torvalds | 6be5ceb | 2012-04-20 17:13:58 -0700 | [diff] [blame] | 1058 | addr = vm_mmap(obj->filp, 0, args->size, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1059 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1060 | args->offset); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1061 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1062 | if (IS_ERR((void *)addr)) |
| 1063 | return addr; |
| 1064 | |
| 1065 | args->addr_ptr = (uint64_t) addr; |
| 1066 | |
| 1067 | return 0; |
| 1068 | } |
| 1069 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1070 | /** |
| 1071 | * i915_gem_fault - fault a page into the GTT |
| 1072 | * vma: VMA in question |
| 1073 | * vmf: fault info |
| 1074 | * |
| 1075 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1076 | * from userspace. The fault handler takes care of binding the object to |
| 1077 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1078 | * only if needed based on whether the old reg is still valid or the object |
| 1079 | * is tiled) and inserting a new PTE into the faulting process. |
| 1080 | * |
| 1081 | * Note that the faulting process may involve evicting existing objects |
| 1082 | * from the GTT and/or fence registers to make room. So performance may |
| 1083 | * suffer if the GTT working set is large or there are few fence registers |
| 1084 | * left. |
| 1085 | */ |
| 1086 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1087 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1088 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1089 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1090 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1091 | pgoff_t page_offset; |
| 1092 | unsigned long pfn; |
| 1093 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1094 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1095 | |
| 1096 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1097 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1098 | PAGE_SHIFT; |
| 1099 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1100 | ret = i915_mutex_lock_interruptible(dev); |
| 1101 | if (ret) |
| 1102 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1103 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1104 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1105 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1106 | /* Now bind it into the GTT if needed */ |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1107 | if (!obj->map_and_fenceable) { |
| 1108 | ret = i915_gem_object_unbind(obj); |
| 1109 | if (ret) |
| 1110 | goto unlock; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1111 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1112 | if (!obj->gtt_space) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1113 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1114 | if (ret) |
| 1115 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1116 | |
Eric Anholt | e92d03b | 2011-06-14 16:43:09 -0700 | [diff] [blame] | 1117 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1118 | if (ret) |
| 1119 | goto unlock; |
| 1120 | } |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 1121 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1122 | if (!obj->has_global_gtt_mapping) |
| 1123 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 1124 | |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 1125 | ret = i915_gem_object_get_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1126 | if (ret) |
| 1127 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1128 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1129 | if (i915_gem_object_is_inactive(obj)) |
| 1130 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1131 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1132 | obj->fault_mappable = true; |
| 1133 | |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1134 | pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) + |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1135 | page_offset; |
| 1136 | |
| 1137 | /* Finally, remap it using the new GTT offset */ |
| 1138 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1139 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1140 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1141 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1142 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1143 | case -EIO: |
Daniel Vetter | a9340cc | 2012-07-04 22:18:42 +0200 | [diff] [blame] | 1144 | /* If this -EIO is due to a gpu hang, give the reset code a |
| 1145 | * chance to clean up the mess. Otherwise return the proper |
| 1146 | * SIGBUS. */ |
| 1147 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 1148 | return VM_FAULT_SIGBUS; |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1149 | case -EAGAIN: |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1150 | /* Give the error handler a chance to run and move the |
| 1151 | * objects off the GPU active list. Next time we service the |
| 1152 | * fault, we should be able to transition the page into the |
| 1153 | * GTT without touching the GPU (and so avoid further |
| 1154 | * EIO/EGAIN). If the GPU is wedged, then there is no issue |
| 1155 | * with coherency, just lost writes. |
| 1156 | */ |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1157 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1158 | case 0: |
| 1159 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1160 | case -EINTR: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1161 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1162 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1163 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1164 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1165 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1166 | } |
| 1167 | } |
| 1168 | |
| 1169 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1170 | * i915_gem_release_mmap - remove physical page mappings |
| 1171 | * @obj: obj in question |
| 1172 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1173 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1174 | * relinquish ownership of the pages back to the system. |
| 1175 | * |
| 1176 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1177 | * object through the GTT and then lose the fence register due to |
| 1178 | * resource pressure. Similarly if the object has been moved out of the |
| 1179 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1180 | * mapping will then trigger a page fault on the next user access, allowing |
| 1181 | * fixup by i915_gem_fault(). |
| 1182 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1183 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1184 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1185 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1186 | if (!obj->fault_mappable) |
| 1187 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1188 | |
Chris Wilson | f6e4788 | 2011-03-20 21:09:12 +0000 | [diff] [blame] | 1189 | if (obj->base.dev->dev_mapping) |
| 1190 | unmap_mapping_range(obj->base.dev->dev_mapping, |
| 1191 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
| 1192 | obj->base.size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1193 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1194 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1195 | } |
| 1196 | |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1197 | static uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1198 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1199 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1200 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1201 | |
| 1202 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1203 | tiling_mode == I915_TILING_NONE) |
| 1204 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1205 | |
| 1206 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1207 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1208 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1209 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1210 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1211 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1212 | while (gtt_size < size) |
| 1213 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1214 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1215 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1216 | } |
| 1217 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1218 | /** |
| 1219 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1220 | * @obj: object to check |
| 1221 | * |
| 1222 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1223 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1224 | */ |
| 1225 | static uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1226 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
| 1227 | uint32_t size, |
| 1228 | int tiling_mode) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1229 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1230 | /* |
| 1231 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1232 | * if a fence register is needed for the object. |
| 1233 | */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1234 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1235 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1236 | return 4096; |
| 1237 | |
| 1238 | /* |
| 1239 | * Previous chips need to be aligned to the size of the smallest |
| 1240 | * fence register that can contain the object. |
| 1241 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1242 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1243 | } |
| 1244 | |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1245 | /** |
| 1246 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
| 1247 | * unfenced object |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1248 | * @dev: the device |
| 1249 | * @size: size of the object |
| 1250 | * @tiling_mode: tiling mode of the object |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1251 | * |
| 1252 | * Return the required GTT alignment for an object, only taking into account |
| 1253 | * unfenced tiled surface requirements. |
| 1254 | */ |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 1255 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1256 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
| 1257 | uint32_t size, |
| 1258 | int tiling_mode) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1259 | { |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1260 | /* |
| 1261 | * Minimum alignment is 4k (GTT page size) for sane hw. |
| 1262 | */ |
| 1263 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1264 | tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1265 | return 4096; |
| 1266 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1267 | /* Previous hardware however needs to be aligned to a power-of-two |
| 1268 | * tile height. The simplest method for determining this is to reuse |
| 1269 | * the power-of-tile object size. |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1270 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1271 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1272 | } |
| 1273 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1274 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1275 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1276 | struct drm_device *dev, |
| 1277 | uint32_t handle, |
| 1278 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1279 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1280 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1281 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1282 | int ret; |
| 1283 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1284 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1285 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1286 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1287 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1288 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1289 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1290 | ret = -ENOENT; |
| 1291 | goto unlock; |
| 1292 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1293 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1294 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1295 | ret = -E2BIG; |
Eric Anholt | ff56b0b | 2011-10-31 23:16:21 -0700 | [diff] [blame] | 1296 | goto out; |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1297 | } |
| 1298 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1299 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1300 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1301 | ret = -EINVAL; |
| 1302 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1303 | } |
| 1304 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1305 | if (!obj->base.map_list.map) { |
Rob Clark | b464e9a | 2011-08-10 08:09:08 -0500 | [diff] [blame] | 1306 | ret = drm_gem_create_mmap_offset(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1307 | if (ret) |
| 1308 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1309 | } |
| 1310 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1311 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1312 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1313 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1314 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1315 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1316 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1317 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1318 | } |
| 1319 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1320 | /** |
| 1321 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1322 | * @dev: DRM device |
| 1323 | * @data: GTT mapping ioctl data |
| 1324 | * @file: GEM object info |
| 1325 | * |
| 1326 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1327 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1328 | * up so we can get faults in the handler above. |
| 1329 | * |
| 1330 | * The fault handler will take care of binding the object into the GTT |
| 1331 | * (since it may have been evicted to make room for something), allocating |
| 1332 | * a fence register, and mapping the appropriate aperture address into |
| 1333 | * userspace. |
| 1334 | */ |
| 1335 | int |
| 1336 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1337 | struct drm_file *file) |
| 1338 | { |
| 1339 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1340 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1341 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1342 | } |
| 1343 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1344 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1345 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1346 | gfp_t gfpmask) |
| 1347 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1348 | int page_count, i; |
| 1349 | struct address_space *mapping; |
| 1350 | struct inode *inode; |
| 1351 | struct page *page; |
| 1352 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1353 | if (obj->pages || obj->sg_table) |
| 1354 | return 0; |
| 1355 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1356 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1357 | * at this point until we release them. |
| 1358 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1359 | page_count = obj->base.size / PAGE_SIZE; |
| 1360 | BUG_ON(obj->pages != NULL); |
| 1361 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); |
| 1362 | if (obj->pages == NULL) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1363 | return -ENOMEM; |
| 1364 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1365 | inode = obj->base.filp->f_path.dentry->d_inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1366 | mapping = inode->i_mapping; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1367 | gfpmask |= mapping_gfp_mask(mapping); |
| 1368 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1369 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1370 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1371 | if (IS_ERR(page)) |
| 1372 | goto err_pages; |
| 1373 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1374 | obj->pages[i] = page; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1375 | } |
| 1376 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1377 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1378 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1379 | |
| 1380 | return 0; |
| 1381 | |
| 1382 | err_pages: |
| 1383 | while (i--) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1384 | page_cache_release(obj->pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1385 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1386 | drm_free_large(obj->pages); |
| 1387 | obj->pages = NULL; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1388 | return PTR_ERR(page); |
| 1389 | } |
| 1390 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1391 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1392 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1393 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1394 | int page_count = obj->base.size / PAGE_SIZE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1395 | int i; |
| 1396 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1397 | if (!obj->pages) |
| 1398 | return; |
| 1399 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1400 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1401 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1402 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1403 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1404 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1405 | if (obj->madv == I915_MADV_DONTNEED) |
| 1406 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1407 | |
| 1408 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1409 | if (obj->dirty) |
| 1410 | set_page_dirty(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1411 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1412 | if (obj->madv == I915_MADV_WILLNEED) |
| 1413 | mark_page_accessed(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1414 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1415 | page_cache_release(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1416 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1417 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1418 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1419 | drm_free_large(obj->pages); |
| 1420 | obj->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1421 | } |
| 1422 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1423 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1424 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1425 | struct intel_ring_buffer *ring, |
| 1426 | u32 seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1427 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1428 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1429 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1430 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1431 | BUG_ON(ring == NULL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1432 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1433 | |
| 1434 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1435 | if (!obj->active) { |
| 1436 | drm_gem_object_reference(&obj->base); |
| 1437 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1438 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1439 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1440 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1441 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
| 1442 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1443 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1444 | obj->last_rendering_seqno = seqno; |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1445 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1446 | if (obj->fenced_gpu_access) { |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1447 | obj->last_fenced_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1448 | |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1449 | /* Bump MRU to take account of the delayed flush */ |
| 1450 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 1451 | struct drm_i915_fence_reg *reg; |
| 1452 | |
| 1453 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1454 | list_move_tail(®->lru_list, |
| 1455 | &dev_priv->mm.fence_list); |
| 1456 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1457 | } |
| 1458 | } |
| 1459 | |
| 1460 | static void |
| 1461 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) |
| 1462 | { |
| 1463 | list_del_init(&obj->ring_list); |
| 1464 | obj->last_rendering_seqno = 0; |
Daniel Vetter | 15a13bb | 2012-04-12 01:27:57 +0200 | [diff] [blame] | 1465 | obj->last_fenced_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1466 | } |
| 1467 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1468 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1469 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1470 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1471 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1472 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1473 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1474 | BUG_ON(!obj->active); |
| 1475 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1476 | |
| 1477 | i915_gem_object_move_off_active(obj); |
| 1478 | } |
| 1479 | |
| 1480 | static void |
| 1481 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1482 | { |
| 1483 | struct drm_device *dev = obj->base.dev; |
| 1484 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1485 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 1486 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1487 | |
| 1488 | BUG_ON(!list_empty(&obj->gpu_write_list)); |
| 1489 | BUG_ON(!obj->active); |
| 1490 | obj->ring = NULL; |
| 1491 | |
| 1492 | i915_gem_object_move_off_active(obj); |
| 1493 | obj->fenced_gpu_access = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1494 | |
| 1495 | obj->active = 0; |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 1496 | obj->pending_gpu_write = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1497 | drm_gem_object_unreference(&obj->base); |
| 1498 | |
| 1499 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1500 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1501 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1502 | /* Immediately discard the backing storage */ |
| 1503 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1504 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1505 | { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1506 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1507 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1508 | /* Our goal here is to return as much of the memory as |
| 1509 | * is possible back to the system as we are called from OOM. |
| 1510 | * To do this we must instruct the shmfs to drop all of its |
Hugh Dickins | e2377fe | 2011-06-27 16:18:19 -0700 | [diff] [blame] | 1511 | * backing pages, *now*. |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1512 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1513 | inode = obj->base.filp->f_path.dentry->d_inode; |
Hugh Dickins | e2377fe | 2011-06-27 16:18:19 -0700 | [diff] [blame] | 1514 | shmem_truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1515 | |
Chris Wilson | a14917e | 2012-02-24 21:13:38 +0000 | [diff] [blame] | 1516 | if (obj->base.map_list.map) |
| 1517 | drm_gem_free_mmap_offset(&obj->base); |
| 1518 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1519 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1520 | } |
| 1521 | |
| 1522 | static inline int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1523 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1524 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1525 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1526 | } |
| 1527 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1528 | static void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1529 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
| 1530 | uint32_t flush_domains) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1531 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1532 | struct drm_i915_gem_object *obj, *next; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1533 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1534 | list_for_each_entry_safe(obj, next, |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1535 | &ring->gpu_write_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1536 | gpu_write_list) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1537 | if (obj->base.write_domain & flush_domains) { |
| 1538 | uint32_t old_write_domain = obj->base.write_domain; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1539 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1540 | obj->base.write_domain = 0; |
| 1541 | list_del_init(&obj->gpu_write_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1542 | i915_gem_object_move_to_active(obj, ring, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1543 | i915_gem_next_request_seqno(ring)); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1544 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1545 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1546 | obj->base.read_domains, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1547 | old_write_domain); |
| 1548 | } |
| 1549 | } |
| 1550 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1551 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1552 | static u32 |
| 1553 | i915_gem_get_seqno(struct drm_device *dev) |
| 1554 | { |
| 1555 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1556 | u32 seqno = dev_priv->next_seqno; |
| 1557 | |
| 1558 | /* reserve 0 for non-seqno */ |
| 1559 | if (++dev_priv->next_seqno == 0) |
| 1560 | dev_priv->next_seqno = 1; |
| 1561 | |
| 1562 | return seqno; |
| 1563 | } |
| 1564 | |
| 1565 | u32 |
| 1566 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
| 1567 | { |
| 1568 | if (ring->outstanding_lazy_request == 0) |
| 1569 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); |
| 1570 | |
| 1571 | return ring->outstanding_lazy_request; |
| 1572 | } |
| 1573 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1574 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1575 | i915_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1576 | struct drm_file *file, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1577 | struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1578 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1579 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1580 | uint32_t seqno; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1581 | u32 request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1582 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1583 | int ret; |
| 1584 | |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 1585 | /* |
| 1586 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 1587 | * after having emitted the batchbuffer command. Hence we need to fix |
| 1588 | * things up similar to emitting the lazy request. The difference here |
| 1589 | * is that the flush _must_ happen before the next request, no matter |
| 1590 | * what. |
| 1591 | */ |
| 1592 | if (ring->gpu_caches_dirty) { |
| 1593 | ret = i915_gem_flush_ring(ring, 0, I915_GEM_GPU_DOMAINS); |
| 1594 | if (ret) |
| 1595 | return ret; |
| 1596 | |
| 1597 | ring->gpu_caches_dirty = false; |
| 1598 | } |
| 1599 | |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame^] | 1600 | if (request == NULL) { |
| 1601 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
| 1602 | if (request == NULL) |
| 1603 | return -ENOMEM; |
| 1604 | } |
| 1605 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1606 | seqno = i915_gem_next_request_seqno(ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1607 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1608 | /* Record the position of the start of the request so that |
| 1609 | * should we detect the updated seqno part-way through the |
| 1610 | * GPU processing the request, we never over-estimate the |
| 1611 | * position of the head. |
| 1612 | */ |
| 1613 | request_ring_position = intel_ring_get_tail(ring); |
| 1614 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1615 | ret = ring->add_request(ring, &seqno); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame^] | 1616 | if (ret) { |
| 1617 | kfree(request); |
| 1618 | return ret; |
| 1619 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1620 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1621 | trace_i915_gem_request_add(ring, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1622 | |
| 1623 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1624 | request->ring = ring; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1625 | request->tail = request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1626 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1627 | was_empty = list_empty(&ring->request_list); |
| 1628 | list_add_tail(&request->list, &ring->request_list); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame^] | 1629 | request->file_priv = NULL; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1630 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1631 | if (file) { |
| 1632 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 1633 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1634 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1635 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1636 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1637 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1638 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1639 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1640 | |
Daniel Vetter | 5391d0c | 2012-01-25 14:03:57 +0100 | [diff] [blame] | 1641 | ring->outstanding_lazy_request = 0; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1642 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1643 | if (!dev_priv->mm.suspended) { |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 1644 | if (i915_enable_hangcheck) { |
| 1645 | mod_timer(&dev_priv->hangcheck_timer, |
| 1646 | jiffies + |
| 1647 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
| 1648 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1649 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1650 | queue_delayed_work(dev_priv->wq, |
| 1651 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1652 | } |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 1653 | |
| 1654 | WARN_ON(!list_empty(&ring->gpu_write_list)); |
| 1655 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1656 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1657 | } |
| 1658 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1659 | static inline void |
| 1660 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1661 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1662 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1663 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1664 | if (!file_priv) |
| 1665 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1666 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1667 | spin_lock(&file_priv->mm.lock); |
Herton Ronaldo Krzesinski | 09bfa51 | 2011-03-17 13:45:12 +0000 | [diff] [blame] | 1668 | if (request->file_priv) { |
| 1669 | list_del(&request->client_list); |
| 1670 | request->file_priv = NULL; |
| 1671 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1672 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1673 | } |
| 1674 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1675 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1676 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1677 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1678 | while (!list_empty(&ring->request_list)) { |
| 1679 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1680 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1681 | request = list_first_entry(&ring->request_list, |
| 1682 | struct drm_i915_gem_request, |
| 1683 | list); |
| 1684 | |
| 1685 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1686 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1687 | kfree(request); |
| 1688 | } |
| 1689 | |
| 1690 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1691 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1692 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1693 | obj = list_first_entry(&ring->active_list, |
| 1694 | struct drm_i915_gem_object, |
| 1695 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1696 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1697 | obj->base.write_domain = 0; |
| 1698 | list_del_init(&obj->gpu_write_list); |
| 1699 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1700 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1701 | } |
| 1702 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1703 | static void i915_gem_reset_fences(struct drm_device *dev) |
| 1704 | { |
| 1705 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1706 | int i; |
| 1707 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 1708 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1709 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 1710 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 1711 | i915_gem_write_fence(dev, i, NULL); |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 1712 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 1713 | if (reg->obj) |
| 1714 | i915_gem_object_fence_lost(reg->obj); |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 1715 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 1716 | reg->pin_count = 0; |
| 1717 | reg->obj = NULL; |
| 1718 | INIT_LIST_HEAD(®->lru_list); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1719 | } |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 1720 | |
| 1721 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1722 | } |
| 1723 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1724 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1725 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1726 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1727 | struct drm_i915_gem_object *obj; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1728 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1729 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1730 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1731 | for_each_ring(ring, dev_priv, i) |
| 1732 | i915_gem_reset_ring_lists(dev_priv, ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1733 | |
| 1734 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1735 | * to be lost on reset along with the data, so simply move the |
| 1736 | * lost bo to the inactive list. |
| 1737 | */ |
| 1738 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1739 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1740 | struct drm_i915_gem_object, |
| 1741 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1742 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1743 | obj->base.write_domain = 0; |
| 1744 | list_del_init(&obj->gpu_write_list); |
| 1745 | i915_gem_object_move_to_inactive(obj); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1746 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1747 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1748 | /* Move everything out of the GPU domains to ensure we do any |
| 1749 | * necessary invalidation upon reuse. |
| 1750 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1751 | list_for_each_entry(obj, |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1752 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1753 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1754 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1755 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1756 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1757 | |
| 1758 | /* The fence registers are invalidated so clear them out */ |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1759 | i915_gem_reset_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1760 | } |
| 1761 | |
| 1762 | /** |
| 1763 | * This function clears the request list as sequence numbers are passed. |
| 1764 | */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1765 | void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1766 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1767 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1768 | uint32_t seqno; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1769 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1770 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1771 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1772 | return; |
| 1773 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1774 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1775 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1776 | seqno = ring->get_seqno(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1777 | |
Chris Wilson | 076e2c0 | 2011-01-21 10:07:18 +0000 | [diff] [blame] | 1778 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1779 | if (seqno >= ring->sync_seqno[i]) |
| 1780 | ring->sync_seqno[i] = 0; |
| 1781 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1782 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1783 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1784 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1785 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1786 | struct drm_i915_gem_request, |
| 1787 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1788 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1789 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1790 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1791 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1792 | trace_i915_gem_request_retire(ring, request->seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1793 | /* We know the GPU must have read the request to have |
| 1794 | * sent us the seqno + interrupt, so use the position |
| 1795 | * of tail of the request to update the last known position |
| 1796 | * of the GPU head. |
| 1797 | */ |
| 1798 | ring->last_retired_head = request->tail; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1799 | |
| 1800 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1801 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1802 | kfree(request); |
| 1803 | } |
| 1804 | |
| 1805 | /* Move any buffers on the active list that are no longer referenced |
| 1806 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1807 | */ |
| 1808 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1809 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1810 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1811 | obj = list_first_entry(&ring->active_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1812 | struct drm_i915_gem_object, |
| 1813 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1814 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1815 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1816 | break; |
| 1817 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1818 | if (obj->base.write_domain != 0) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1819 | i915_gem_object_move_to_flushing(obj); |
| 1820 | else |
| 1821 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1822 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1823 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1824 | if (unlikely(ring->trace_irq_seqno && |
| 1825 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1826 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1827 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1828 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1829 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1830 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1831 | } |
| 1832 | |
| 1833 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1834 | i915_gem_retire_requests(struct drm_device *dev) |
| 1835 | { |
| 1836 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1837 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1838 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1839 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1840 | for_each_ring(ring, dev_priv, i) |
| 1841 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1842 | } |
| 1843 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1844 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1845 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1846 | { |
| 1847 | drm_i915_private_t *dev_priv; |
| 1848 | struct drm_device *dev; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1849 | struct intel_ring_buffer *ring; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1850 | bool idle; |
| 1851 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1852 | |
| 1853 | dev_priv = container_of(work, drm_i915_private_t, |
| 1854 | mm.retire_work.work); |
| 1855 | dev = dev_priv->dev; |
| 1856 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 1857 | /* Come back later if the device is busy... */ |
| 1858 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 1859 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1860 | return; |
| 1861 | } |
| 1862 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1863 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1864 | |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1865 | /* Send a periodic flush down the ring so we don't hold onto GEM |
| 1866 | * objects indefinitely. |
| 1867 | */ |
| 1868 | idle = true; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1869 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame^] | 1870 | if (ring->gpu_caches_dirty) |
| 1871 | i915_add_request(ring, NULL, NULL); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1872 | |
| 1873 | idle &= list_empty(&ring->request_list); |
| 1874 | } |
| 1875 | |
| 1876 | if (!dev_priv->mm.suspended && !idle) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1877 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1878 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1879 | mutex_unlock(&dev->struct_mutex); |
| 1880 | } |
| 1881 | |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1882 | int |
| 1883 | i915_gem_check_wedge(struct drm_i915_private *dev_priv, |
| 1884 | bool interruptible) |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 1885 | { |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 1886 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 1887 | struct completion *x = &dev_priv->error_completion; |
| 1888 | bool recovery_complete; |
| 1889 | unsigned long flags; |
| 1890 | |
| 1891 | /* Give the error handler a chance to run. */ |
| 1892 | spin_lock_irqsave(&x->wait.lock, flags); |
| 1893 | recovery_complete = x->done > 0; |
| 1894 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 1895 | |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1896 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 1897 | * -EIO unconditionally for these. */ |
| 1898 | if (!interruptible) |
| 1899 | return -EIO; |
| 1900 | |
| 1901 | /* Recovery complete, but still wedged means reset failure. */ |
| 1902 | if (recovery_complete) |
| 1903 | return -EIO; |
| 1904 | |
| 1905 | return -EAGAIN; |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 1906 | } |
| 1907 | |
| 1908 | return 0; |
| 1909 | } |
| 1910 | |
| 1911 | /* |
| 1912 | * Compare seqno against outstanding lazy request. Emit a request if they are |
| 1913 | * equal. |
| 1914 | */ |
| 1915 | static int |
| 1916 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) |
| 1917 | { |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame^] | 1918 | int ret; |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 1919 | |
| 1920 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
| 1921 | |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame^] | 1922 | ret = 0; |
| 1923 | if (seqno == ring->outstanding_lazy_request) |
| 1924 | ret = i915_add_request(ring, NULL, NULL); |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 1925 | |
| 1926 | return ret; |
| 1927 | } |
| 1928 | |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1929 | /** |
| 1930 | * __wait_seqno - wait until execution of seqno has finished |
| 1931 | * @ring: the ring expected to report seqno |
| 1932 | * @seqno: duh! |
| 1933 | * @interruptible: do an interruptible wait (normally yes) |
| 1934 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 1935 | * |
| 1936 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
| 1937 | * errno with remaining time filled in timeout argument. |
| 1938 | */ |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1939 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1940 | bool interruptible, struct timespec *timeout) |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1941 | { |
| 1942 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1943 | struct timespec before, now, wait_time={1,0}; |
| 1944 | unsigned long timeout_jiffies; |
| 1945 | long end; |
| 1946 | bool wait_forever = true; |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1947 | int ret; |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1948 | |
| 1949 | if (i915_seqno_passed(ring->get_seqno(ring), seqno)) |
| 1950 | return 0; |
| 1951 | |
| 1952 | trace_i915_gem_request_wait_begin(ring, seqno); |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1953 | |
| 1954 | if (timeout != NULL) { |
| 1955 | wait_time = *timeout; |
| 1956 | wait_forever = false; |
| 1957 | } |
| 1958 | |
| 1959 | timeout_jiffies = timespec_to_jiffies(&wait_time); |
| 1960 | |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1961 | if (WARN_ON(!ring->irq_get(ring))) |
| 1962 | return -ENODEV; |
| 1963 | |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1964 | /* Record current time in case interrupted by signal, or wedged * */ |
| 1965 | getrawmonotonic(&before); |
| 1966 | |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1967 | #define EXIT_COND \ |
| 1968 | (i915_seqno_passed(ring->get_seqno(ring), seqno) || \ |
| 1969 | atomic_read(&dev_priv->mm.wedged)) |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1970 | do { |
| 1971 | if (interruptible) |
| 1972 | end = wait_event_interruptible_timeout(ring->irq_queue, |
| 1973 | EXIT_COND, |
| 1974 | timeout_jiffies); |
| 1975 | else |
| 1976 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, |
| 1977 | timeout_jiffies); |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1978 | |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1979 | ret = i915_gem_check_wedge(dev_priv, interruptible); |
| 1980 | if (ret) |
| 1981 | end = ret; |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1982 | } while (end == 0 && wait_forever); |
| 1983 | |
| 1984 | getrawmonotonic(&now); |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1985 | |
| 1986 | ring->irq_put(ring); |
| 1987 | trace_i915_gem_request_wait_end(ring, seqno); |
| 1988 | #undef EXIT_COND |
| 1989 | |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1990 | if (timeout) { |
| 1991 | struct timespec sleep_time = timespec_sub(now, before); |
| 1992 | *timeout = timespec_sub(*timeout, sleep_time); |
| 1993 | } |
| 1994 | |
| 1995 | switch (end) { |
Chris Wilson | eeef9b3 | 2012-07-16 13:05:34 +0100 | [diff] [blame] | 1996 | case -EIO: |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1997 | case -EAGAIN: /* Wedged */ |
| 1998 | case -ERESTARTSYS: /* Signal */ |
| 1999 | return (int)end; |
| 2000 | case 0: /* Timeout */ |
| 2001 | if (timeout) |
| 2002 | set_normalized_timespec(timeout, 0, 0); |
| 2003 | return -ETIME; |
| 2004 | default: /* Completed */ |
| 2005 | WARN_ON(end < 0); /* We're not aware of other errors */ |
| 2006 | return 0; |
| 2007 | } |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 2008 | } |
| 2009 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2010 | /** |
| 2011 | * Waits for a sequence number to be signaled, and cleans up the |
| 2012 | * request and object lists appropriately for that event. |
| 2013 | */ |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 2014 | int |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 2015 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2016 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2017 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2018 | int ret = 0; |
| 2019 | |
| 2020 | BUG_ON(seqno == 0); |
| 2021 | |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 2022 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 2023 | if (ret) |
| 2024 | return ret; |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 2025 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 2026 | ret = i915_gem_check_olr(ring, seqno); |
| 2027 | if (ret) |
| 2028 | return ret; |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2029 | |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 2030 | ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2031 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2032 | return ret; |
| 2033 | } |
| 2034 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2035 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2036 | * Ensures that all rendering to the object has completed and the object is |
| 2037 | * safe to unbind from the GTT or access from the CPU. |
| 2038 | */ |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2039 | int |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2040 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2041 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2042 | int ret; |
| 2043 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2044 | /* This function only exists to support waiting for existing rendering, |
| 2045 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2046 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2047 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2048 | |
| 2049 | /* If there is rendering queued on the buffer being evicted, wait for |
| 2050 | * it. |
| 2051 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2052 | if (obj->active) { |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 2053 | ret = i915_wait_seqno(obj->ring, obj->last_rendering_seqno); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2054 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2055 | return ret; |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2056 | i915_gem_retire_requests_ring(obj->ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2057 | } |
| 2058 | |
| 2059 | return 0; |
| 2060 | } |
| 2061 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2062 | /** |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2063 | * Ensures that an object will eventually get non-busy by flushing any required |
| 2064 | * write domains, emitting any outstanding lazy request and retiring and |
| 2065 | * completed requests. |
| 2066 | */ |
| 2067 | static int |
| 2068 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 2069 | { |
| 2070 | int ret; |
| 2071 | |
| 2072 | if (obj->active) { |
| 2073 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2074 | if (ret) |
| 2075 | return ret; |
| 2076 | |
| 2077 | ret = i915_gem_check_olr(obj->ring, |
| 2078 | obj->last_rendering_seqno); |
| 2079 | if (ret) |
| 2080 | return ret; |
| 2081 | i915_gem_retire_requests_ring(obj->ring); |
| 2082 | } |
| 2083 | |
| 2084 | return 0; |
| 2085 | } |
| 2086 | |
| 2087 | /** |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2088 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 2089 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 2090 | * |
| 2091 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 2092 | * the timeout parameter. |
| 2093 | * -ETIME: object is still busy after timeout |
| 2094 | * -ERESTARTSYS: signal interrupted the wait |
| 2095 | * -ENONENT: object doesn't exist |
| 2096 | * Also possible, but rare: |
| 2097 | * -EAGAIN: GPU wedged |
| 2098 | * -ENOMEM: damn |
| 2099 | * -ENODEV: Internal IRQ fail |
| 2100 | * -E?: The add request failed |
| 2101 | * |
| 2102 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 2103 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 2104 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 2105 | * without holding struct_mutex the object may become re-busied before this |
| 2106 | * function completes. A similar but shorter * race condition exists in the busy |
| 2107 | * ioctl |
| 2108 | */ |
| 2109 | int |
| 2110 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 2111 | { |
| 2112 | struct drm_i915_gem_wait *args = data; |
| 2113 | struct drm_i915_gem_object *obj; |
| 2114 | struct intel_ring_buffer *ring = NULL; |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2115 | struct timespec timeout_stack, *timeout = NULL; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2116 | u32 seqno = 0; |
| 2117 | int ret = 0; |
| 2118 | |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2119 | if (args->timeout_ns >= 0) { |
| 2120 | timeout_stack = ns_to_timespec(args->timeout_ns); |
| 2121 | timeout = &timeout_stack; |
| 2122 | } |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2123 | |
| 2124 | ret = i915_mutex_lock_interruptible(dev); |
| 2125 | if (ret) |
| 2126 | return ret; |
| 2127 | |
| 2128 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 2129 | if (&obj->base == NULL) { |
| 2130 | mutex_unlock(&dev->struct_mutex); |
| 2131 | return -ENOENT; |
| 2132 | } |
| 2133 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2134 | /* Need to make sure the object gets inactive eventually. */ |
| 2135 | ret = i915_gem_object_flush_active(obj); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2136 | if (ret) |
| 2137 | goto out; |
| 2138 | |
| 2139 | if (obj->active) { |
| 2140 | seqno = obj->last_rendering_seqno; |
| 2141 | ring = obj->ring; |
| 2142 | } |
| 2143 | |
| 2144 | if (seqno == 0) |
| 2145 | goto out; |
| 2146 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2147 | /* Do this after OLR check to make sure we make forward progress polling |
| 2148 | * on this IOCTL with a 0 timeout (like busy ioctl) |
| 2149 | */ |
| 2150 | if (!args->timeout_ns) { |
| 2151 | ret = -ETIME; |
| 2152 | goto out; |
| 2153 | } |
| 2154 | |
| 2155 | drm_gem_object_unreference(&obj->base); |
| 2156 | mutex_unlock(&dev->struct_mutex); |
| 2157 | |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2158 | ret = __wait_seqno(ring, seqno, true, timeout); |
| 2159 | if (timeout) { |
| 2160 | WARN_ON(!timespec_valid(timeout)); |
| 2161 | args->timeout_ns = timespec_to_ns(timeout); |
| 2162 | } |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2163 | return ret; |
| 2164 | |
| 2165 | out: |
| 2166 | drm_gem_object_unreference(&obj->base); |
| 2167 | mutex_unlock(&dev->struct_mutex); |
| 2168 | return ret; |
| 2169 | } |
| 2170 | |
| 2171 | /** |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2172 | * i915_gem_object_sync - sync an object to a ring. |
| 2173 | * |
| 2174 | * @obj: object which may be in use on another ring. |
| 2175 | * @to: ring we wish to use the object on. May be NULL. |
| 2176 | * |
| 2177 | * This code is meant to abstract object synchronization with the GPU. |
| 2178 | * Calling with NULL implies synchronizing the object with the CPU |
| 2179 | * rather than a particular GPU ring. |
| 2180 | * |
| 2181 | * Returns 0 if successful, else propagates up the lower layer error. |
| 2182 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2183 | int |
| 2184 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 2185 | struct intel_ring_buffer *to) |
| 2186 | { |
| 2187 | struct intel_ring_buffer *from = obj->ring; |
| 2188 | u32 seqno; |
| 2189 | int ret, idx; |
| 2190 | |
| 2191 | if (from == NULL || to == from) |
| 2192 | return 0; |
| 2193 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2194 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2195 | return i915_gem_object_wait_rendering(obj); |
| 2196 | |
| 2197 | idx = intel_ring_sync_index(from, to); |
| 2198 | |
| 2199 | seqno = obj->last_rendering_seqno; |
| 2200 | if (seqno <= from->sync_seqno[idx]) |
| 2201 | return 0; |
| 2202 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 2203 | ret = i915_gem_check_olr(obj->ring, seqno); |
| 2204 | if (ret) |
| 2205 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2206 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 2207 | ret = to->sync_to(to, from, seqno); |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2208 | if (!ret) |
| 2209 | from->sync_seqno[idx] = seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2210 | |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2211 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2212 | } |
| 2213 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2214 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 2215 | { |
| 2216 | u32 old_write_domain, old_read_domains; |
| 2217 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2218 | /* Act a barrier for all accesses through the GTT */ |
| 2219 | mb(); |
| 2220 | |
| 2221 | /* Force a pagefault for domain tracking on next user access */ |
| 2222 | i915_gem_release_mmap(obj); |
| 2223 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 2224 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 2225 | return; |
| 2226 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2227 | old_read_domains = obj->base.read_domains; |
| 2228 | old_write_domain = obj->base.write_domain; |
| 2229 | |
| 2230 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 2231 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 2232 | |
| 2233 | trace_i915_gem_object_change_domain(obj, |
| 2234 | old_read_domains, |
| 2235 | old_write_domain); |
| 2236 | } |
| 2237 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2238 | /** |
| 2239 | * Unbinds an object from the GTT aperture. |
| 2240 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2241 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2242 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2243 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2244 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2245 | int ret = 0; |
| 2246 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2247 | if (obj->gtt_space == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2248 | return 0; |
| 2249 | |
Chris Wilson | 31d8d65 | 2012-05-24 19:11:20 +0100 | [diff] [blame] | 2250 | if (obj->pin_count) |
| 2251 | return -EBUSY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2252 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2253 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2254 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2255 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2256 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2257 | * should be safe and we need to cleanup or else we might |
| 2258 | * cause memory corruption through use-after-free. |
| 2259 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2260 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2261 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2262 | |
| 2263 | /* Move the object to the CPU domain to ensure that |
| 2264 | * any possible CPU writes while it's not in the GTT |
| 2265 | * are flushed when we go to remap it. |
| 2266 | */ |
| 2267 | if (ret == 0) |
| 2268 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 2269 | if (ret == -ERESTARTSYS) |
| 2270 | return ret; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2271 | if (ret) { |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2272 | /* In the event of a disaster, abandon all caches and |
| 2273 | * hope for the best. |
| 2274 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2275 | i915_gem_clflush_object(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2276 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2277 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2278 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2279 | /* release the fence reg _after_ flushing */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2280 | ret = i915_gem_object_put_fence(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2281 | if (ret) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2282 | return ret; |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2283 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2284 | trace_i915_gem_object_unbind(obj); |
| 2285 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 2286 | if (obj->has_global_gtt_mapping) |
| 2287 | i915_gem_gtt_unbind_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2288 | if (obj->has_aliasing_ppgtt_mapping) { |
| 2289 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); |
| 2290 | obj->has_aliasing_ppgtt_mapping = 0; |
| 2291 | } |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2292 | i915_gem_gtt_finish_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2293 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2294 | i915_gem_object_put_pages_gtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2295 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2296 | list_del_init(&obj->gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2297 | list_del_init(&obj->mm_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2298 | /* Avoid an unnecessary call to unbind on rebind. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2299 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2300 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2301 | drm_mm_put_block(obj->gtt_space); |
| 2302 | obj->gtt_space = NULL; |
| 2303 | obj->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2304 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2305 | if (i915_gem_object_is_purgeable(obj)) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2306 | i915_gem_object_truncate(obj); |
| 2307 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2308 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2309 | } |
| 2310 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2311 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2312 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2313 | uint32_t invalidate_domains, |
| 2314 | uint32_t flush_domains) |
| 2315 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2316 | int ret; |
| 2317 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 2318 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
| 2319 | return 0; |
| 2320 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2321 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
| 2322 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2323 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
| 2324 | if (ret) |
| 2325 | return ret; |
| 2326 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 2327 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
| 2328 | i915_gem_process_flushing_list(ring, flush_domains); |
| 2329 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2330 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2331 | } |
| 2332 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2333 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2334 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2335 | int ret; |
| 2336 | |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2337 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2338 | return 0; |
| 2339 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2340 | if (!list_empty(&ring->gpu_write_list)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2341 | ret = i915_gem_flush_ring(ring, |
Chris Wilson | 0ac74c6 | 2010-12-06 14:36:02 +0000 | [diff] [blame] | 2342 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2343 | if (ret) |
| 2344 | return ret; |
| 2345 | } |
| 2346 | |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 2347 | return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring)); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2348 | } |
| 2349 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2350 | int i915_gpu_idle(struct drm_device *dev) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2351 | { |
| 2352 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2353 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2354 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2355 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2356 | /* Flush everything onto the inactive list. */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2357 | for_each_ring(ring, dev_priv, i) { |
| 2358 | ret = i915_ring_idle(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2359 | if (ret) |
| 2360 | return ret; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2361 | |
| 2362 | /* Is the device fubar? */ |
| 2363 | if (WARN_ON(!list_empty(&ring->gpu_write_list))) |
| 2364 | return -EBUSY; |
Ben Widawsky | f2ef6eb | 2012-06-04 14:42:53 -0700 | [diff] [blame] | 2365 | |
| 2366 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
| 2367 | if (ret) |
| 2368 | return ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2369 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2370 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2371 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2372 | } |
| 2373 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2374 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
| 2375 | struct drm_i915_gem_object *obj) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2376 | { |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2377 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2378 | uint64_t val; |
| 2379 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2380 | if (obj) { |
| 2381 | u32 size = obj->gtt_space->size; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2382 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2383 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
| 2384 | 0xfffff000) << 32; |
| 2385 | val |= obj->gtt_offset & 0xfffff000; |
| 2386 | val |= (uint64_t)((obj->stride / 128) - 1) << |
| 2387 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2388 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2389 | if (obj->tiling_mode == I915_TILING_Y) |
| 2390 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2391 | val |= I965_FENCE_REG_VALID; |
| 2392 | } else |
| 2393 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2394 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2395 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
| 2396 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2397 | } |
| 2398 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2399 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 2400 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2401 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2402 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2403 | uint64_t val; |
| 2404 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2405 | if (obj) { |
| 2406 | u32 size = obj->gtt_space->size; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2407 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2408 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
| 2409 | 0xfffff000) << 32; |
| 2410 | val |= obj->gtt_offset & 0xfffff000; |
| 2411 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2412 | if (obj->tiling_mode == I915_TILING_Y) |
| 2413 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2414 | val |= I965_FENCE_REG_VALID; |
| 2415 | } else |
| 2416 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2417 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2418 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
| 2419 | POSTING_READ(FENCE_REG_965_0 + reg * 8); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2420 | } |
| 2421 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2422 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 2423 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2424 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2425 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2426 | u32 val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2427 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2428 | if (obj) { |
| 2429 | u32 size = obj->gtt_space->size; |
| 2430 | int pitch_val; |
| 2431 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2432 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2433 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2434 | (size & -size) != size || |
| 2435 | (obj->gtt_offset & (size - 1)), |
| 2436 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2437 | obj->gtt_offset, obj->map_and_fenceable, size); |
| 2438 | |
| 2439 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 2440 | tile_width = 128; |
| 2441 | else |
| 2442 | tile_width = 512; |
| 2443 | |
| 2444 | /* Note: pitch better be a power of two tile widths */ |
| 2445 | pitch_val = obj->stride / tile_width; |
| 2446 | pitch_val = ffs(pitch_val) - 1; |
| 2447 | |
| 2448 | val = obj->gtt_offset; |
| 2449 | if (obj->tiling_mode == I915_TILING_Y) |
| 2450 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2451 | val |= I915_FENCE_SIZE_BITS(size); |
| 2452 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2453 | val |= I830_FENCE_REG_VALID; |
| 2454 | } else |
| 2455 | val = 0; |
| 2456 | |
| 2457 | if (reg < 8) |
| 2458 | reg = FENCE_REG_830_0 + reg * 4; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2459 | else |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2460 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2461 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2462 | I915_WRITE(reg, val); |
| 2463 | POSTING_READ(reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2464 | } |
| 2465 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2466 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 2467 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2468 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2469 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2470 | uint32_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2471 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2472 | if (obj) { |
| 2473 | u32 size = obj->gtt_space->size; |
| 2474 | uint32_t pitch_val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2475 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2476 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
| 2477 | (size & -size) != size || |
| 2478 | (obj->gtt_offset & (size - 1)), |
| 2479 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", |
| 2480 | obj->gtt_offset, size); |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2481 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2482 | pitch_val = obj->stride / 128; |
| 2483 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2484 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2485 | val = obj->gtt_offset; |
| 2486 | if (obj->tiling_mode == I915_TILING_Y) |
| 2487 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2488 | val |= I830_FENCE_SIZE_BITS(size); |
| 2489 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2490 | val |= I830_FENCE_REG_VALID; |
| 2491 | } else |
| 2492 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2493 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2494 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 2495 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 2496 | } |
| 2497 | |
| 2498 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 2499 | struct drm_i915_gem_object *obj) |
| 2500 | { |
| 2501 | switch (INTEL_INFO(dev)->gen) { |
| 2502 | case 7: |
| 2503 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; |
| 2504 | case 5: |
| 2505 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
| 2506 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
| 2507 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
| 2508 | default: break; |
| 2509 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2510 | } |
| 2511 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2512 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 2513 | struct drm_i915_fence_reg *fence) |
| 2514 | { |
| 2515 | return fence - dev_priv->fence_regs; |
| 2516 | } |
| 2517 | |
| 2518 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 2519 | struct drm_i915_fence_reg *fence, |
| 2520 | bool enable) |
| 2521 | { |
| 2522 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2523 | int reg = fence_number(dev_priv, fence); |
| 2524 | |
| 2525 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
| 2526 | |
| 2527 | if (enable) { |
| 2528 | obj->fence_reg = reg; |
| 2529 | fence->obj = obj; |
| 2530 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 2531 | } else { |
| 2532 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 2533 | fence->obj = NULL; |
| 2534 | list_del_init(&fence->lru_list); |
| 2535 | } |
| 2536 | } |
| 2537 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2538 | static int |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2539 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2540 | { |
| 2541 | int ret; |
| 2542 | |
| 2543 | if (obj->fenced_gpu_access) { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2544 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 2545 | ret = i915_gem_flush_ring(obj->ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2546 | 0, obj->base.write_domain); |
| 2547 | if (ret) |
| 2548 | return ret; |
| 2549 | } |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2550 | |
| 2551 | obj->fenced_gpu_access = false; |
| 2552 | } |
| 2553 | |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 2554 | if (obj->last_fenced_seqno) { |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 2555 | ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
Chris Wilson | 1899184 | 2012-04-17 15:31:29 +0100 | [diff] [blame] | 2556 | if (ret) |
| 2557 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2558 | |
| 2559 | obj->last_fenced_seqno = 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2560 | } |
| 2561 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2562 | /* Ensure that all CPU reads are completed before installing a fence |
| 2563 | * and all writes before removing the fence. |
| 2564 | */ |
| 2565 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) |
| 2566 | mb(); |
| 2567 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2568 | return 0; |
| 2569 | } |
| 2570 | |
| 2571 | int |
| 2572 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 2573 | { |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2574 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2575 | int ret; |
| 2576 | |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2577 | ret = i915_gem_object_flush_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2578 | if (ret) |
| 2579 | return ret; |
| 2580 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2581 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 2582 | return 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2583 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2584 | i915_gem_object_update_fence(obj, |
| 2585 | &dev_priv->fence_regs[obj->fence_reg], |
| 2586 | false); |
| 2587 | i915_gem_object_fence_lost(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2588 | |
| 2589 | return 0; |
| 2590 | } |
| 2591 | |
| 2592 | static struct drm_i915_fence_reg * |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2593 | i915_find_fence_reg(struct drm_device *dev) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2594 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2595 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2596 | struct drm_i915_fence_reg *reg, *avail; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2597 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2598 | |
| 2599 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2600 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2601 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2602 | reg = &dev_priv->fence_regs[i]; |
| 2603 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2604 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2605 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2606 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2607 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2608 | } |
| 2609 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2610 | if (avail == NULL) |
| 2611 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2612 | |
| 2613 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2614 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2615 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2616 | continue; |
| 2617 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2618 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2619 | } |
| 2620 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2621 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2622 | } |
| 2623 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2624 | /** |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2625 | * i915_gem_object_get_fence - set up fencing for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2626 | * @obj: object to map through a fence reg |
| 2627 | * |
| 2628 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2629 | * to them without having to worry about swizzling if the object is tiled. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2630 | * This function walks the fence regs looking for a free one for @obj, |
| 2631 | * stealing one if it can't find any. |
| 2632 | * |
| 2633 | * It then sets up the reg based on the object's properties: address, pitch |
| 2634 | * and tiling format. |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2635 | * |
| 2636 | * For an untiled surface, this removes any existing fence. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2637 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2638 | int |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 2639 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2640 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2641 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2642 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2643 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2644 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2645 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2646 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2647 | /* Have we updated the tiling parameters upon the object and so |
| 2648 | * will need to serialise the write to the associated fence register? |
| 2649 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2650 | if (obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2651 | ret = i915_gem_object_flush_fence(obj); |
| 2652 | if (ret) |
| 2653 | return ret; |
| 2654 | } |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2655 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2656 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2657 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2658 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2659 | if (!obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2660 | list_move_tail(®->lru_list, |
| 2661 | &dev_priv->mm.fence_list); |
| 2662 | return 0; |
| 2663 | } |
| 2664 | } else if (enable) { |
| 2665 | reg = i915_find_fence_reg(dev); |
| 2666 | if (reg == NULL) |
| 2667 | return -EDEADLK; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2668 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2669 | if (reg->obj) { |
| 2670 | struct drm_i915_gem_object *old = reg->obj; |
| 2671 | |
| 2672 | ret = i915_gem_object_flush_fence(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2673 | if (ret) |
| 2674 | return ret; |
| 2675 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2676 | i915_gem_object_fence_lost(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2677 | } |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2678 | } else |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2679 | return 0; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2680 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2681 | i915_gem_object_update_fence(obj, reg, enable); |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2682 | obj->fence_dirty = false; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2683 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2684 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2685 | } |
| 2686 | |
| 2687 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2688 | * Finds free space in the GTT aperture and binds the object there. |
| 2689 | */ |
| 2690 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2691 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2692 | unsigned alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2693 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2694 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2695 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2696 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2697 | struct drm_mm_node *free_space; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2698 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2699 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2700 | bool mappable, fenceable; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2701 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2702 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2703 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2704 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2705 | return -EINVAL; |
| 2706 | } |
| 2707 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2708 | fence_size = i915_gem_get_gtt_size(dev, |
| 2709 | obj->base.size, |
| 2710 | obj->tiling_mode); |
| 2711 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 2712 | obj->base.size, |
| 2713 | obj->tiling_mode); |
| 2714 | unfenced_alignment = |
| 2715 | i915_gem_get_unfenced_gtt_alignment(dev, |
| 2716 | obj->base.size, |
| 2717 | obj->tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2718 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2719 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2720 | alignment = map_and_fenceable ? fence_alignment : |
| 2721 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2722 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2723 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2724 | return -EINVAL; |
| 2725 | } |
| 2726 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2727 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2728 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2729 | /* If the object is bigger than the entire aperture, reject it early |
| 2730 | * before evicting everything in a vain attempt to find space. |
| 2731 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2732 | if (obj->base.size > |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2733 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2734 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2735 | return -E2BIG; |
| 2736 | } |
| 2737 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2738 | search_free: |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2739 | if (map_and_fenceable) |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2740 | free_space = |
| 2741 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
Chris Wilson | 6b9d89b | 2012-07-10 11:15:23 +0100 | [diff] [blame] | 2742 | size, alignment, |
| 2743 | 0, dev_priv->mm.gtt_mappable_end, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2744 | 0); |
| 2745 | else |
| 2746 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2747 | size, alignment, 0); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2748 | |
| 2749 | if (free_space != NULL) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2750 | if (map_and_fenceable) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2751 | obj->gtt_space = |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2752 | drm_mm_get_block_range_generic(free_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2753 | size, alignment, 0, |
Chris Wilson | 6b9d89b | 2012-07-10 11:15:23 +0100 | [diff] [blame] | 2754 | 0, dev_priv->mm.gtt_mappable_end, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2755 | 0); |
| 2756 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2757 | obj->gtt_space = |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2758 | drm_mm_get_block(free_space, size, alignment); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2759 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2760 | if (obj->gtt_space == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2761 | /* If the gtt is empty and we're still having trouble |
| 2762 | * fitting our object in, we're out of memory. |
| 2763 | */ |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2764 | ret = i915_gem_evict_something(dev, size, alignment, |
| 2765 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2766 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2767 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2768 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2769 | goto search_free; |
| 2770 | } |
| 2771 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2772 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2773 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2774 | drm_mm_put_block(obj->gtt_space); |
| 2775 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2776 | |
| 2777 | if (ret == -ENOMEM) { |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2778 | /* first try to reclaim some memory by clearing the GTT */ |
| 2779 | ret = i915_gem_evict_everything(dev, false); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2780 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2781 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2782 | if (gfpmask) { |
| 2783 | gfpmask = 0; |
| 2784 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2785 | } |
| 2786 | |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2787 | return -ENOMEM; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2788 | } |
| 2789 | |
| 2790 | goto search_free; |
| 2791 | } |
| 2792 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2793 | return ret; |
| 2794 | } |
| 2795 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2796 | ret = i915_gem_gtt_prepare_object(obj); |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2797 | if (ret) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2798 | i915_gem_object_put_pages_gtt(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2799 | drm_mm_put_block(obj->gtt_space); |
| 2800 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2801 | |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2802 | if (i915_gem_evict_everything(dev, false)) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2803 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2804 | |
| 2805 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2806 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2807 | |
Daniel Vetter | 0ebb982 | 2012-02-15 23:50:24 +0100 | [diff] [blame] | 2808 | if (!dev_priv->mm.aliasing_ppgtt) |
| 2809 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2810 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2811 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2812 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2813 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2814 | /* Assert that the object is not currently in any GPU domain. As it |
| 2815 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2816 | * a GPU cache |
| 2817 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2818 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2819 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2820 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2821 | obj->gtt_offset = obj->gtt_space->start; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2822 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2823 | fenceable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2824 | obj->gtt_space->size == fence_size && |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2825 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2826 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2827 | mappable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2828 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2829 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2830 | obj->map_and_fenceable = mappable && fenceable; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2831 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2832 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2833 | return 0; |
| 2834 | } |
| 2835 | |
| 2836 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2837 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2838 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2839 | /* If we don't have a page list set up, then we're not pinned |
| 2840 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2841 | * again at bind time. |
| 2842 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2843 | if (obj->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2844 | return; |
| 2845 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 2846 | /* If the GPU is snooping the contents of the CPU cache, |
| 2847 | * we do not need to manually clear the CPU cache lines. However, |
| 2848 | * the caches are only snooped when the render cache is |
| 2849 | * flushed/invalidated. As we always have to emit invalidations |
| 2850 | * and flushes when moving into and out of the RENDER domain, correct |
| 2851 | * snooping behaviour occurs naturally as the result of our domain |
| 2852 | * tracking. |
| 2853 | */ |
| 2854 | if (obj->cache_level != I915_CACHE_NONE) |
| 2855 | return; |
| 2856 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2857 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2858 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2859 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2860 | } |
| 2861 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2862 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2863 | static int |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2864 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2865 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2866 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2867 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2868 | |
| 2869 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2870 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2871 | } |
| 2872 | |
| 2873 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2874 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2875 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2876 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2877 | uint32_t old_write_domain; |
| 2878 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2879 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2880 | return; |
| 2881 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2882 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2883 | * to it immediately go to main memory as far as we know, so there's |
| 2884 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2885 | * |
| 2886 | * However, we do have to enforce the order so that all writes through |
| 2887 | * the GTT land before any writes to the device, such as updates to |
| 2888 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2889 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2890 | wmb(); |
| 2891 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2892 | old_write_domain = obj->base.write_domain; |
| 2893 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2894 | |
| 2895 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2896 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2897 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2898 | } |
| 2899 | |
| 2900 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2901 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2902 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2903 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2904 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2905 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2906 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2907 | return; |
| 2908 | |
| 2909 | i915_gem_clflush_object(obj); |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 2910 | intel_gtt_chipset_flush(); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2911 | old_write_domain = obj->base.write_domain; |
| 2912 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2913 | |
| 2914 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2915 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2916 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2917 | } |
| 2918 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2919 | /** |
| 2920 | * Moves a single object to the GTT read, and possibly write domain. |
| 2921 | * |
| 2922 | * This function returns when the move is complete, including waiting on |
| 2923 | * flushes to occur. |
| 2924 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2925 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2926 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2927 | { |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 2928 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2929 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2930 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2931 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2932 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2933 | if (obj->gtt_space == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2934 | return -EINVAL; |
| 2935 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 2936 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 2937 | return 0; |
| 2938 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2939 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2940 | if (ret) |
| 2941 | return ret; |
| 2942 | |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 2943 | if (obj->pending_gpu_write || write) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2944 | ret = i915_gem_object_wait_rendering(obj); |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 2945 | if (ret) |
| 2946 | return ret; |
| 2947 | } |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2948 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2949 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2950 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2951 | old_write_domain = obj->base.write_domain; |
| 2952 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2953 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2954 | /* It should now be out of any other write domains, and we can update |
| 2955 | * the domain values for our changes. |
| 2956 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2957 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2958 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2959 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2960 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 2961 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 2962 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2963 | } |
| 2964 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2965 | trace_i915_gem_object_change_domain(obj, |
| 2966 | old_read_domains, |
| 2967 | old_write_domain); |
| 2968 | |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 2969 | /* And bump the LRU for this access */ |
| 2970 | if (i915_gem_object_is_inactive(obj)) |
| 2971 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 2972 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2973 | return 0; |
| 2974 | } |
| 2975 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2976 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 2977 | enum i915_cache_level cache_level) |
| 2978 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2979 | struct drm_device *dev = obj->base.dev; |
| 2980 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2981 | int ret; |
| 2982 | |
| 2983 | if (obj->cache_level == cache_level) |
| 2984 | return 0; |
| 2985 | |
| 2986 | if (obj->pin_count) { |
| 2987 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 2988 | return -EBUSY; |
| 2989 | } |
| 2990 | |
| 2991 | if (obj->gtt_space) { |
| 2992 | ret = i915_gem_object_finish_gpu(obj); |
| 2993 | if (ret) |
| 2994 | return ret; |
| 2995 | |
| 2996 | i915_gem_object_finish_gtt(obj); |
| 2997 | |
| 2998 | /* Before SandyBridge, you could not use tiling or fence |
| 2999 | * registers with snooped memory, so relinquish any fences |
| 3000 | * currently pointing to our region in the aperture. |
| 3001 | */ |
| 3002 | if (INTEL_INFO(obj->base.dev)->gen < 6) { |
| 3003 | ret = i915_gem_object_put_fence(obj); |
| 3004 | if (ret) |
| 3005 | return ret; |
| 3006 | } |
| 3007 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3008 | if (obj->has_global_gtt_mapping) |
| 3009 | i915_gem_gtt_bind_object(obj, cache_level); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3010 | if (obj->has_aliasing_ppgtt_mapping) |
| 3011 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
| 3012 | obj, cache_level); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3013 | } |
| 3014 | |
| 3015 | if (cache_level == I915_CACHE_NONE) { |
| 3016 | u32 old_read_domains, old_write_domain; |
| 3017 | |
| 3018 | /* If we're coming from LLC cached, then we haven't |
| 3019 | * actually been tracking whether the data is in the |
| 3020 | * CPU cache or not, since we only allow one bit set |
| 3021 | * in obj->write_domain and have been skipping the clflushes. |
| 3022 | * Just set it to the CPU cache for now. |
| 3023 | */ |
| 3024 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
| 3025 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); |
| 3026 | |
| 3027 | old_read_domains = obj->base.read_domains; |
| 3028 | old_write_domain = obj->base.write_domain; |
| 3029 | |
| 3030 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3031 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3032 | |
| 3033 | trace_i915_gem_object_change_domain(obj, |
| 3034 | old_read_domains, |
| 3035 | old_write_domain); |
| 3036 | } |
| 3037 | |
| 3038 | obj->cache_level = cache_level; |
| 3039 | return 0; |
| 3040 | } |
| 3041 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3042 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3043 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 3044 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 3045 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3046 | */ |
| 3047 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3048 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 3049 | u32 alignment, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3050 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3051 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3052 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3053 | int ret; |
| 3054 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3055 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 3056 | if (ret) |
| 3057 | return ret; |
| 3058 | |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 3059 | if (pipelined != obj->ring) { |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3060 | ret = i915_gem_object_sync(obj, pipelined); |
| 3061 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3062 | return ret; |
| 3063 | } |
| 3064 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3065 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 3066 | * a result, we make sure that the pinning that is about to occur is |
| 3067 | * done with uncached PTEs. This is lowest common denominator for all |
| 3068 | * chipsets. |
| 3069 | * |
| 3070 | * However for gen6+, we could do better by using the GFDT bit instead |
| 3071 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 3072 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 3073 | */ |
| 3074 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); |
| 3075 | if (ret) |
| 3076 | return ret; |
| 3077 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3078 | /* As the user may map the buffer once pinned in the display plane |
| 3079 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 3080 | * always use map_and_fenceable for all scanout buffers. |
| 3081 | */ |
| 3082 | ret = i915_gem_object_pin(obj, alignment, true); |
| 3083 | if (ret) |
| 3084 | return ret; |
| 3085 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3086 | i915_gem_object_flush_cpu_write_domain(obj); |
| 3087 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3088 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3089 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3090 | |
| 3091 | /* It should now be out of any other write domains, and we can update |
| 3092 | * the domain values for our changes. |
| 3093 | */ |
| 3094 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3095 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3096 | |
| 3097 | trace_i915_gem_object_change_domain(obj, |
| 3098 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3099 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3100 | |
| 3101 | return 0; |
| 3102 | } |
| 3103 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3104 | int |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3105 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3106 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3107 | int ret; |
| 3108 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3109 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3110 | return 0; |
| 3111 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3112 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3113 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3114 | if (ret) |
| 3115 | return ret; |
| 3116 | } |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3117 | |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3118 | ret = i915_gem_object_wait_rendering(obj); |
| 3119 | if (ret) |
| 3120 | return ret; |
| 3121 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3122 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 3123 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3124 | return 0; |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3125 | } |
| 3126 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3127 | /** |
| 3128 | * Moves a single object to the CPU read, and possibly write domain. |
| 3129 | * |
| 3130 | * This function returns when the move is complete, including waiting on |
| 3131 | * flushes to occur. |
| 3132 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 3133 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3134 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3135 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3136 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3137 | int ret; |
| 3138 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3139 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 3140 | return 0; |
| 3141 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3142 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 3143 | if (ret) |
| 3144 | return ret; |
| 3145 | |
Chris Wilson | f841319 | 2012-04-10 11:52:50 +0100 | [diff] [blame] | 3146 | if (write || obj->pending_gpu_write) { |
| 3147 | ret = i915_gem_object_wait_rendering(obj); |
| 3148 | if (ret) |
| 3149 | return ret; |
| 3150 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3151 | |
| 3152 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3153 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3154 | old_write_domain = obj->base.write_domain; |
| 3155 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3156 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3157 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3158 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3159 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3160 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3161 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3162 | } |
| 3163 | |
| 3164 | /* It should now be out of any other write domains, and we can update |
| 3165 | * the domain values for our changes. |
| 3166 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3167 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3168 | |
| 3169 | /* If we're writing through the CPU, then the GPU read domains will |
| 3170 | * need to be invalidated at next use. |
| 3171 | */ |
| 3172 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3173 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3174 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3175 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3176 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3177 | trace_i915_gem_object_change_domain(obj, |
| 3178 | old_read_domains, |
| 3179 | old_write_domain); |
| 3180 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3181 | return 0; |
| 3182 | } |
| 3183 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3184 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3185 | * emitted over 20 msec ago. |
| 3186 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3187 | * Note that if we were to use the current jiffies each time around the loop, |
| 3188 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3189 | * render a frame was over 20ms. |
| 3190 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3191 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3192 | * relatively low latency when blocking on a particular request to finish. |
| 3193 | */ |
| 3194 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3195 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3196 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3197 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3198 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3199 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3200 | struct drm_i915_gem_request *request; |
| 3201 | struct intel_ring_buffer *ring = NULL; |
| 3202 | u32 seqno = 0; |
| 3203 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3204 | |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 3205 | if (atomic_read(&dev_priv->mm.wedged)) |
| 3206 | return -EIO; |
| 3207 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3208 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3209 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3210 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3211 | break; |
| 3212 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3213 | ring = request->ring; |
| 3214 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3215 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3216 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3217 | |
| 3218 | if (seqno == 0) |
| 3219 | return 0; |
| 3220 | |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 3221 | ret = __wait_seqno(ring, seqno, true, NULL); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3222 | if (ret == 0) |
| 3223 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3224 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3225 | return ret; |
| 3226 | } |
| 3227 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3228 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3229 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 3230 | uint32_t alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3231 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3232 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3233 | int ret; |
| 3234 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3235 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3236 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3237 | if (obj->gtt_space != NULL) { |
| 3238 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
| 3239 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 3240 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 3241 | "bo is already pinned with incorrect alignment:" |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3242 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
| 3243 | " obj->map_and_fenceable=%d\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3244 | obj->gtt_offset, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3245 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3246 | obj->map_and_fenceable); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3247 | ret = i915_gem_object_unbind(obj); |
| 3248 | if (ret) |
| 3249 | return ret; |
| 3250 | } |
| 3251 | } |
| 3252 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3253 | if (obj->gtt_space == NULL) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3254 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3255 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3256 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3257 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3258 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3259 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3260 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
| 3261 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 3262 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3263 | obj->pin_count++; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3264 | obj->pin_mappable |= map_and_fenceable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3265 | |
| 3266 | return 0; |
| 3267 | } |
| 3268 | |
| 3269 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3270 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3271 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3272 | BUG_ON(obj->pin_count == 0); |
| 3273 | BUG_ON(obj->gtt_space == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3274 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3275 | if (--obj->pin_count == 0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3276 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3277 | } |
| 3278 | |
| 3279 | int |
| 3280 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3281 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3282 | { |
| 3283 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3284 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3285 | int ret; |
| 3286 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3287 | ret = i915_mutex_lock_interruptible(dev); |
| 3288 | if (ret) |
| 3289 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3290 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3291 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3292 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3293 | ret = -ENOENT; |
| 3294 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3295 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3296 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3297 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3298 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3299 | ret = -EINVAL; |
| 3300 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3301 | } |
| 3302 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3303 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3304 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3305 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3306 | ret = -EINVAL; |
| 3307 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3308 | } |
| 3309 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3310 | obj->user_pin_count++; |
| 3311 | obj->pin_filp = file; |
| 3312 | if (obj->user_pin_count == 1) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3313 | ret = i915_gem_object_pin(obj, args->alignment, true); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3314 | if (ret) |
| 3315 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3316 | } |
| 3317 | |
| 3318 | /* XXX - flush the CPU caches for pinned objects |
| 3319 | * as the X server doesn't manage domains yet |
| 3320 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3321 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3322 | args->offset = obj->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3323 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3324 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3325 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3326 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3327 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3328 | } |
| 3329 | |
| 3330 | int |
| 3331 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3332 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3333 | { |
| 3334 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3335 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3336 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3337 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3338 | ret = i915_mutex_lock_interruptible(dev); |
| 3339 | if (ret) |
| 3340 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3341 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3342 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3343 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3344 | ret = -ENOENT; |
| 3345 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3346 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3347 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3348 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3349 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 3350 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3351 | ret = -EINVAL; |
| 3352 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3353 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3354 | obj->user_pin_count--; |
| 3355 | if (obj->user_pin_count == 0) { |
| 3356 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3357 | i915_gem_object_unpin(obj); |
| 3358 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3359 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3360 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3361 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3362 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3363 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3364 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3365 | } |
| 3366 | |
| 3367 | int |
| 3368 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3369 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3370 | { |
| 3371 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3372 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3373 | int ret; |
| 3374 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3375 | ret = i915_mutex_lock_interruptible(dev); |
| 3376 | if (ret) |
| 3377 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3378 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3379 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3380 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3381 | ret = -ENOENT; |
| 3382 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3383 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3384 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3385 | /* Count all active objects as busy, even if they are currently not used |
| 3386 | * by the gpu. Users of this interface expect objects to eventually |
| 3387 | * become non-busy without any further actions, therefore emit any |
| 3388 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 3389 | */ |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3390 | ret = i915_gem_object_flush_active(obj); |
| 3391 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3392 | args->busy = obj->active; |
Chris Wilson | e9808ed | 2012-07-04 12:25:08 +0100 | [diff] [blame] | 3393 | if (obj->ring) { |
| 3394 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
| 3395 | args->busy |= intel_ring_flag(obj->ring) << 16; |
| 3396 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3397 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3398 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3399 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3400 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3401 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3402 | } |
| 3403 | |
| 3404 | int |
| 3405 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 3406 | struct drm_file *file_priv) |
| 3407 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3408 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3409 | } |
| 3410 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3411 | int |
| 3412 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 3413 | struct drm_file *file_priv) |
| 3414 | { |
| 3415 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3416 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3417 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3418 | |
| 3419 | switch (args->madv) { |
| 3420 | case I915_MADV_DONTNEED: |
| 3421 | case I915_MADV_WILLNEED: |
| 3422 | break; |
| 3423 | default: |
| 3424 | return -EINVAL; |
| 3425 | } |
| 3426 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3427 | ret = i915_mutex_lock_interruptible(dev); |
| 3428 | if (ret) |
| 3429 | return ret; |
| 3430 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3431 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3432 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3433 | ret = -ENOENT; |
| 3434 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3435 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3436 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3437 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3438 | ret = -EINVAL; |
| 3439 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3440 | } |
| 3441 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3442 | if (obj->madv != __I915_MADV_PURGED) |
| 3443 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3444 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3445 | /* if the object is no longer bound, discard its backing storage */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3446 | if (i915_gem_object_is_purgeable(obj) && |
| 3447 | obj->gtt_space == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3448 | i915_gem_object_truncate(obj); |
| 3449 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3450 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3451 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3452 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3453 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3454 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3455 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3456 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3457 | } |
| 3458 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3459 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 3460 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3461 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3462 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3463 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3464 | struct address_space *mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 3465 | u32 mask; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3466 | |
| 3467 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 3468 | if (obj == NULL) |
| 3469 | return NULL; |
| 3470 | |
| 3471 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 3472 | kfree(obj); |
| 3473 | return NULL; |
| 3474 | } |
| 3475 | |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 3476 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 3477 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 3478 | /* 965gm cannot relocate objects above 4GiB. */ |
| 3479 | mask &= ~__GFP_HIGHMEM; |
| 3480 | mask |= __GFP_DMA32; |
| 3481 | } |
| 3482 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3483 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 3484 | mapping_set_gfp_mask(mapping, mask); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3485 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3486 | i915_gem_info_add_obj(dev_priv, size); |
| 3487 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3488 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3489 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3490 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 3491 | if (HAS_LLC(dev)) { |
| 3492 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 3493 | * cache) for about a 10% performance improvement |
| 3494 | * compared to uncached. Graphics requests other than |
| 3495 | * display scanout are coherent with the CPU in |
| 3496 | * accessing this cache. This means in this mode we |
| 3497 | * don't need to clflush on the CPU side, and on the |
| 3498 | * GPU side we only need to flush internal caches to |
| 3499 | * get data visible to the CPU. |
| 3500 | * |
| 3501 | * However, we maintain the display planes as UC, and so |
| 3502 | * need to rebind when first used as such. |
| 3503 | */ |
| 3504 | obj->cache_level = I915_CACHE_LLC; |
| 3505 | } else |
| 3506 | obj->cache_level = I915_CACHE_NONE; |
| 3507 | |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 3508 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3509 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3510 | INIT_LIST_HEAD(&obj->mm_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3511 | INIT_LIST_HEAD(&obj->gtt_list); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3512 | INIT_LIST_HEAD(&obj->ring_list); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 3513 | INIT_LIST_HEAD(&obj->exec_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3514 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3515 | obj->madv = I915_MADV_WILLNEED; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3516 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 3517 | obj->map_and_fenceable = true; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3518 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3519 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3520 | } |
| 3521 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3522 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 3523 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3524 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3525 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3526 | return 0; |
| 3527 | } |
| 3528 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3529 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3530 | { |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3531 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3532 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3533 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3534 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 3535 | trace_i915_gem_object_destroy(obj); |
| 3536 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 3537 | if (gem_obj->import_attach) |
| 3538 | drm_prime_gem_destroy(gem_obj, obj->sg_table); |
| 3539 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3540 | if (obj->phys_obj) |
| 3541 | i915_gem_detach_phys_object(dev, obj); |
| 3542 | |
| 3543 | obj->pin_count = 0; |
| 3544 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { |
| 3545 | bool was_interruptible; |
| 3546 | |
| 3547 | was_interruptible = dev_priv->mm.interruptible; |
| 3548 | dev_priv->mm.interruptible = false; |
| 3549 | |
| 3550 | WARN_ON(i915_gem_object_unbind(obj)); |
| 3551 | |
| 3552 | dev_priv->mm.interruptible = was_interruptible; |
| 3553 | } |
| 3554 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3555 | if (obj->base.map_list.map) |
Rob Clark | b464e9a | 2011-08-10 08:09:08 -0500 | [diff] [blame] | 3556 | drm_gem_free_mmap_offset(&obj->base); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3557 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3558 | drm_gem_object_release(&obj->base); |
| 3559 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3560 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3561 | kfree(obj->bit_17); |
| 3562 | kfree(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3563 | } |
| 3564 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 3565 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3566 | i915_gem_idle(struct drm_device *dev) |
| 3567 | { |
| 3568 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3569 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3570 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3571 | mutex_lock(&dev->struct_mutex); |
| 3572 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 3573 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3574 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3575 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3576 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3577 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3578 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3579 | if (ret) { |
| 3580 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3581 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3582 | } |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3583 | i915_gem_retire_requests(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3584 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3585 | /* Under UMS, be paranoid and evict. */ |
Chris Wilson | a39d7ef | 2012-04-24 18:22:52 +0100 | [diff] [blame] | 3586 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3587 | i915_gem_evict_everything(dev, false); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3588 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 3589 | i915_gem_reset_fences(dev); |
| 3590 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3591 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 3592 | * We need to replace this with a semaphore, or something. |
| 3593 | * And not confound mm.suspended! |
| 3594 | */ |
| 3595 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 3596 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3597 | |
| 3598 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3599 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3600 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3601 | mutex_unlock(&dev->struct_mutex); |
| 3602 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3603 | /* Cancel the retire work handler, which should be idle now. */ |
| 3604 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 3605 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3606 | return 0; |
| 3607 | } |
| 3608 | |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 3609 | void i915_gem_l3_remap(struct drm_device *dev) |
| 3610 | { |
| 3611 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3612 | u32 misccpctl; |
| 3613 | int i; |
| 3614 | |
| 3615 | if (!IS_IVYBRIDGE(dev)) |
| 3616 | return; |
| 3617 | |
| 3618 | if (!dev_priv->mm.l3_remap_info) |
| 3619 | return; |
| 3620 | |
| 3621 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 3622 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 3623 | POSTING_READ(GEN7_MISCCPCTL); |
| 3624 | |
| 3625 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
| 3626 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); |
| 3627 | if (remap && remap != dev_priv->mm.l3_remap_info[i/4]) |
| 3628 | DRM_DEBUG("0x%x was already programmed to %x\n", |
| 3629 | GEN7_L3LOG_BASE + i, remap); |
| 3630 | if (remap && !dev_priv->mm.l3_remap_info[i/4]) |
| 3631 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
| 3632 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]); |
| 3633 | } |
| 3634 | |
| 3635 | /* Make sure all the writes land before disabling dop clock gating */ |
| 3636 | POSTING_READ(GEN7_L3LOG_BASE); |
| 3637 | |
| 3638 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 3639 | } |
| 3640 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3641 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 3642 | { |
| 3643 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3644 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3645 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3646 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 3647 | return; |
| 3648 | |
| 3649 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 3650 | DISP_TILE_SURFACE_SWIZZLING); |
| 3651 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3652 | if (IS_GEN5(dev)) |
| 3653 | return; |
| 3654 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3655 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 3656 | if (IS_GEN6(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3657 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3658 | else |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3659 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3660 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3661 | |
| 3662 | void i915_gem_init_ppgtt(struct drm_device *dev) |
| 3663 | { |
| 3664 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3665 | uint32_t pd_offset; |
| 3666 | struct intel_ring_buffer *ring; |
Daniel Vetter | 55a254a | 2012-03-22 00:14:43 +0100 | [diff] [blame] | 3667 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 3668 | uint32_t __iomem *pd_addr; |
| 3669 | uint32_t pd_entry; |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3670 | int i; |
| 3671 | |
| 3672 | if (!dev_priv->mm.aliasing_ppgtt) |
| 3673 | return; |
| 3674 | |
Daniel Vetter | 55a254a | 2012-03-22 00:14:43 +0100 | [diff] [blame] | 3675 | |
| 3676 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); |
| 3677 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 3678 | dma_addr_t pt_addr; |
| 3679 | |
| 3680 | if (dev_priv->mm.gtt->needs_dmar) |
| 3681 | pt_addr = ppgtt->pt_dma_addr[i]; |
| 3682 | else |
| 3683 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); |
| 3684 | |
| 3685 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); |
| 3686 | pd_entry |= GEN6_PDE_VALID; |
| 3687 | |
| 3688 | writel(pd_entry, pd_addr + i); |
| 3689 | } |
| 3690 | readl(pd_addr); |
| 3691 | |
| 3692 | pd_offset = ppgtt->pd_offset; |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3693 | pd_offset /= 64; /* in cachelines, */ |
| 3694 | pd_offset <<= 16; |
| 3695 | |
| 3696 | if (INTEL_INFO(dev)->gen == 6) { |
Daniel Vetter | 48ecfa1 | 2012-04-11 20:42:40 +0200 | [diff] [blame] | 3697 | uint32_t ecochk, gab_ctl, ecobits; |
| 3698 | |
| 3699 | ecobits = I915_READ(GAC_ECO_BITS); |
| 3700 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); |
Daniel Vetter | be901a5 | 2012-04-11 20:42:39 +0200 | [diff] [blame] | 3701 | |
| 3702 | gab_ctl = I915_READ(GAB_CTL); |
| 3703 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); |
| 3704 | |
| 3705 | ecochk = I915_READ(GAM_ECOCHK); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3706 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
| 3707 | ECOCHK_PPGTT_CACHE64B); |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3708 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3709 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 3710 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); |
| 3711 | /* GFX_MODE is per-ring on gen7+ */ |
| 3712 | } |
| 3713 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3714 | for_each_ring(ring, dev_priv, i) { |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3715 | if (INTEL_INFO(dev)->gen >= 7) |
| 3716 | I915_WRITE(RING_MODE_GEN7(ring), |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3717 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3718 | |
| 3719 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 3720 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); |
| 3721 | } |
| 3722 | } |
| 3723 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 3724 | static bool |
| 3725 | intel_enable_blt(struct drm_device *dev) |
| 3726 | { |
| 3727 | if (!HAS_BLT(dev)) |
| 3728 | return false; |
| 3729 | |
| 3730 | /* The blitter was dysfunctional on early prototypes */ |
| 3731 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
| 3732 | DRM_INFO("BLT not supported on this pre-production hardware;" |
| 3733 | " graphics performance will be degraded.\n"); |
| 3734 | return false; |
| 3735 | } |
| 3736 | |
| 3737 | return true; |
| 3738 | } |
| 3739 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3740 | int |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3741 | i915_gem_init_hw(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3742 | { |
| 3743 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3744 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3745 | |
Daniel Vetter | 8ecd1a6 | 2012-06-07 15:56:03 +0200 | [diff] [blame] | 3746 | if (!intel_enable_gtt()) |
| 3747 | return -EIO; |
| 3748 | |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 3749 | i915_gem_l3_remap(dev); |
| 3750 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3751 | i915_gem_init_swizzling(dev); |
| 3752 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3753 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3754 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 3755 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3756 | |
| 3757 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3758 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3759 | if (ret) |
| 3760 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3761 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3762 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 3763 | if (intel_enable_blt(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3764 | ret = intel_init_blt_ring_buffer(dev); |
| 3765 | if (ret) |
| 3766 | goto cleanup_bsd_ring; |
| 3767 | } |
| 3768 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 3769 | dev_priv->next_seqno = 1; |
| 3770 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 3771 | /* |
| 3772 | * XXX: There was some w/a described somewhere suggesting loading |
| 3773 | * contexts before PPGTT. |
| 3774 | */ |
| 3775 | i915_gem_context_init(dev); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3776 | i915_gem_init_ppgtt(dev); |
| 3777 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3778 | return 0; |
| 3779 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3780 | cleanup_bsd_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3781 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3782 | cleanup_render_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3783 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3784 | return ret; |
| 3785 | } |
| 3786 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 3787 | static bool |
| 3788 | intel_enable_ppgtt(struct drm_device *dev) |
| 3789 | { |
| 3790 | if (i915_enable_ppgtt >= 0) |
| 3791 | return i915_enable_ppgtt; |
| 3792 | |
| 3793 | #ifdef CONFIG_INTEL_IOMMU |
| 3794 | /* Disable ppgtt on SNB if VT-d is on. */ |
| 3795 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
| 3796 | return false; |
| 3797 | #endif |
| 3798 | |
| 3799 | return true; |
| 3800 | } |
| 3801 | |
| 3802 | int i915_gem_init(struct drm_device *dev) |
| 3803 | { |
| 3804 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3805 | unsigned long gtt_size, mappable_size; |
| 3806 | int ret; |
| 3807 | |
| 3808 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; |
| 3809 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
| 3810 | |
| 3811 | mutex_lock(&dev->struct_mutex); |
| 3812 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { |
| 3813 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the |
| 3814 | * aperture accordingly when using aliasing ppgtt. */ |
| 3815 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; |
| 3816 | |
| 3817 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); |
| 3818 | |
| 3819 | ret = i915_gem_init_aliasing_ppgtt(dev); |
| 3820 | if (ret) { |
| 3821 | mutex_unlock(&dev->struct_mutex); |
| 3822 | return ret; |
| 3823 | } |
| 3824 | } else { |
| 3825 | /* Let GEM Manage all of the aperture. |
| 3826 | * |
| 3827 | * However, leave one page at the end still bound to the scratch |
| 3828 | * page. There are a number of places where the hardware |
| 3829 | * apparently prefetches past the end of the object, and we've |
| 3830 | * seen multiple hangs with the GPU head pointer stuck in a |
| 3831 | * batchbuffer bound at the last page of the aperture. One page |
| 3832 | * should be enough to keep any prefetching inside of the |
| 3833 | * aperture. |
| 3834 | */ |
| 3835 | i915_gem_init_global_gtt(dev, 0, mappable_size, |
| 3836 | gtt_size); |
| 3837 | } |
| 3838 | |
| 3839 | ret = i915_gem_init_hw(dev); |
| 3840 | mutex_unlock(&dev->struct_mutex); |
| 3841 | if (ret) { |
| 3842 | i915_gem_cleanup_aliasing_ppgtt(dev); |
| 3843 | return ret; |
| 3844 | } |
| 3845 | |
Daniel Vetter | 53ca26c | 2012-04-26 23:28:03 +0200 | [diff] [blame] | 3846 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
| 3847 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3848 | dev_priv->dri1.allow_batchbuffer = 1; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 3849 | return 0; |
| 3850 | } |
| 3851 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3852 | void |
| 3853 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 3854 | { |
| 3855 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3856 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3857 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3858 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3859 | for_each_ring(ring, dev_priv, i) |
| 3860 | intel_cleanup_ring_buffer(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3861 | } |
| 3862 | |
| 3863 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3864 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 3865 | struct drm_file *file_priv) |
| 3866 | { |
| 3867 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3868 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3869 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3870 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3871 | return 0; |
| 3872 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3873 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3874 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3875 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3876 | } |
| 3877 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3878 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3879 | dev_priv->mm.suspended = 0; |
| 3880 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3881 | ret = i915_gem_init_hw(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3882 | if (ret != 0) { |
| 3883 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3884 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3885 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3886 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3887 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3888 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 3889 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3890 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3891 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3892 | ret = drm_irq_install(dev); |
| 3893 | if (ret) |
| 3894 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3895 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3896 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3897 | |
| 3898 | cleanup_ringbuffer: |
| 3899 | mutex_lock(&dev->struct_mutex); |
| 3900 | i915_gem_cleanup_ringbuffer(dev); |
| 3901 | dev_priv->mm.suspended = 1; |
| 3902 | mutex_unlock(&dev->struct_mutex); |
| 3903 | |
| 3904 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3905 | } |
| 3906 | |
| 3907 | int |
| 3908 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 3909 | struct drm_file *file_priv) |
| 3910 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3911 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3912 | return 0; |
| 3913 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3914 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 3915 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3916 | } |
| 3917 | |
| 3918 | void |
| 3919 | i915_gem_lastclose(struct drm_device *dev) |
| 3920 | { |
| 3921 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3922 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 3923 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3924 | return; |
| 3925 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3926 | ret = i915_gem_idle(dev); |
| 3927 | if (ret) |
| 3928 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3929 | } |
| 3930 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 3931 | static void |
| 3932 | init_ring_lists(struct intel_ring_buffer *ring) |
| 3933 | { |
| 3934 | INIT_LIST_HEAD(&ring->active_list); |
| 3935 | INIT_LIST_HEAD(&ring->request_list); |
| 3936 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 3937 | } |
| 3938 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3939 | void |
| 3940 | i915_gem_load(struct drm_device *dev) |
| 3941 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3942 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3943 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3944 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3945 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3946 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 3947 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3948 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3949 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3950 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 3951 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 3952 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 3953 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3954 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 3955 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3956 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3957 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 3958 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 3959 | if (IS_GEN3(dev)) { |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 3960 | I915_WRITE(MI_ARB_STATE, |
| 3961 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 3962 | } |
| 3963 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 3964 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 3965 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3966 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 3967 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3968 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3969 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3970 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3971 | dev_priv->num_fence_regs = 16; |
| 3972 | else |
| 3973 | dev_priv->num_fence_regs = 8; |
| 3974 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3975 | /* Initialize fence registers to zero */ |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 3976 | i915_gem_reset_fences(dev); |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 3977 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3978 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3979 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3980 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3981 | dev_priv->mm.interruptible = true; |
| 3982 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3983 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 3984 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 3985 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3986 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3987 | |
| 3988 | /* |
| 3989 | * Create a physically contiguous memory object for this object |
| 3990 | * e.g. for cursor + overlay regs |
| 3991 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3992 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 3993 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3994 | { |
| 3995 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3996 | struct drm_i915_gem_phys_object *phys_obj; |
| 3997 | int ret; |
| 3998 | |
| 3999 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4000 | return 0; |
| 4001 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4002 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4003 | if (!phys_obj) |
| 4004 | return -ENOMEM; |
| 4005 | |
| 4006 | phys_obj->id = id; |
| 4007 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4008 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4009 | if (!phys_obj->handle) { |
| 4010 | ret = -ENOMEM; |
| 4011 | goto kfree_obj; |
| 4012 | } |
| 4013 | #ifdef CONFIG_X86 |
| 4014 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4015 | #endif |
| 4016 | |
| 4017 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4018 | |
| 4019 | return 0; |
| 4020 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4021 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4022 | return ret; |
| 4023 | } |
| 4024 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4025 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4026 | { |
| 4027 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4028 | struct drm_i915_gem_phys_object *phys_obj; |
| 4029 | |
| 4030 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4031 | return; |
| 4032 | |
| 4033 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4034 | if (phys_obj->cur_obj) { |
| 4035 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4036 | } |
| 4037 | |
| 4038 | #ifdef CONFIG_X86 |
| 4039 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4040 | #endif |
| 4041 | drm_pci_free(dev, phys_obj->handle); |
| 4042 | kfree(phys_obj); |
| 4043 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4044 | } |
| 4045 | |
| 4046 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4047 | { |
| 4048 | int i; |
| 4049 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4050 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4051 | i915_gem_free_phys_object(dev, i); |
| 4052 | } |
| 4053 | |
| 4054 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4055 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4056 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4057 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4058 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4059 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4060 | int page_count; |
| 4061 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4062 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4063 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4064 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4065 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4066 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4067 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4068 | struct page *page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4069 | if (!IS_ERR(page)) { |
| 4070 | char *dst = kmap_atomic(page); |
| 4071 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 4072 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4073 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4074 | drm_clflush_pages(&page, 1); |
| 4075 | |
| 4076 | set_page_dirty(page); |
| 4077 | mark_page_accessed(page); |
| 4078 | page_cache_release(page); |
| 4079 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4080 | } |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 4081 | intel_gtt_chipset_flush(); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4082 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4083 | obj->phys_obj->cur_obj = NULL; |
| 4084 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4085 | } |
| 4086 | |
| 4087 | int |
| 4088 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4089 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4090 | int id, |
| 4091 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4092 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4093 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4094 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4095 | int ret = 0; |
| 4096 | int page_count; |
| 4097 | int i; |
| 4098 | |
| 4099 | if (id > I915_MAX_PHYS_OBJECT) |
| 4100 | return -EINVAL; |
| 4101 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4102 | if (obj->phys_obj) { |
| 4103 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4104 | return 0; |
| 4105 | i915_gem_detach_phys_object(dev, obj); |
| 4106 | } |
| 4107 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4108 | /* create a new object */ |
| 4109 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4110 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4111 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4112 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4113 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 4114 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4115 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4116 | } |
| 4117 | } |
| 4118 | |
| 4119 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4120 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4121 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4122 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4123 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4124 | |
| 4125 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4126 | struct page *page; |
| 4127 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4128 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4129 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4130 | if (IS_ERR(page)) |
| 4131 | return PTR_ERR(page); |
| 4132 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 4133 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4134 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4135 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4136 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4137 | |
| 4138 | mark_page_accessed(page); |
| 4139 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4140 | } |
| 4141 | |
| 4142 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4143 | } |
| 4144 | |
| 4145 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4146 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 4147 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4148 | struct drm_i915_gem_pwrite *args, |
| 4149 | struct drm_file *file_priv) |
| 4150 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4151 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 4152 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4153 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 4154 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 4155 | unsigned long unwritten; |
| 4156 | |
| 4157 | /* The physical object once assigned is fixed for the lifetime |
| 4158 | * of the obj, so we can safely drop the lock and continue |
| 4159 | * to access vaddr. |
| 4160 | */ |
| 4161 | mutex_unlock(&dev->struct_mutex); |
| 4162 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 4163 | mutex_lock(&dev->struct_mutex); |
| 4164 | if (unwritten) |
| 4165 | return -EFAULT; |
| 4166 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4167 | |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 4168 | intel_gtt_chipset_flush(); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4169 | return 0; |
| 4170 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4171 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4172 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4173 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4174 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4175 | |
| 4176 | /* Clean up our request list when the client is going away, so that |
| 4177 | * later retire_requests won't dereference our soon-to-be-gone |
| 4178 | * file_priv. |
| 4179 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4180 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4181 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4182 | struct drm_i915_gem_request *request; |
| 4183 | |
| 4184 | request = list_first_entry(&file_priv->mm.request_list, |
| 4185 | struct drm_i915_gem_request, |
| 4186 | client_list); |
| 4187 | list_del(&request->client_list); |
| 4188 | request->file_priv = NULL; |
| 4189 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4190 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4191 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4192 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4193 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4194 | i915_gpu_is_active(struct drm_device *dev) |
| 4195 | { |
| 4196 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4197 | int lists_empty; |
| 4198 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4199 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4200 | list_empty(&dev_priv->mm.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4201 | |
| 4202 | return !lists_empty; |
| 4203 | } |
| 4204 | |
| 4205 | static int |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4206 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4207 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4208 | struct drm_i915_private *dev_priv = |
| 4209 | container_of(shrinker, |
| 4210 | struct drm_i915_private, |
| 4211 | mm.inactive_shrinker); |
| 4212 | struct drm_device *dev = dev_priv->dev; |
| 4213 | struct drm_i915_gem_object *obj, *next; |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4214 | int nr_to_scan = sc->nr_to_scan; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4215 | int cnt; |
| 4216 | |
| 4217 | if (!mutex_trylock(&dev->struct_mutex)) |
Chris Wilson | bbe2e11 | 2010-10-28 22:35:07 +0100 | [diff] [blame] | 4218 | return 0; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4219 | |
| 4220 | /* "fast-path" to count number of available objects */ |
| 4221 | if (nr_to_scan == 0) { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4222 | cnt = 0; |
| 4223 | list_for_each_entry(obj, |
| 4224 | &dev_priv->mm.inactive_list, |
| 4225 | mm_list) |
| 4226 | cnt++; |
| 4227 | mutex_unlock(&dev->struct_mutex); |
| 4228 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4229 | } |
| 4230 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4231 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4232 | /* first scan for clean buffers */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4233 | i915_gem_retire_requests(dev); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4234 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4235 | list_for_each_entry_safe(obj, next, |
| 4236 | &dev_priv->mm.inactive_list, |
| 4237 | mm_list) { |
| 4238 | if (i915_gem_object_is_purgeable(obj)) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4239 | if (i915_gem_object_unbind(obj) == 0 && |
| 4240 | --nr_to_scan == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4241 | break; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4242 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4243 | } |
| 4244 | |
| 4245 | /* second pass, evict/count anything still on the inactive list */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4246 | cnt = 0; |
| 4247 | list_for_each_entry_safe(obj, next, |
| 4248 | &dev_priv->mm.inactive_list, |
| 4249 | mm_list) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4250 | if (nr_to_scan && |
| 4251 | i915_gem_object_unbind(obj) == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4252 | nr_to_scan--; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4253 | else |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4254 | cnt++; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4255 | } |
| 4256 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4257 | if (nr_to_scan && i915_gpu_is_active(dev)) { |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4258 | /* |
| 4259 | * We are desperate for pages, so as a last resort, wait |
| 4260 | * for the GPU to finish and discard whatever we can. |
| 4261 | * This has a dramatic impact to reduce the number of |
| 4262 | * OOM-killer events whilst running the GPU aggressively. |
| 4263 | */ |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4264 | if (i915_gpu_idle(dev) == 0) |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4265 | goto rescan; |
| 4266 | } |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4267 | mutex_unlock(&dev->struct_mutex); |
| 4268 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4269 | } |