blob: 71866646ffefceec7c60f4927dade78fdde6854a [file] [log] [blame]
Thomas Petazzoni19a340b2016-06-16 14:28:34 +02001/*
2 * Copyright (C) 2015-2016 Marvell International Ltd.
3
4 * This program is free software: you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation, either version 2 of the
7 * License, or any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/dma-mapping.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/msi.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/platform_device.h>
24#include <linux/spinlock.h>
25
26#include "dmaengine.h"
27
28/* DMA Engine Registers */
29#define MV_XOR_V2_DMA_DESQ_BALR_OFF 0x000
30#define MV_XOR_V2_DMA_DESQ_BAHR_OFF 0x004
31#define MV_XOR_V2_DMA_DESQ_SIZE_OFF 0x008
32#define MV_XOR_V2_DMA_DESQ_DONE_OFF 0x00C
33#define MV_XOR_V2_DMA_DESQ_DONE_PENDING_MASK 0x7FFF
34#define MV_XOR_V2_DMA_DESQ_DONE_PENDING_SHIFT 0
35#define MV_XOR_V2_DMA_DESQ_DONE_READ_PTR_MASK 0x1FFF
36#define MV_XOR_V2_DMA_DESQ_DONE_READ_PTR_SHIFT 16
37#define MV_XOR_V2_DMA_DESQ_ARATTR_OFF 0x010
38#define MV_XOR_V2_DMA_DESQ_ATTR_CACHE_MASK 0x3F3F
39#define MV_XOR_V2_DMA_DESQ_ATTR_OUTER_SHAREABLE 0x202
40#define MV_XOR_V2_DMA_DESQ_ATTR_CACHEABLE 0x3C3C
41#define MV_XOR_V2_DMA_IMSG_CDAT_OFF 0x014
42#define MV_XOR_V2_DMA_IMSG_THRD_OFF 0x018
43#define MV_XOR_V2_DMA_IMSG_THRD_MASK 0x7FFF
44#define MV_XOR_V2_DMA_IMSG_THRD_SHIFT 0x0
45#define MV_XOR_V2_DMA_DESQ_AWATTR_OFF 0x01C
46 /* Same flags as MV_XOR_V2_DMA_DESQ_ARATTR_OFF */
47#define MV_XOR_V2_DMA_DESQ_ALLOC_OFF 0x04C
48#define MV_XOR_V2_DMA_DESQ_ALLOC_WRPTR_MASK 0xFFFF
49#define MV_XOR_V2_DMA_DESQ_ALLOC_WRPTR_SHIFT 16
50#define MV_XOR_V2_DMA_IMSG_BALR_OFF 0x050
51#define MV_XOR_V2_DMA_IMSG_BAHR_OFF 0x054
52#define MV_XOR_V2_DMA_DESQ_CTRL_OFF 0x100
53#define MV_XOR_V2_DMA_DESQ_CTRL_32B 1
54#define MV_XOR_V2_DMA_DESQ_CTRL_128B 7
55#define MV_XOR_V2_DMA_DESQ_STOP_OFF 0x800
56#define MV_XOR_V2_DMA_DESQ_DEALLOC_OFF 0x804
57#define MV_XOR_V2_DMA_DESQ_ADD_OFF 0x808
58
59/* XOR Global registers */
60#define MV_XOR_V2_GLOB_BW_CTRL 0x4
61#define MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_RD_SHIFT 0
62#define MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_RD_VAL 64
63#define MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_WR_SHIFT 8
64#define MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_WR_VAL 8
65#define MV_XOR_V2_GLOB_BW_CTRL_RD_BURST_LEN_SHIFT 12
66#define MV_XOR_V2_GLOB_BW_CTRL_RD_BURST_LEN_VAL 4
67#define MV_XOR_V2_GLOB_BW_CTRL_WR_BURST_LEN_SHIFT 16
68#define MV_XOR_V2_GLOB_BW_CTRL_WR_BURST_LEN_VAL 4
69#define MV_XOR_V2_GLOB_PAUSE 0x014
70#define MV_XOR_V2_GLOB_PAUSE_AXI_TIME_DIS_VAL 0x8
71#define MV_XOR_V2_GLOB_SYS_INT_CAUSE 0x200
72#define MV_XOR_V2_GLOB_SYS_INT_MASK 0x204
73#define MV_XOR_V2_GLOB_MEM_INT_CAUSE 0x220
74#define MV_XOR_V2_GLOB_MEM_INT_MASK 0x224
75
76#define MV_XOR_V2_MIN_DESC_SIZE 32
77#define MV_XOR_V2_EXT_DESC_SIZE 128
78
79#define MV_XOR_V2_DESC_RESERVED_SIZE 12
80#define MV_XOR_V2_DESC_BUFF_D_ADDR_SIZE 12
81
82#define MV_XOR_V2_CMD_LINE_NUM_MAX_D_BUF 8
83
84/*
85 * Descriptors queue size. With 32 bytes descriptors, up to 2^14
86 * descriptors are allowed, with 128 bytes descriptors, up to 2^12
87 * descriptors are allowed. This driver uses 128 bytes descriptors,
88 * but experimentation has shown that a set of 1024 descriptors is
89 * sufficient to reach a good level of performance.
90 */
91#define MV_XOR_V2_DESC_NUM 1024
92
93/**
94 * struct mv_xor_v2_descriptor - DMA HW descriptor
95 * @desc_id: used by S/W and is not affected by H/W.
96 * @flags: error and status flags
97 * @crc32_result: CRC32 calculation result
98 * @desc_ctrl: operation mode and control flags
99 * @buff_size: amount of bytes to be processed
100 * @fill_pattern_src_addr: Fill-Pattern or Source-Address and
101 * AW-Attributes
102 * @data_buff_addr: Source (and might be RAID6 destination)
103 * addresses of data buffers in RAID5 and RAID6
104 * @reserved: reserved
105 */
106struct mv_xor_v2_descriptor {
107 u16 desc_id;
108 u16 flags;
109 u32 crc32_result;
110 u32 desc_ctrl;
111
112 /* Definitions for desc_ctrl */
113#define DESC_NUM_ACTIVE_D_BUF_SHIFT 22
114#define DESC_OP_MODE_SHIFT 28
115#define DESC_OP_MODE_NOP 0 /* Idle operation */
116#define DESC_OP_MODE_MEMCPY 1 /* Pure-DMA operation */
117#define DESC_OP_MODE_MEMSET 2 /* Mem-Fill operation */
118#define DESC_OP_MODE_MEMINIT 3 /* Mem-Init operation */
119#define DESC_OP_MODE_MEM_COMPARE 4 /* Mem-Compare operation */
120#define DESC_OP_MODE_CRC32 5 /* CRC32 calculation */
121#define DESC_OP_MODE_XOR 6 /* RAID5 (XOR) operation */
122#define DESC_OP_MODE_RAID6 7 /* RAID6 P&Q-generation */
123#define DESC_OP_MODE_RAID6_REC 8 /* RAID6 Recovery */
124#define DESC_Q_BUFFER_ENABLE BIT(16)
125#define DESC_P_BUFFER_ENABLE BIT(17)
126#define DESC_IOD BIT(27)
127
128 u32 buff_size;
129 u32 fill_pattern_src_addr[4];
130 u32 data_buff_addr[MV_XOR_V2_DESC_BUFF_D_ADDR_SIZE];
131 u32 reserved[MV_XOR_V2_DESC_RESERVED_SIZE];
132};
133
134/**
135 * struct mv_xor_v2_device - implements a xor device
136 * @lock: lock for the engine
137 * @dma_base: memory mapped DMA register base
138 * @glob_base: memory mapped global register base
139 * @irq_tasklet:
140 * @free_sw_desc: linked list of free SW descriptors
141 * @dmadev: dma device
142 * @dmachan: dma channel
143 * @hw_desq: HW descriptors queue
144 * @hw_desq_virt: virtual address of DESCQ
145 * @sw_desq: SW descriptors queue
146 * @desc_size: HW descriptor size
147 * @npendings: number of pending descriptors (for which tx_submit has
148 * been called, but not yet issue_pending)
149 */
150struct mv_xor_v2_device {
151 spinlock_t lock;
152 void __iomem *dma_base;
153 void __iomem *glob_base;
154 struct clk *clk;
Gregory CLEMENT3bdcced2018-03-07 16:40:10 +0100155 struct clk *reg_clk;
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200156 struct tasklet_struct irq_tasklet;
157 struct list_head free_sw_desc;
158 struct dma_device dmadev;
159 struct dma_chan dmachan;
160 dma_addr_t hw_desq;
161 struct mv_xor_v2_descriptor *hw_desq_virt;
162 struct mv_xor_v2_sw_desc *sw_desq;
163 int desc_size;
164 unsigned int npendings;
Thomas Petazzonib2c8bb02017-05-05 11:57:48 +0200165 unsigned int hw_queue_idx;
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200166};
167
168/**
169 * struct mv_xor_v2_sw_desc - implements a xor SW descriptor
170 * @idx: descriptor index
171 * @async_tx: support for the async_tx api
172 * @hw_desc: assosiated HW descriptor
173 * @free_list: node of the free SW descriprots list
174*/
175struct mv_xor_v2_sw_desc {
176 int idx;
177 struct dma_async_tx_descriptor async_tx;
178 struct mv_xor_v2_descriptor hw_desc;
179 struct list_head free_list;
180};
181
182/*
183 * Fill the data buffers to a HW descriptor
184 */
185static void mv_xor_v2_set_data_buffers(struct mv_xor_v2_device *xor_dev,
186 struct mv_xor_v2_descriptor *desc,
187 dma_addr_t src, int index)
188{
189 int arr_index = ((index >> 1) * 3);
190
191 /*
192 * Fill the buffer's addresses to the descriptor.
193 *
194 * The format of the buffers address for 2 sequential buffers
195 * X and X + 1:
196 *
197 * First word: Buffer-DX-Address-Low[31:0]
198 * Second word: Buffer-DX+1-Address-Low[31:0]
199 * Third word: DX+1-Buffer-Address-High[47:32] [31:16]
200 * DX-Buffer-Address-High[47:32] [15:0]
201 */
202 if ((index & 0x1) == 0) {
203 desc->data_buff_addr[arr_index] = lower_32_bits(src);
204
205 desc->data_buff_addr[arr_index + 2] &= ~0xFFFF;
206 desc->data_buff_addr[arr_index + 2] |=
207 upper_32_bits(src) & 0xFFFF;
208 } else {
209 desc->data_buff_addr[arr_index + 1] =
210 lower_32_bits(src);
211
212 desc->data_buff_addr[arr_index + 2] &= ~0xFFFF0000;
213 desc->data_buff_addr[arr_index + 2] |=
214 (upper_32_bits(src) & 0xFFFF) << 16;
215 }
216}
217
218/*
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200219 * notify the engine of new descriptors, and update the available index.
220 */
221static void mv_xor_v2_add_desc_to_desq(struct mv_xor_v2_device *xor_dev,
222 int num_of_desc)
223{
224 /* write the number of new descriptors in the DESQ. */
225 writel(num_of_desc, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ADD_OFF);
226}
227
228/*
229 * free HW descriptors
230 */
231static void mv_xor_v2_free_desc_from_desq(struct mv_xor_v2_device *xor_dev,
232 int num_of_desc)
233{
234 /* write the number of new descriptors in the DESQ. */
235 writel(num_of_desc, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DEALLOC_OFF);
236}
237
238/*
239 * Set descriptor size
240 * Return the HW descriptor size in bytes
241 */
242static int mv_xor_v2_set_desc_size(struct mv_xor_v2_device *xor_dev)
243{
244 writel(MV_XOR_V2_DMA_DESQ_CTRL_128B,
245 xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_CTRL_OFF);
246
247 return MV_XOR_V2_EXT_DESC_SIZE;
248}
249
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200250static irqreturn_t mv_xor_v2_interrupt_handler(int irq, void *data)
251{
252 struct mv_xor_v2_device *xor_dev = data;
253 unsigned int ndescs;
254 u32 reg;
255
256 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DONE_OFF);
257
258 ndescs = ((reg >> MV_XOR_V2_DMA_DESQ_DONE_PENDING_SHIFT) &
259 MV_XOR_V2_DMA_DESQ_DONE_PENDING_MASK);
260
261 /* No descriptors to process */
262 if (!ndescs)
263 return IRQ_NONE;
264
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200265 /* schedule a tasklet to handle descriptors callbacks */
266 tasklet_schedule(&xor_dev->irq_tasklet);
267
268 return IRQ_HANDLED;
269}
270
271/*
272 * submit a descriptor to the DMA engine
273 */
274static dma_cookie_t
275mv_xor_v2_tx_submit(struct dma_async_tx_descriptor *tx)
276{
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200277 void *dest_hw_desc;
278 dma_cookie_t cookie;
279 struct mv_xor_v2_sw_desc *sw_desc =
280 container_of(tx, struct mv_xor_v2_sw_desc, async_tx);
281 struct mv_xor_v2_device *xor_dev =
282 container_of(tx->chan, struct mv_xor_v2_device, dmachan);
283
284 dev_dbg(xor_dev->dmadev.dev,
285 "%s sw_desc %p: async_tx %p\n",
286 __func__, sw_desc, &sw_desc->async_tx);
287
288 /* assign coookie */
289 spin_lock_bh(&xor_dev->lock);
290 cookie = dma_cookie_assign(tx);
291
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200292 /* copy the HW descriptor from the SW descriptor to the DESQ */
Thomas Petazzonib2c8bb02017-05-05 11:57:48 +0200293 dest_hw_desc = xor_dev->hw_desq_virt + xor_dev->hw_queue_idx;
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200294
295 memcpy(dest_hw_desc, &sw_desc->hw_desc, xor_dev->desc_size);
296
297 xor_dev->npendings++;
Thomas Petazzonib2c8bb02017-05-05 11:57:48 +0200298 xor_dev->hw_queue_idx++;
299 if (xor_dev->hw_queue_idx >= MV_XOR_V2_DESC_NUM)
300 xor_dev->hw_queue_idx = 0;
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200301
302 spin_unlock_bh(&xor_dev->lock);
303
304 return cookie;
305}
306
307/*
308 * Prepare a SW descriptor
309 */
310static struct mv_xor_v2_sw_desc *
311mv_xor_v2_prep_sw_desc(struct mv_xor_v2_device *xor_dev)
312{
313 struct mv_xor_v2_sw_desc *sw_desc;
Thomas Petazzonie2a092e2017-05-05 11:57:46 +0200314 bool found = false;
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200315
316 /* Lock the channel */
317 spin_lock_bh(&xor_dev->lock);
318
319 if (list_empty(&xor_dev->free_sw_desc)) {
320 spin_unlock_bh(&xor_dev->lock);
321 /* schedule tasklet to free some descriptors */
322 tasklet_schedule(&xor_dev->irq_tasklet);
323 return NULL;
324 }
325
Thomas Petazzonie2a092e2017-05-05 11:57:46 +0200326 list_for_each_entry(sw_desc, &xor_dev->free_sw_desc, free_list) {
327 if (async_tx_test_ack(&sw_desc->async_tx)) {
328 found = true;
329 break;
330 }
331 }
332
333 if (!found) {
334 spin_unlock_bh(&xor_dev->lock);
335 return NULL;
336 }
337
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200338 list_del(&sw_desc->free_list);
339
340 /* Release the channel */
341 spin_unlock_bh(&xor_dev->lock);
342
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200343 return sw_desc;
344}
345
346/*
347 * Prepare a HW descriptor for a memcpy operation
348 */
349static struct dma_async_tx_descriptor *
350mv_xor_v2_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest,
351 dma_addr_t src, size_t len, unsigned long flags)
352{
353 struct mv_xor_v2_sw_desc *sw_desc;
354 struct mv_xor_v2_descriptor *hw_descriptor;
355 struct mv_xor_v2_device *xor_dev;
356
357 xor_dev = container_of(chan, struct mv_xor_v2_device, dmachan);
358
359 dev_dbg(xor_dev->dmadev.dev,
360 "%s len: %zu src %pad dest %pad flags: %ld\n",
361 __func__, len, &src, &dest, flags);
362
363 sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);
Thomas Petazzonif08c84d2017-05-05 11:57:44 +0200364 if (!sw_desc)
365 return NULL;
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200366
367 sw_desc->async_tx.flags = flags;
368
369 /* set the HW descriptor */
370 hw_descriptor = &sw_desc->hw_desc;
371
372 /* save the SW descriptor ID to restore when operation is done */
373 hw_descriptor->desc_id = sw_desc->idx;
374
375 /* Set the MEMCPY control word */
376 hw_descriptor->desc_ctrl =
377 DESC_OP_MODE_MEMCPY << DESC_OP_MODE_SHIFT;
378
379 if (flags & DMA_PREP_INTERRUPT)
380 hw_descriptor->desc_ctrl |= DESC_IOD;
381
382 /* Set source address */
383 hw_descriptor->fill_pattern_src_addr[0] = lower_32_bits(src);
384 hw_descriptor->fill_pattern_src_addr[1] =
385 upper_32_bits(src) & 0xFFFF;
386
387 /* Set Destination address */
388 hw_descriptor->fill_pattern_src_addr[2] = lower_32_bits(dest);
389 hw_descriptor->fill_pattern_src_addr[3] =
390 upper_32_bits(dest) & 0xFFFF;
391
392 /* Set buffers size */
393 hw_descriptor->buff_size = len;
394
395 /* return the async tx descriptor */
396 return &sw_desc->async_tx;
397}
398
399/*
400 * Prepare a HW descriptor for a XOR operation
401 */
402static struct dma_async_tx_descriptor *
403mv_xor_v2_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
404 unsigned int src_cnt, size_t len, unsigned long flags)
405{
406 struct mv_xor_v2_sw_desc *sw_desc;
407 struct mv_xor_v2_descriptor *hw_descriptor;
408 struct mv_xor_v2_device *xor_dev =
409 container_of(chan, struct mv_xor_v2_device, dmachan);
410 int i;
411
412 if (src_cnt > MV_XOR_V2_CMD_LINE_NUM_MAX_D_BUF || src_cnt < 1)
413 return NULL;
414
415 dev_dbg(xor_dev->dmadev.dev,
416 "%s src_cnt: %d len: %zu dest %pad flags: %ld\n",
417 __func__, src_cnt, len, &dest, flags);
418
419 sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);
Thomas Petazzonif08c84d2017-05-05 11:57:44 +0200420 if (!sw_desc)
421 return NULL;
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200422
423 sw_desc->async_tx.flags = flags;
424
425 /* set the HW descriptor */
426 hw_descriptor = &sw_desc->hw_desc;
427
428 /* save the SW descriptor ID to restore when operation is done */
429 hw_descriptor->desc_id = sw_desc->idx;
430
431 /* Set the XOR control word */
432 hw_descriptor->desc_ctrl =
433 DESC_OP_MODE_XOR << DESC_OP_MODE_SHIFT;
434 hw_descriptor->desc_ctrl |= DESC_P_BUFFER_ENABLE;
435
436 if (flags & DMA_PREP_INTERRUPT)
437 hw_descriptor->desc_ctrl |= DESC_IOD;
438
439 /* Set the data buffers */
440 for (i = 0; i < src_cnt; i++)
441 mv_xor_v2_set_data_buffers(xor_dev, hw_descriptor, src[i], i);
442
443 hw_descriptor->desc_ctrl |=
444 src_cnt << DESC_NUM_ACTIVE_D_BUF_SHIFT;
445
446 /* Set Destination address */
447 hw_descriptor->fill_pattern_src_addr[2] = lower_32_bits(dest);
448 hw_descriptor->fill_pattern_src_addr[3] =
449 upper_32_bits(dest) & 0xFFFF;
450
451 /* Set buffers size */
452 hw_descriptor->buff_size = len;
453
454 /* return the async tx descriptor */
455 return &sw_desc->async_tx;
456}
457
458/*
459 * Prepare a HW descriptor for interrupt operation.
460 */
461static struct dma_async_tx_descriptor *
462mv_xor_v2_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
463{
464 struct mv_xor_v2_sw_desc *sw_desc;
465 struct mv_xor_v2_descriptor *hw_descriptor;
466 struct mv_xor_v2_device *xor_dev =
467 container_of(chan, struct mv_xor_v2_device, dmachan);
468
469 sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);
Thomas Petazzonif08c84d2017-05-05 11:57:44 +0200470 if (!sw_desc)
471 return NULL;
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200472
473 /* set the HW descriptor */
474 hw_descriptor = &sw_desc->hw_desc;
475
476 /* save the SW descriptor ID to restore when operation is done */
477 hw_descriptor->desc_id = sw_desc->idx;
478
479 /* Set the INTERRUPT control word */
480 hw_descriptor->desc_ctrl =
481 DESC_OP_MODE_NOP << DESC_OP_MODE_SHIFT;
482 hw_descriptor->desc_ctrl |= DESC_IOD;
483
484 /* return the async tx descriptor */
485 return &sw_desc->async_tx;
486}
487
488/*
489 * push pending transactions to hardware
490 */
491static void mv_xor_v2_issue_pending(struct dma_chan *chan)
492{
493 struct mv_xor_v2_device *xor_dev =
494 container_of(chan, struct mv_xor_v2_device, dmachan);
495
496 spin_lock_bh(&xor_dev->lock);
497
498 /*
499 * update the engine with the number of descriptors to
500 * process
501 */
502 mv_xor_v2_add_desc_to_desq(xor_dev, xor_dev->npendings);
503 xor_dev->npendings = 0;
504
505 /* Activate the channel */
506 writel(0, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF);
507
508 spin_unlock_bh(&xor_dev->lock);
509}
510
511static inline
512int mv_xor_v2_get_pending_params(struct mv_xor_v2_device *xor_dev,
513 int *pending_ptr)
514{
515 u32 reg;
516
517 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DONE_OFF);
518
519 /* get the next pending descriptor index */
520 *pending_ptr = ((reg >> MV_XOR_V2_DMA_DESQ_DONE_READ_PTR_SHIFT) &
521 MV_XOR_V2_DMA_DESQ_DONE_READ_PTR_MASK);
522
523 /* get the number of descriptors pending handle */
524 return ((reg >> MV_XOR_V2_DMA_DESQ_DONE_PENDING_SHIFT) &
525 MV_XOR_V2_DMA_DESQ_DONE_PENDING_MASK);
526}
527
528/*
529 * handle the descriptors after HW process
530 */
531static void mv_xor_v2_tasklet(unsigned long data)
532{
533 struct mv_xor_v2_device *xor_dev = (struct mv_xor_v2_device *) data;
534 int pending_ptr, num_of_pending, i;
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200535 struct mv_xor_v2_sw_desc *next_pending_sw_desc = NULL;
536
537 dev_dbg(xor_dev->dmadev.dev, "%s %d\n", __func__, __LINE__);
538
539 /* get the pending descriptors parameters */
540 num_of_pending = mv_xor_v2_get_pending_params(xor_dev, &pending_ptr);
541
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200542 /* loop over free descriptors */
543 for (i = 0; i < num_of_pending; i++) {
Thomas Petazzoni67b16842017-05-05 11:57:45 +0200544 struct mv_xor_v2_descriptor *next_pending_hw_desc =
545 xor_dev->hw_desq_virt + pending_ptr;
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200546
547 /* get the SW descriptor related to the HW descriptor */
548 next_pending_sw_desc =
549 &xor_dev->sw_desq[next_pending_hw_desc->desc_id];
550
551 /* call the callback */
552 if (next_pending_sw_desc->async_tx.cookie > 0) {
553 /*
554 * update the channel's completed cookie - no
555 * lock is required the IMSG threshold provide
556 * the locking
557 */
558 dma_cookie_complete(&next_pending_sw_desc->async_tx);
559
560 if (next_pending_sw_desc->async_tx.callback)
561 next_pending_sw_desc->async_tx.callback(
562 next_pending_sw_desc->async_tx.callback_param);
563
564 dma_descriptor_unmap(&next_pending_sw_desc->async_tx);
565 }
566
567 dma_run_dependencies(&next_pending_sw_desc->async_tx);
568
569 /* Lock the channel */
570 spin_lock_bh(&xor_dev->lock);
571
572 /* add the SW descriptor to the free descriptors list */
573 list_add(&next_pending_sw_desc->free_list,
574 &xor_dev->free_sw_desc);
575
576 /* Release the channel */
577 spin_unlock_bh(&xor_dev->lock);
578
579 /* increment the next descriptor */
580 pending_ptr++;
Thomas Petazzoni67b16842017-05-05 11:57:45 +0200581 if (pending_ptr >= MV_XOR_V2_DESC_NUM)
582 pending_ptr = 0;
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200583 }
584
585 if (num_of_pending != 0) {
586 /* free the descriptores */
587 mv_xor_v2_free_desc_from_desq(xor_dev, num_of_pending);
588 }
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200589}
590
591/*
592 * Set DMA Interrupt-message (IMSG) parameters
593 */
594static void mv_xor_v2_set_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
595{
596 struct mv_xor_v2_device *xor_dev = dev_get_drvdata(desc->dev);
597
598 writel(msg->address_lo,
599 xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_BALR_OFF);
600 writel(msg->address_hi & 0xFFFF,
601 xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_BAHR_OFF);
602 writel(msg->data,
603 xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_CDAT_OFF);
604}
605
606static int mv_xor_v2_descq_init(struct mv_xor_v2_device *xor_dev)
607{
608 u32 reg;
609
610 /* write the DESQ size to the DMA engine */
611 writel(MV_XOR_V2_DESC_NUM,
612 xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_SIZE_OFF);
613
614 /* write the DESQ address to the DMA enngine*/
615 writel(xor_dev->hw_desq & 0xFFFFFFFF,
616 xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_BALR_OFF);
617 writel((xor_dev->hw_desq & 0xFFFF00000000) >> 32,
618 xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_BAHR_OFF);
619
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200620 /*
621 * This is a temporary solution, until we activate the
622 * SMMU. Set the attributes for reading & writing data buffers
623 * & descriptors to:
624 *
625 * - OuterShareable - Snoops will be performed on CPU caches
626 * - Enable cacheable - Bufferable, Modifiable, Other Allocate
627 * and Allocate
628 */
629 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ARATTR_OFF);
630 reg &= ~MV_XOR_V2_DMA_DESQ_ATTR_CACHE_MASK;
631 reg |= MV_XOR_V2_DMA_DESQ_ATTR_OUTER_SHAREABLE |
632 MV_XOR_V2_DMA_DESQ_ATTR_CACHEABLE;
633 writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ARATTR_OFF);
634
635 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_AWATTR_OFF);
636 reg &= ~MV_XOR_V2_DMA_DESQ_ATTR_CACHE_MASK;
637 reg |= MV_XOR_V2_DMA_DESQ_ATTR_OUTER_SHAREABLE |
638 MV_XOR_V2_DMA_DESQ_ATTR_CACHEABLE;
639 writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_AWATTR_OFF);
640
641 /* BW CTRL - set values to optimize the XOR performance:
642 *
643 * - Set WrBurstLen & RdBurstLen - the unit will issue
644 * maximum of 256B write/read transactions.
645 * - Limit the number of outstanding write & read data
646 * (OBB/IBB) requests to the maximal value.
647 */
648 reg = ((MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_RD_VAL <<
649 MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_RD_SHIFT) |
650 (MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_WR_VAL <<
651 MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_WR_SHIFT) |
652 (MV_XOR_V2_GLOB_BW_CTRL_RD_BURST_LEN_VAL <<
653 MV_XOR_V2_GLOB_BW_CTRL_RD_BURST_LEN_SHIFT) |
654 (MV_XOR_V2_GLOB_BW_CTRL_WR_BURST_LEN_VAL <<
655 MV_XOR_V2_GLOB_BW_CTRL_WR_BURST_LEN_SHIFT));
656 writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_BW_CTRL);
657
658 /* Disable the AXI timer feature */
659 reg = readl(xor_dev->glob_base + MV_XOR_V2_GLOB_PAUSE);
660 reg |= MV_XOR_V2_GLOB_PAUSE_AXI_TIME_DIS_VAL;
661 writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_PAUSE);
662
Hanna Hawa0d091852017-05-05 11:57:47 +0200663 /* enable the DMA engine */
664 writel(0, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF);
665
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200666 return 0;
667}
668
669static int mv_xor_v2_probe(struct platform_device *pdev)
670{
671 struct mv_xor_v2_device *xor_dev;
672 struct resource *res;
673 int i, ret = 0;
674 struct dma_device *dma_dev;
675 struct mv_xor_v2_sw_desc *sw_desc;
676 struct msi_desc *msi_desc;
677
678 BUILD_BUG_ON(sizeof(struct mv_xor_v2_descriptor) !=
679 MV_XOR_V2_EXT_DESC_SIZE);
680
681 xor_dev = devm_kzalloc(&pdev->dev, sizeof(*xor_dev), GFP_KERNEL);
682 if (!xor_dev)
683 return -ENOMEM;
684
685 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
686 xor_dev->dma_base = devm_ioremap_resource(&pdev->dev, res);
687 if (IS_ERR(xor_dev->dma_base))
688 return PTR_ERR(xor_dev->dma_base);
689
690 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
691 xor_dev->glob_base = devm_ioremap_resource(&pdev->dev, res);
692 if (IS_ERR(xor_dev->glob_base))
693 return PTR_ERR(xor_dev->glob_base);
694
695 platform_set_drvdata(pdev, xor_dev);
696
Thomas Petazzoni1f67d282017-05-05 11:57:50 +0200697 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
698 if (ret)
699 return ret;
700
Gregory CLEMENT3bdcced2018-03-07 16:40:10 +0100701 xor_dev->reg_clk = devm_clk_get(&pdev->dev, "reg");
702 if (PTR_ERR(xor_dev->reg_clk) != -ENOENT) {
703 if (!IS_ERR(xor_dev->reg_clk)) {
704 ret = clk_prepare_enable(xor_dev->reg_clk);
705 if (ret)
706 return ret;
707 } else {
708 return PTR_ERR(xor_dev->reg_clk);
709 }
710 }
711
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200712 xor_dev->clk = devm_clk_get(&pdev->dev, NULL);
Gregory CLEMENT3bdcced2018-03-07 16:40:10 +0100713 if (IS_ERR(xor_dev->clk) && PTR_ERR(xor_dev->clk) == -EPROBE_DEFER) {
714 ret = EPROBE_DEFER;
715 goto disable_reg_clk;
716 }
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200717 if (!IS_ERR(xor_dev->clk)) {
718 ret = clk_prepare_enable(xor_dev->clk);
719 if (ret)
Gregory CLEMENT3bdcced2018-03-07 16:40:10 +0100720 goto disable_reg_clk;
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200721 }
722
723 ret = platform_msi_domain_alloc_irqs(&pdev->dev, 1,
724 mv_xor_v2_set_msi_msg);
725 if (ret)
726 goto disable_clk;
727
728 msi_desc = first_msi_entry(&pdev->dev);
729 if (!msi_desc)
730 goto free_msi_irqs;
731
732 ret = devm_request_irq(&pdev->dev, msi_desc->irq,
733 mv_xor_v2_interrupt_handler, 0,
734 dev_name(&pdev->dev), xor_dev);
735 if (ret)
736 goto free_msi_irqs;
737
738 tasklet_init(&xor_dev->irq_tasklet, mv_xor_v2_tasklet,
739 (unsigned long) xor_dev);
740
741 xor_dev->desc_size = mv_xor_v2_set_desc_size(xor_dev);
742
743 dma_cookie_init(&xor_dev->dmachan);
744
745 /*
746 * allocate coherent memory for hardware descriptors
747 * note: writecombine gives slightly better performance, but
748 * requires that we explicitly flush the writes
749 */
750 xor_dev->hw_desq_virt =
751 dma_alloc_coherent(&pdev->dev,
752 xor_dev->desc_size * MV_XOR_V2_DESC_NUM,
753 &xor_dev->hw_desq, GFP_KERNEL);
754 if (!xor_dev->hw_desq_virt) {
755 ret = -ENOMEM;
756 goto free_msi_irqs;
757 }
758
759 /* alloc memory for the SW descriptors */
760 xor_dev->sw_desq = devm_kzalloc(&pdev->dev, sizeof(*sw_desc) *
761 MV_XOR_V2_DESC_NUM, GFP_KERNEL);
762 if (!xor_dev->sw_desq) {
763 ret = -ENOMEM;
764 goto free_hw_desq;
765 }
766
767 spin_lock_init(&xor_dev->lock);
768
769 /* init the free SW descriptors list */
770 INIT_LIST_HEAD(&xor_dev->free_sw_desc);
771
772 /* add all SW descriptors to the free list */
773 for (i = 0; i < MV_XOR_V2_DESC_NUM; i++) {
Thomas Petazzonie2a092e2017-05-05 11:57:46 +0200774 struct mv_xor_v2_sw_desc *sw_desc =
775 xor_dev->sw_desq + i;
776 sw_desc->idx = i;
777 dma_async_tx_descriptor_init(&sw_desc->async_tx,
778 &xor_dev->dmachan);
779 sw_desc->async_tx.tx_submit = mv_xor_v2_tx_submit;
780 async_tx_ack(&sw_desc->async_tx);
781
782 list_add(&sw_desc->free_list,
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200783 &xor_dev->free_sw_desc);
784 }
785
786 dma_dev = &xor_dev->dmadev;
787
788 /* set DMA capabilities */
789 dma_cap_zero(dma_dev->cap_mask);
790 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
791 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
792 dma_cap_set(DMA_INTERRUPT, dma_dev->cap_mask);
793
794 /* init dma link list */
795 INIT_LIST_HEAD(&dma_dev->channels);
796
797 /* set base routines */
798 dma_dev->device_tx_status = dma_cookie_status;
799 dma_dev->device_issue_pending = mv_xor_v2_issue_pending;
800 dma_dev->dev = &pdev->dev;
801
802 dma_dev->device_prep_dma_memcpy = mv_xor_v2_prep_dma_memcpy;
803 dma_dev->device_prep_dma_interrupt = mv_xor_v2_prep_dma_interrupt;
804 dma_dev->max_xor = 8;
805 dma_dev->device_prep_dma_xor = mv_xor_v2_prep_dma_xor;
806
807 xor_dev->dmachan.device = dma_dev;
808
809 list_add_tail(&xor_dev->dmachan.device_node,
810 &dma_dev->channels);
811
812 mv_xor_v2_descq_init(xor_dev);
813
814 ret = dma_async_device_register(dma_dev);
815 if (ret)
816 goto free_hw_desq;
817
818 dev_notice(&pdev->dev, "Marvell Version 2 XOR driver\n");
819
820 return 0;
821
822free_hw_desq:
823 dma_free_coherent(&pdev->dev,
824 xor_dev->desc_size * MV_XOR_V2_DESC_NUM,
825 xor_dev->hw_desq_virt, xor_dev->hw_desq);
826free_msi_irqs:
827 platform_msi_domain_free_irqs(&pdev->dev);
828disable_clk:
Gregory CLEMENT3bdcced2018-03-07 16:40:10 +0100829 clk_disable_unprepare(xor_dev->clk);
830disable_reg_clk:
831 clk_disable_unprepare(xor_dev->reg_clk);
Thomas Petazzoni19a340b2016-06-16 14:28:34 +0200832 return ret;
833}
834
835static int mv_xor_v2_remove(struct platform_device *pdev)
836{
837 struct mv_xor_v2_device *xor_dev = platform_get_drvdata(pdev);
838
839 dma_async_device_unregister(&xor_dev->dmadev);
840
841 dma_free_coherent(&pdev->dev,
842 xor_dev->desc_size * MV_XOR_V2_DESC_NUM,
843 xor_dev->hw_desq_virt, xor_dev->hw_desq);
844
845 platform_msi_domain_free_irqs(&pdev->dev);
846
847 clk_disable_unprepare(xor_dev->clk);
848
849 return 0;
850}
851
852#ifdef CONFIG_OF
853static const struct of_device_id mv_xor_v2_dt_ids[] = {
854 { .compatible = "marvell,xor-v2", },
855 {},
856};
857MODULE_DEVICE_TABLE(of, mv_xor_v2_dt_ids);
858#endif
859
860static struct platform_driver mv_xor_v2_driver = {
861 .probe = mv_xor_v2_probe,
862 .remove = mv_xor_v2_remove,
863 .driver = {
864 .name = "mv_xor_v2",
865 .of_match_table = of_match_ptr(mv_xor_v2_dt_ids),
866 },
867};
868
869module_platform_driver(mv_xor_v2_driver);
870
871MODULE_DESCRIPTION("DMA engine driver for Marvell's Version 2 of XOR engine");
872MODULE_LICENSE("GPL");