Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Atheros AR71XX/AR724X/AR913X common routines |
| 3 | * |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 4 | * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 5 | * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> |
| 6 | * |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 7 | * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP |
| 8 | * |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License version 2 as published |
| 11 | * by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/clk.h> |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 19 | #include <linux/clkdev.h> |
Alban Bedel | 411520a | 2015-04-19 14:30:04 +0200 | [diff] [blame] | 20 | #include <linux/clk-provider.h> |
Antony Pavlov | 3bdf107 | 2016-03-17 06:34:15 +0300 | [diff] [blame^] | 21 | #include <linux/of.h> |
| 22 | #include <linux/of_address.h> |
Antony Pavlov | af5ad0d | 2016-03-17 06:34:14 +0300 | [diff] [blame] | 23 | #include <dt-bindings/clock/ath79-clk.h> |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 24 | |
Gabor Juhos | 97541cc | 2012-09-08 14:02:21 +0200 | [diff] [blame] | 25 | #include <asm/div64.h> |
| 26 | |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 27 | #include <asm/mach-ath79/ath79.h> |
| 28 | #include <asm/mach-ath79/ar71xx_regs.h> |
| 29 | #include "common.h" |
Antony Pavlov | 3bdf107 | 2016-03-17 06:34:15 +0300 | [diff] [blame^] | 30 | #include "machtypes.h" |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 31 | |
| 32 | #define AR71XX_BASE_FREQ 40000000 |
Weijie Gao | c338d59 | 2016-03-17 06:34:09 +0300 | [diff] [blame] | 33 | #define AR724X_BASE_FREQ 40000000 |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 34 | |
Antony Pavlov | af5ad0d | 2016-03-17 06:34:14 +0300 | [diff] [blame] | 35 | static struct clk *clks[ATH79_CLK_END]; |
Alban Bedel | 6451af0 | 2015-05-31 02:18:22 +0200 | [diff] [blame] | 36 | static struct clk_onecell_data clk_data = { |
| 37 | .clks = clks, |
| 38 | .clk_num = ARRAY_SIZE(clks), |
| 39 | }; |
| 40 | |
| 41 | static struct clk *__init ath79_add_sys_clkdev( |
| 42 | const char *id, unsigned long rate) |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 43 | { |
| 44 | struct clk *clk; |
| 45 | int err; |
| 46 | |
Alban Bedel | 411520a | 2015-04-19 14:30:04 +0200 | [diff] [blame] | 47 | clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate); |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 48 | if (!clk) |
| 49 | panic("failed to allocate %s clock structure", id); |
| 50 | |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 51 | err = clk_register_clkdev(clk, id, NULL); |
| 52 | if (err) |
| 53 | panic("unable to register %s clock device", id); |
Alban Bedel | 6451af0 | 2015-05-31 02:18:22 +0200 | [diff] [blame] | 54 | |
| 55 | return clk; |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 56 | } |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 57 | |
| 58 | static void __init ar71xx_clocks_init(void) |
| 59 | { |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 60 | unsigned long ref_rate; |
| 61 | unsigned long cpu_rate; |
| 62 | unsigned long ddr_rate; |
| 63 | unsigned long ahb_rate; |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 64 | u32 pll; |
| 65 | u32 freq; |
| 66 | u32 div; |
| 67 | |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 68 | ref_rate = AR71XX_BASE_FREQ; |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 69 | |
| 70 | pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); |
| 71 | |
Alban Bedel | 626a069 | 2015-04-19 14:30:02 +0200 | [diff] [blame] | 72 | div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 73 | freq = div * ref_rate; |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 74 | |
| 75 | div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 76 | cpu_rate = freq / div; |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 77 | |
| 78 | div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 79 | ddr_rate = freq / div; |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 80 | |
| 81 | div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 82 | ahb_rate = cpu_rate / div; |
| 83 | |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 84 | ath79_add_sys_clkdev("ref", ref_rate); |
Antony Pavlov | af5ad0d | 2016-03-17 06:34:14 +0300 | [diff] [blame] | 85 | clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); |
| 86 | clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); |
| 87 | clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 88 | |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 89 | clk_add_alias("wdt", NULL, "ahb", NULL); |
| 90 | clk_add_alias("uart", NULL, "ahb", NULL); |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 91 | } |
| 92 | |
Antony Pavlov | 3bdf107 | 2016-03-17 06:34:15 +0300 | [diff] [blame^] | 93 | static struct clk * __init ath79_reg_ffclk(const char *name, |
| 94 | const char *parent_name, unsigned int mult, unsigned int div) |
| 95 | { |
| 96 | struct clk *clk; |
| 97 | |
| 98 | clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); |
| 99 | if (!clk) |
| 100 | panic("failed to allocate %s clock structure", name); |
| 101 | |
| 102 | return clk; |
| 103 | } |
| 104 | |
| 105 | static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base) |
| 106 | { |
| 107 | u32 pll; |
| 108 | u32 mult, div, ddr_div, ahb_div; |
| 109 | |
| 110 | pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); |
| 111 | |
| 112 | mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); |
| 113 | div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; |
| 114 | |
| 115 | ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; |
| 116 | ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; |
| 117 | |
| 118 | clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div); |
| 119 | clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div); |
| 120 | clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div); |
| 121 | } |
| 122 | |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 123 | static void __init ar724x_clocks_init(void) |
| 124 | { |
Antony Pavlov | 3bdf107 | 2016-03-17 06:34:15 +0300 | [diff] [blame^] | 125 | struct clk *ref_clk; |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 126 | |
Antony Pavlov | 3bdf107 | 2016-03-17 06:34:15 +0300 | [diff] [blame^] | 127 | ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ); |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 128 | |
Antony Pavlov | 3bdf107 | 2016-03-17 06:34:15 +0300 | [diff] [blame^] | 129 | ar724x_clk_init(ref_clk, ath79_pll_base); |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 130 | |
Antony Pavlov | 3bdf107 | 2016-03-17 06:34:15 +0300 | [diff] [blame^] | 131 | /* just make happy plat_time_init() from arch/mips/ath79/setup.c */ |
| 132 | clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL); |
| 133 | clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL); |
| 134 | clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL); |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 135 | |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 136 | clk_add_alias("wdt", NULL, "ahb", NULL); |
| 137 | clk_add_alias("uart", NULL, "ahb", NULL); |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 138 | } |
| 139 | |
Gabor Juhos | 04225e1 | 2011-06-20 21:26:04 +0200 | [diff] [blame] | 140 | static void __init ar933x_clocks_init(void) |
| 141 | { |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 142 | unsigned long ref_rate; |
| 143 | unsigned long cpu_rate; |
| 144 | unsigned long ddr_rate; |
| 145 | unsigned long ahb_rate; |
Gabor Juhos | 04225e1 | 2011-06-20 21:26:04 +0200 | [diff] [blame] | 146 | u32 clock_ctrl; |
| 147 | u32 cpu_config; |
| 148 | u32 freq; |
| 149 | u32 t; |
| 150 | |
| 151 | t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); |
| 152 | if (t & AR933X_BOOTSTRAP_REF_CLK_40) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 153 | ref_rate = (40 * 1000 * 1000); |
Gabor Juhos | 04225e1 | 2011-06-20 21:26:04 +0200 | [diff] [blame] | 154 | else |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 155 | ref_rate = (25 * 1000 * 1000); |
Gabor Juhos | 04225e1 | 2011-06-20 21:26:04 +0200 | [diff] [blame] | 156 | |
| 157 | clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG); |
| 158 | if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 159 | cpu_rate = ref_rate; |
| 160 | ahb_rate = ref_rate; |
| 161 | ddr_rate = ref_rate; |
Gabor Juhos | 04225e1 | 2011-06-20 21:26:04 +0200 | [diff] [blame] | 162 | } else { |
| 163 | cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG); |
| 164 | |
| 165 | t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & |
| 166 | AR933X_PLL_CPU_CONFIG_REFDIV_MASK; |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 167 | freq = ref_rate / t; |
Gabor Juhos | 04225e1 | 2011-06-20 21:26:04 +0200 | [diff] [blame] | 168 | |
| 169 | t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & |
| 170 | AR933X_PLL_CPU_CONFIG_NINT_MASK; |
| 171 | freq *= t; |
| 172 | |
| 173 | t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & |
| 174 | AR933X_PLL_CPU_CONFIG_OUTDIV_MASK; |
| 175 | if (t == 0) |
| 176 | t = 1; |
| 177 | |
| 178 | freq >>= t; |
| 179 | |
| 180 | t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & |
| 181 | AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 182 | cpu_rate = freq / t; |
Gabor Juhos | 04225e1 | 2011-06-20 21:26:04 +0200 | [diff] [blame] | 183 | |
| 184 | t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & |
| 185 | AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 186 | ddr_rate = freq / t; |
Gabor Juhos | 04225e1 | 2011-06-20 21:26:04 +0200 | [diff] [blame] | 187 | |
| 188 | t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & |
| 189 | AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 190 | ahb_rate = freq / t; |
Gabor Juhos | 04225e1 | 2011-06-20 21:26:04 +0200 | [diff] [blame] | 191 | } |
| 192 | |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 193 | ath79_add_sys_clkdev("ref", ref_rate); |
Antony Pavlov | af5ad0d | 2016-03-17 06:34:14 +0300 | [diff] [blame] | 194 | clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); |
| 195 | clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); |
| 196 | clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 197 | |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 198 | clk_add_alias("wdt", NULL, "ahb", NULL); |
| 199 | clk_add_alias("uart", NULL, "ref", NULL); |
Gabor Juhos | 04225e1 | 2011-06-20 21:26:04 +0200 | [diff] [blame] | 200 | } |
| 201 | |
Gabor Juhos | 97541cc | 2012-09-08 14:02:21 +0200 | [diff] [blame] | 202 | static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, |
| 203 | u32 frac, u32 out_div) |
| 204 | { |
| 205 | u64 t; |
| 206 | u32 ret; |
| 207 | |
Gabor Juhos | 837f036 | 2013-08-28 10:41:43 +0200 | [diff] [blame] | 208 | t = ref; |
Gabor Juhos | 97541cc | 2012-09-08 14:02:21 +0200 | [diff] [blame] | 209 | t *= nint; |
| 210 | do_div(t, ref_div); |
| 211 | ret = t; |
| 212 | |
Gabor Juhos | 837f036 | 2013-08-28 10:41:43 +0200 | [diff] [blame] | 213 | t = ref; |
Gabor Juhos | 97541cc | 2012-09-08 14:02:21 +0200 | [diff] [blame] | 214 | t *= nfrac; |
| 215 | do_div(t, ref_div * frac); |
| 216 | ret += t; |
| 217 | |
| 218 | ret /= (1 << out_div); |
| 219 | return ret; |
| 220 | } |
| 221 | |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 222 | static void __init ar934x_clocks_init(void) |
| 223 | { |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 224 | unsigned long ref_rate; |
| 225 | unsigned long cpu_rate; |
| 226 | unsigned long ddr_rate; |
| 227 | unsigned long ahb_rate; |
Gabor Juhos | 97541cc | 2012-09-08 14:02:21 +0200 | [diff] [blame] | 228 | u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 229 | u32 cpu_pll, ddr_pll; |
| 230 | u32 bootstrap; |
Gabor Juhos | 97541cc | 2012-09-08 14:02:21 +0200 | [diff] [blame] | 231 | void __iomem *dpll_base; |
| 232 | |
| 233 | dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE); |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 234 | |
| 235 | bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 236 | if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 237 | ref_rate = 40 * 1000 * 1000; |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 238 | else |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 239 | ref_rate = 25 * 1000 * 1000; |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 240 | |
Gabor Juhos | 97541cc | 2012-09-08 14:02:21 +0200 | [diff] [blame] | 241 | pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); |
| 242 | if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { |
| 243 | out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & |
| 244 | AR934X_SRIF_DPLL2_OUTDIV_MASK; |
| 245 | pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); |
| 246 | nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & |
| 247 | AR934X_SRIF_DPLL1_NINT_MASK; |
| 248 | nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; |
| 249 | ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & |
| 250 | AR934X_SRIF_DPLL1_REFDIV_MASK; |
| 251 | frac = 1 << 18; |
| 252 | } else { |
| 253 | pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); |
| 254 | out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & |
| 255 | AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; |
| 256 | ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & |
| 257 | AR934X_PLL_CPU_CONFIG_REFDIV_MASK; |
| 258 | nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & |
| 259 | AR934X_PLL_CPU_CONFIG_NINT_MASK; |
| 260 | nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & |
| 261 | AR934X_PLL_CPU_CONFIG_NFRAC_MASK; |
| 262 | frac = 1 << 6; |
| 263 | } |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 264 | |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 265 | cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, |
Gabor Juhos | 97541cc | 2012-09-08 14:02:21 +0200 | [diff] [blame] | 266 | nfrac, frac, out_div); |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 267 | |
Gabor Juhos | 97541cc | 2012-09-08 14:02:21 +0200 | [diff] [blame] | 268 | pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); |
| 269 | if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { |
| 270 | out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & |
| 271 | AR934X_SRIF_DPLL2_OUTDIV_MASK; |
| 272 | pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); |
| 273 | nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & |
| 274 | AR934X_SRIF_DPLL1_NINT_MASK; |
| 275 | nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; |
| 276 | ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & |
| 277 | AR934X_SRIF_DPLL1_REFDIV_MASK; |
| 278 | frac = 1 << 18; |
| 279 | } else { |
| 280 | pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); |
| 281 | out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & |
| 282 | AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; |
| 283 | ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & |
| 284 | AR934X_PLL_DDR_CONFIG_REFDIV_MASK; |
| 285 | nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & |
| 286 | AR934X_PLL_DDR_CONFIG_NINT_MASK; |
| 287 | nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & |
| 288 | AR934X_PLL_DDR_CONFIG_NFRAC_MASK; |
| 289 | frac = 1 << 10; |
| 290 | } |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 291 | |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 292 | ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, |
Gabor Juhos | 97541cc | 2012-09-08 14:02:21 +0200 | [diff] [blame] | 293 | nfrac, frac, out_div); |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 294 | |
| 295 | clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); |
| 296 | |
| 297 | postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & |
| 298 | AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; |
| 299 | |
| 300 | if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 301 | cpu_rate = ref_rate; |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 302 | else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 303 | cpu_rate = cpu_pll / (postdiv + 1); |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 304 | else |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 305 | cpu_rate = ddr_pll / (postdiv + 1); |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 306 | |
| 307 | postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & |
| 308 | AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; |
| 309 | |
| 310 | if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 311 | ddr_rate = ref_rate; |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 312 | else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 313 | ddr_rate = ddr_pll / (postdiv + 1); |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 314 | else |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 315 | ddr_rate = cpu_pll / (postdiv + 1); |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 316 | |
| 317 | postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & |
| 318 | AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; |
| 319 | |
| 320 | if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 321 | ahb_rate = ref_rate; |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 322 | else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 323 | ahb_rate = ddr_pll / (postdiv + 1); |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 324 | else |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 325 | ahb_rate = cpu_pll / (postdiv + 1); |
| 326 | |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 327 | ath79_add_sys_clkdev("ref", ref_rate); |
Antony Pavlov | af5ad0d | 2016-03-17 06:34:14 +0300 | [diff] [blame] | 328 | clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); |
| 329 | clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); |
| 330 | clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 331 | |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 332 | clk_add_alias("wdt", NULL, "ref", NULL); |
| 333 | clk_add_alias("uart", NULL, "ref", NULL); |
Gabor Juhos | 97541cc | 2012-09-08 14:02:21 +0200 | [diff] [blame] | 334 | |
| 335 | iounmap(dpll_base); |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 336 | } |
| 337 | |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 338 | static void __init qca955x_clocks_init(void) |
| 339 | { |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 340 | unsigned long ref_rate; |
| 341 | unsigned long cpu_rate; |
| 342 | unsigned long ddr_rate; |
| 343 | unsigned long ahb_rate; |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 344 | u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; |
| 345 | u32 cpu_pll, ddr_pll; |
| 346 | u32 bootstrap; |
| 347 | |
| 348 | bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); |
| 349 | if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 350 | ref_rate = 40 * 1000 * 1000; |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 351 | else |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 352 | ref_rate = 25 * 1000 * 1000; |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 353 | |
| 354 | pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); |
| 355 | out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & |
| 356 | QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; |
| 357 | ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & |
| 358 | QCA955X_PLL_CPU_CONFIG_REFDIV_MASK; |
| 359 | nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & |
| 360 | QCA955X_PLL_CPU_CONFIG_NINT_MASK; |
| 361 | frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & |
| 362 | QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; |
| 363 | |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 364 | cpu_pll = nint * ref_rate / ref_div; |
| 365 | cpu_pll += frac * ref_rate / (ref_div * (1 << 6)); |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 366 | cpu_pll /= (1 << out_div); |
| 367 | |
| 368 | pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); |
| 369 | out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & |
| 370 | QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK; |
| 371 | ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & |
| 372 | QCA955X_PLL_DDR_CONFIG_REFDIV_MASK; |
| 373 | nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & |
| 374 | QCA955X_PLL_DDR_CONFIG_NINT_MASK; |
| 375 | frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & |
| 376 | QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; |
| 377 | |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 378 | ddr_pll = nint * ref_rate / ref_div; |
| 379 | ddr_pll += frac * ref_rate / (ref_div * (1 << 10)); |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 380 | ddr_pll /= (1 << out_div); |
| 381 | |
| 382 | clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); |
| 383 | |
| 384 | postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & |
| 385 | QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; |
| 386 | |
| 387 | if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 388 | cpu_rate = ref_rate; |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 389 | else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 390 | cpu_rate = ddr_pll / (postdiv + 1); |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 391 | else |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 392 | cpu_rate = cpu_pll / (postdiv + 1); |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 393 | |
| 394 | postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & |
| 395 | QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; |
| 396 | |
| 397 | if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 398 | ddr_rate = ref_rate; |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 399 | else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 400 | ddr_rate = cpu_pll / (postdiv + 1); |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 401 | else |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 402 | ddr_rate = ddr_pll / (postdiv + 1); |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 403 | |
| 404 | postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & |
| 405 | QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; |
| 406 | |
| 407 | if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 408 | ahb_rate = ref_rate; |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 409 | else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 410 | ahb_rate = ddr_pll / (postdiv + 1); |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 411 | else |
Gabor Juhos | 6612a68 | 2013-08-28 10:41:46 +0200 | [diff] [blame] | 412 | ahb_rate = cpu_pll / (postdiv + 1); |
| 413 | |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 414 | ath79_add_sys_clkdev("ref", ref_rate); |
Antony Pavlov | af5ad0d | 2016-03-17 06:34:14 +0300 | [diff] [blame] | 415 | clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); |
| 416 | clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); |
| 417 | clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 418 | |
Gabor Juhos | 2c4f1ac | 2013-08-28 10:41:47 +0200 | [diff] [blame] | 419 | clk_add_alias("wdt", NULL, "ref", NULL); |
| 420 | clk_add_alias("uart", NULL, "ref", NULL); |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 421 | } |
| 422 | |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 423 | void __init ath79_clocks_init(void) |
| 424 | { |
| 425 | if (soc_is_ar71xx()) |
| 426 | ar71xx_clocks_init(); |
Alban Bedel | f4c87b7 | 2016-03-17 06:34:10 +0300 | [diff] [blame] | 427 | else if (soc_is_ar724x() || soc_is_ar913x()) |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 428 | ar724x_clocks_init(); |
Gabor Juhos | 04225e1 | 2011-06-20 21:26:04 +0200 | [diff] [blame] | 429 | else if (soc_is_ar933x()) |
| 430 | ar933x_clocks_init(); |
Gabor Juhos | 8889612 | 2012-03-14 10:45:22 +0100 | [diff] [blame] | 431 | else if (soc_is_ar934x()) |
| 432 | ar934x_clocks_init(); |
Gabor Juhos | 41583c0 | 2013-02-15 13:38:17 +0000 | [diff] [blame] | 433 | else if (soc_is_qca955x()) |
| 434 | qca955x_clocks_init(); |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 435 | else |
| 436 | BUG(); |
Gabor Juhos | d4a67d9 | 2011-01-04 21:28:14 +0100 | [diff] [blame] | 437 | } |
| 438 | |
Gabor Juhos | 2310780 | 2013-08-28 10:41:44 +0200 | [diff] [blame] | 439 | unsigned long __init |
| 440 | ath79_get_sys_clk_rate(const char *id) |
| 441 | { |
| 442 | struct clk *clk; |
| 443 | unsigned long rate; |
| 444 | |
| 445 | clk = clk_get(NULL, id); |
| 446 | if (IS_ERR(clk)) |
| 447 | panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk)); |
| 448 | |
| 449 | rate = clk_get_rate(clk); |
| 450 | clk_put(clk); |
| 451 | |
| 452 | return rate; |
| 453 | } |
Alban Bedel | 6451af0 | 2015-05-31 02:18:22 +0200 | [diff] [blame] | 454 | |
| 455 | #ifdef CONFIG_OF |
| 456 | static void __init ath79_clocks_init_dt(struct device_node *np) |
| 457 | { |
| 458 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
| 459 | } |
| 460 | |
| 461 | CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt); |
| 462 | CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt); |
Alban Bedel | 6451af0 | 2015-05-31 02:18:22 +0200 | [diff] [blame] | 463 | CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt); |
| 464 | CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt); |
| 465 | CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt); |
Antony Pavlov | 3bdf107 | 2016-03-17 06:34:15 +0300 | [diff] [blame^] | 466 | |
| 467 | static void __init ath79_clocks_init_dt_ng(struct device_node *np) |
| 468 | { |
| 469 | struct clk *ref_clk; |
| 470 | void __iomem *pll_base; |
| 471 | const char *dnfn = of_node_full_name(np); |
| 472 | |
| 473 | ref_clk = of_clk_get(np, 0); |
| 474 | if (IS_ERR(ref_clk)) { |
| 475 | pr_err("%s: of_clk_get failed\n", dnfn); |
| 476 | goto err; |
| 477 | } |
| 478 | |
| 479 | pll_base = of_iomap(np, 0); |
| 480 | if (!pll_base) { |
| 481 | pr_err("%s: can't map pll registers\n", dnfn); |
| 482 | goto err_clk; |
| 483 | } |
| 484 | |
| 485 | ar724x_clk_init(ref_clk, pll_base); |
| 486 | |
| 487 | if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { |
| 488 | pr_err("%s: could not register clk provider\n", dnfn); |
| 489 | goto err_clk; |
| 490 | } |
| 491 | |
| 492 | return; |
| 493 | |
| 494 | err_clk: |
| 495 | clk_put(ref_clk); |
| 496 | |
| 497 | err: |
| 498 | return; |
| 499 | } |
| 500 | CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng); |
Alban Bedel | 6451af0 | 2015-05-31 02:18:22 +0200 | [diff] [blame] | 501 | #endif |