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Juergen Beisertd0f349f2008-07-05 10:02:50 +02001/*
2 * linux/arch/arm/plat-mxc/time.c
3 *
4 * Copyright (C) 2000-2001 Deep Blue Solutions
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301, USA.
22 */
23
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/clockchips.h>
27#include <linux/clk.h>
Sascha Hauer821dc4d2012-03-09 09:29:27 +010028#include <linux/err.h>
Juergen Beisertd0f349f2008-07-05 10:02:50 +020029
Russell Kinga09e64f2008-08-05 16:14:15 +010030#include <mach/hardware.h>
Jan Weitzelc124bef2011-03-17 13:44:30 +010031#include <asm/sched_clock.h>
Juergen Beisertd0f349f2008-07-05 10:02:50 +020032#include <asm/mach/time.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010033#include <mach/common.h>
Sascha Hauerec996ba2009-02-18 20:58:40 +010034
Sascha Hauer0f3332c2009-12-04 09:34:51 +010035/*
36 * There are 2 versions of the timer hardware on Freescale MXC hardware.
37 * Version 1: MX1/MXL, MX21, MX27.
38 * Version 2: MX25, MX31, MX35, MX37, MX51
39 */
40
Sascha Hauerec996ba2009-02-18 20:58:40 +010041/* defines common for all i.MX */
42#define MXC_TCTL 0x00
Sascha Hauer0f3332c2009-12-04 09:34:51 +010043#define MXC_TCTL_TEN (1 << 0) /* Enable module */
Sascha Hauerec996ba2009-02-18 20:58:40 +010044#define MXC_TPRER 0x04
45
46/* MX1, MX21, MX27 */
47#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
48#define MX1_2_TCTL_IRQEN (1 << 4)
49#define MX1_2_TCTL_FRR (1 << 8)
50#define MX1_2_TCMP 0x08
51#define MX1_2_TCN 0x10
52#define MX1_2_TSTAT 0x14
53
54/* MX21, MX27 */
55#define MX2_TSTAT_CAPT (1 << 1)
56#define MX2_TSTAT_COMP (1 << 0)
57
Uwe Kleine-König13cf8df2011-04-07 11:13:25 +020058/* MX31, MX35, MX25, MX5 */
Amit Kucheria38a66f52010-04-21 21:34:36 +030059#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
60#define V2_TCTL_CLK_IPG (1 << 6)
Richard Zhao1f152b42012-05-15 15:34:40 +080061#define V2_TCTL_CLK_PER (2 << 6)
Amit Kucheria38a66f52010-04-21 21:34:36 +030062#define V2_TCTL_FRR (1 << 9)
63#define V2_IR 0x0c
64#define V2_TSTAT 0x08
65#define V2_TSTAT_OF1 (1 << 0)
66#define V2_TCN 0x24
67#define V2_TCMP 0x10
Juergen Beisertd0f349f2008-07-05 10:02:50 +020068
Sascha Hauer0f3332c2009-12-04 09:34:51 +010069#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
70#define timer_is_v2() (!timer_is_v1())
71
Juergen Beisertd0f349f2008-07-05 10:02:50 +020072static struct clock_event_device clockevent_mxc;
73static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
74
Sascha Hauerec996ba2009-02-18 20:58:40 +010075static void __iomem *timer_base;
Juergen Beisertd0f349f2008-07-05 10:02:50 +020076
Sascha Hauerec996ba2009-02-18 20:58:40 +010077static inline void gpt_irq_disable(void)
Juergen Beisertd0f349f2008-07-05 10:02:50 +020078{
Sascha Hauerec996ba2009-02-18 20:58:40 +010079 unsigned int tmp;
80
Sascha Hauer0f3332c2009-12-04 09:34:51 +010081 if (timer_is_v2())
Amit Kucheria38a66f52010-04-21 21:34:36 +030082 __raw_writel(0, timer_base + V2_IR);
Sascha Hauerec996ba2009-02-18 20:58:40 +010083 else {
84 tmp = __raw_readl(timer_base + MXC_TCTL);
85 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
86 }
87}
88
89static inline void gpt_irq_enable(void)
90{
Sascha Hauer0f3332c2009-12-04 09:34:51 +010091 if (timer_is_v2())
Amit Kucheria38a66f52010-04-21 21:34:36 +030092 __raw_writel(1<<0, timer_base + V2_IR);
Sascha Hauerec996ba2009-02-18 20:58:40 +010093 else {
94 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
95 timer_base + MXC_TCTL);
96 }
97}
98
99static void gpt_irq_acknowledge(void)
100{
Sascha Hauer0f3332c2009-12-04 09:34:51 +0100101 if (timer_is_v1()) {
102 if (cpu_is_mx1())
103 __raw_writel(0, timer_base + MX1_2_TSTAT);
104 else
105 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
106 timer_base + MX1_2_TSTAT);
107 } else if (timer_is_v2())
Wolfram Sangd943f2c2010-04-23 06:49:43 +0200108 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100109}
110
Russell King234b6ced2011-05-08 14:09:47 +0100111static void __iomem *sched_clock_reg;
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200112
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100113static u32 notrace mxc_read_sched_clock(void)
Jan Weitzelc124bef2011-03-17 13:44:30 +0100114{
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100115 return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
Jan Weitzelc124bef2011-03-17 13:44:30 +0100116}
117
Sascha Hauer30c730f2009-02-16 14:36:49 +0100118static int __init mxc_clocksource_init(struct clk *timer_clk)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200119{
Holger Schurig058b7a62009-01-26 16:34:51 +0100120 unsigned int c = clk_get_rate(timer_clk);
Russell King234b6ced2011-05-08 14:09:47 +0100121 void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200122
Russell King234b6ced2011-05-08 14:09:47 +0100123 sched_clock_reg = reg;
Sascha Hauerec996ba2009-02-18 20:58:40 +0100124
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100125 setup_sched_clock(mxc_read_sched_clock, 32, c);
Russell King234b6ced2011-05-08 14:09:47 +0100126 return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
127 clocksource_mmio_readl_up);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200128}
129
130/* clock event */
131
Sascha Hauerec996ba2009-02-18 20:58:40 +0100132static int mx1_2_set_next_event(unsigned long evt,
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200133 struct clock_event_device *unused)
134{
135 unsigned long tcmp;
136
Sascha Hauerec996ba2009-02-18 20:58:40 +0100137 tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200138
Sascha Hauerec996ba2009-02-18 20:58:40 +0100139 __raw_writel(tcmp, timer_base + MX1_2_TCMP);
140
141 return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
142 -ETIME : 0;
143}
144
Amit Kucheria38a66f52010-04-21 21:34:36 +0300145static int v2_set_next_event(unsigned long evt,
Sascha Hauerec996ba2009-02-18 20:58:40 +0100146 struct clock_event_device *unused)
147{
148 unsigned long tcmp;
149
Amit Kucheria38a66f52010-04-21 21:34:36 +0300150 tcmp = __raw_readl(timer_base + V2_TCN) + evt;
Sascha Hauerec996ba2009-02-18 20:58:40 +0100151
Amit Kucheria38a66f52010-04-21 21:34:36 +0300152 __raw_writel(tcmp, timer_base + V2_TCMP);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100153
Amit Kucheria38a66f52010-04-21 21:34:36 +0300154 return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200155 -ETIME : 0;
156}
157
158#ifdef DEBUG
159static const char *clock_event_mode_label[] = {
160 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
161 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
162 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
Uwe Kleine-Königde9c5152012-07-16 22:07:06 +0200163 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
164 [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200165};
166#endif /* DEBUG */
167
168static void mxc_set_mode(enum clock_event_mode mode,
169 struct clock_event_device *evt)
170{
171 unsigned long flags;
172
173 /*
174 * The timer interrupt generation is disabled at least
175 * for enough time to call mxc_set_next_event()
176 */
177 local_irq_save(flags);
178
179 /* Disable interrupt in GPT module */
180 gpt_irq_disable();
181
182 if (mode != clockevent_mode) {
183 /* Set event time into far-far future */
Sascha Hauer0f3332c2009-12-04 09:34:51 +0100184 if (timer_is_v2())
Amit Kucheria38a66f52010-04-21 21:34:36 +0300185 __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
186 timer_base + V2_TCMP);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100187 else
188 __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
189 timer_base + MX1_2_TCMP);
190
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200191 /* Clear pending interrupt */
192 gpt_irq_acknowledge();
193 }
194
195#ifdef DEBUG
196 printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
197 clock_event_mode_label[clockevent_mode],
198 clock_event_mode_label[mode]);
199#endif /* DEBUG */
200
201 /* Remember timer mode */
202 clockevent_mode = mode;
203 local_irq_restore(flags);
204
205 switch (mode) {
206 case CLOCK_EVT_MODE_PERIODIC:
207 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
208 "supported for i.MX\n");
209 break;
210 case CLOCK_EVT_MODE_ONESHOT:
211 /*
212 * Do not put overhead of interrupt enable/disable into
213 * mxc_set_next_event(), the core has about 4 minutes
214 * to call mxc_set_next_event() or shutdown clock after
215 * mode switching
216 */
217 local_irq_save(flags);
218 gpt_irq_enable();
219 local_irq_restore(flags);
220 break;
221 case CLOCK_EVT_MODE_SHUTDOWN:
222 case CLOCK_EVT_MODE_UNUSED:
223 case CLOCK_EVT_MODE_RESUME:
224 /* Left event sources disabled, no more interrupts appear */
225 break;
226 }
227}
228
229/*
230 * IRQ handler for the timer
231 */
232static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
233{
234 struct clock_event_device *evt = &clockevent_mxc;
235 uint32_t tstat;
236
Sascha Hauer0f3332c2009-12-04 09:34:51 +0100237 if (timer_is_v2())
Amit Kucheria38a66f52010-04-21 21:34:36 +0300238 tstat = __raw_readl(timer_base + V2_TSTAT);
Sascha Hauer81ec1f92009-04-29 13:55:13 +0200239 else
240 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200241
242 gpt_irq_acknowledge();
243
244 evt->event_handler(evt);
245
246 return IRQ_HANDLED;
247}
248
249static struct irqaction mxc_timer_irq = {
250 .name = "i.MX Timer Tick",
251 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
252 .handler = mxc_timer_interrupt,
253};
254
255static struct clock_event_device clockevent_mxc = {
256 .name = "mxc_timer1",
257 .features = CLOCK_EVT_FEAT_ONESHOT,
258 .shift = 32,
259 .set_mode = mxc_set_mode,
Sascha Hauerec996ba2009-02-18 20:58:40 +0100260 .set_next_event = mx1_2_set_next_event,
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200261 .rating = 200,
262};
263
Sascha Hauer30c730f2009-02-16 14:36:49 +0100264static int __init mxc_clockevent_init(struct clk *timer_clk)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200265{
Holger Schurig058b7a62009-01-26 16:34:51 +0100266 unsigned int c = clk_get_rate(timer_clk);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200267
Sascha Hauer0f3332c2009-12-04 09:34:51 +0100268 if (timer_is_v2())
Amit Kucheria38a66f52010-04-21 21:34:36 +0300269 clockevent_mxc.set_next_event = v2_set_next_event;
Sascha Hauerec996ba2009-02-18 20:58:40 +0100270
Holger Schurig058b7a62009-01-26 16:34:51 +0100271 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200272 clockevent_mxc.shift);
273 clockevent_mxc.max_delta_ns =
274 clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
275 clockevent_mxc.min_delta_ns =
276 clockevent_delta2ns(0xff, &clockevent_mxc);
277
Rusty Russell320ab2b2008-12-13 21:20:26 +1030278 clockevent_mxc.cpumask = cpumask_of(0);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200279
280 clockevents_register_device(&clockevent_mxc);
281
282 return 0;
283}
284
Sascha Hauer2cfb4512012-05-16 12:29:53 +0200285void __init mxc_timer_init(void __iomem *base, int irq)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200286{
Sascha Hauerec996ba2009-02-18 20:58:40 +0100287 uint32_t tctl_val;
Sascha Hauer2cfb4512012-05-16 12:29:53 +0200288 struct clk *timer_clk;
Sascha Hauer821dc4d2012-03-09 09:29:27 +0100289 struct clk *timer_ipg_clk;
290
Sascha Hauer2cfb4512012-05-16 12:29:53 +0200291 timer_clk = clk_get_sys("imx-gpt.0", "per");
292 if (IS_ERR(timer_clk)) {
293 pr_err("i.MX timer: unable to get clk\n");
294 return;
Sascha Hauer821dc4d2012-03-09 09:29:27 +0100295 }
Sascha Hauerec996ba2009-02-18 20:58:40 +0100296
Sascha Hauer2cfb4512012-05-16 12:29:53 +0200297 timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
298 if (!IS_ERR(timer_ipg_clk))
299 clk_prepare_enable(timer_ipg_clk);
300
Richard Zhao46f417d2011-11-15 14:47:57 +0800301 clk_prepare_enable(timer_clk);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200302
Sascha Hauer8db5d1a2009-05-25 12:21:38 +0200303 timer_base = base;
Sascha Hauerec996ba2009-02-18 20:58:40 +0100304
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200305 /*
306 * Initialise to a known state (all timers off, and timing reset)
307 */
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200308
Sascha Hauerec996ba2009-02-18 20:58:40 +0100309 __raw_writel(0, timer_base + MXC_TCTL);
310 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
311
Sascha Hauer0f3332c2009-12-04 09:34:51 +0100312 if (timer_is_v2())
Richard Zhao1f152b42012-05-15 15:34:40 +0800313 tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
Sascha Hauerec996ba2009-02-18 20:58:40 +0100314 else
315 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
316
317 __raw_writel(tctl_val, timer_base + MXC_TCTL);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200318
319 /* init and register the timer to the framework */
Sascha Hauer30c730f2009-02-16 14:36:49 +0100320 mxc_clocksource_init(timer_clk);
321 mxc_clockevent_init(timer_clk);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200322
323 /* Make irqs happen */
Sascha Hauerec996ba2009-02-18 20:58:40 +0100324 setup_irq(irq, &mxc_timer_irq);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200325}