blob: 931dcace5628f4370e9e5c196cdf51773c688786 [file] [log] [blame]
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001/* bnx2x_fw_defs.h: Broadcom Everest network driver.
2 *
Eilon Greenstein2b144022009-02-12 08:38:35 +00003 * Copyright (c) 2007-2009 Broadcom Corporation
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10
Eilon Greenstein34f80b02008-06-23 20:33:01 -070011#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
Eilon Greenstein6378c022008-08-13 15:59:25 -070012 (IS_E1H_OFFSET ? 0x7000 : 0x1000)
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013#define CSTORM_ASSERT_LIST_OFFSET(idx) \
Eilon Greenstein6378c022008-08-13 15:59:25 -070014 (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
Eilon Greensteinca003922009-08-12 22:53:28 -070015#define CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(function, index) \
16 (IS_E1H_OFFSET ? (0x8622 + ((function>>1) * 0x40) + \
17 ((function&1) * 0x100) + (index * 0x4)) : (0x3562 + (function * \
Eilon Greenstein6378c022008-08-13 15:59:25 -070018 0x40) + (index * 0x4)))
Eilon Greensteinca003922009-08-12 22:53:28 -070019#define CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(function, index) \
20 (IS_E1H_OFFSET ? (0x8822 + ((function>>1) * 0x80) + \
21 ((function&1) * 0x200) + (index * 0x4)) : (0x35e2 + (function * \
22 0x80) + (index * 0x4)))
23#define CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(function) \
24 (IS_E1H_OFFSET ? (0x8600 + ((function>>1) * 0x40) + \
25 ((function&1) * 0x100)) : (0x3540 + (function * 0x40)))
26#define CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(function) \
27 (IS_E1H_OFFSET ? (0x8800 + ((function>>1) * 0x80) + \
28 ((function&1) * 0x200)) : (0x35c0 + (function * 0x80)))
29#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(function) \
30 (IS_E1H_OFFSET ? (0x8608 + ((function>>1) * 0x40) + \
31 ((function&1) * 0x100)) : (0x3548 + (function * 0x40)))
32#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(function) \
33 (IS_E1H_OFFSET ? (0x8808 + ((function>>1) * 0x80) + \
34 ((function&1) * 0x200)) : (0x35c8 + (function * 0x80)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -070035#define CSTORM_FUNCTION_MODE_OFFSET \
Eilon Greenstein6378c022008-08-13 15:59:25 -070036 (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
Eilon Greensteinca003922009-08-12 22:53:28 -070037#define CSTORM_HC_BTR_C_OFFSET(port) \
38 (IS_E1H_OFFSET ? (0x8c04 + (port * 0xf0)) : (0x36c4 + (port * 0xc0)))
39#define CSTORM_HC_BTR_U_OFFSET(port) \
40 (IS_E1H_OFFSET ? (0x8de4 + (port * 0xf0)) : (0x3844 + (port * 0xc0)))
41#define CSTORM_ISCSI_CQ_SIZE_OFFSET(function) \
42 (IS_E1H_OFFSET ? (0x6680 + (function * 0x8)) : (0x25a0 + \
43 (function * 0x8)))
44#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
45 (IS_E1H_OFFSET ? (0x66c0 + (function * 0x8)) : (0x25b0 + \
46 (function * 0x8)))
47#define CSTORM_ISCSI_EQ_CONS_OFFSET(function, eqIdx) \
48 (IS_E1H_OFFSET ? (0x6040 + (function * 0xc0) + (eqIdx * 0x18)) : \
49 (0x2410 + (function * 0xc0) + (eqIdx * 0x18)))
50#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(function, eqIdx) \
51 (IS_E1H_OFFSET ? (0x6044 + (function * 0xc0) + (eqIdx * 0x18)) : \
52 (0x2414 + (function * 0xc0) + (eqIdx * 0x18)))
53#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(function, eqIdx) \
54 (IS_E1H_OFFSET ? (0x604c + (function * 0xc0) + (eqIdx * 0x18)) : \
55 (0x241c + (function * 0xc0) + (eqIdx * 0x18)))
56#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(function, eqIdx) \
57 (IS_E1H_OFFSET ? (0x6057 + (function * 0xc0) + (eqIdx * 0x18)) : \
58 (0x2427 + (function * 0xc0) + (eqIdx * 0x18)))
59#define CSTORM_ISCSI_EQ_PROD_OFFSET(function, eqIdx) \
60 (IS_E1H_OFFSET ? (0x6042 + (function * 0xc0) + (eqIdx * 0x18)) : \
61 (0x2412 + (function * 0xc0) + (eqIdx * 0x18)))
62#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(function, eqIdx) \
63 (IS_E1H_OFFSET ? (0x6056 + (function * 0xc0) + (eqIdx * 0x18)) : \
64 (0x2426 + (function * 0xc0) + (eqIdx * 0x18)))
65#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(function, eqIdx) \
66 (IS_E1H_OFFSET ? (0x6054 + (function * 0xc0) + (eqIdx * 0x18)) : \
67 (0x2424 + (function * 0xc0) + (eqIdx * 0x18)))
68#define CSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
69 (IS_E1H_OFFSET ? (0x6640 + (function * 0x8)) : (0x2590 + \
70 (function * 0x8)))
71#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
72 (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x2404 + \
73 (function * 0x8)))
74#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
75 (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x2402 + \
76 (function * 0x8)))
77#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
78 (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x2400 + \
79 (function * 0x8)))
80#define CSTORM_SB_HC_DISABLE_C_OFFSET(port, cpu_id, index) \
81 (IS_E1H_OFFSET ? (0x811a + (port * 0x280) + (cpu_id * 0x28) + \
82 (index * 0x4)) : (0x305a + (port * 0x280) + (cpu_id * 0x28) + \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070083 (index * 0x4)))
Eilon Greensteinca003922009-08-12 22:53:28 -070084#define CSTORM_SB_HC_DISABLE_U_OFFSET(port, cpu_id, index) \
85 (IS_E1H_OFFSET ? (0xb01a + (port * 0x800) + (cpu_id * 0x80) + \
86 (index * 0x4)) : (0x401a + (port * 0x800) + (cpu_id * 0x80) + \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070087 (index * 0x4)))
Eilon Greensteinca003922009-08-12 22:53:28 -070088#define CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, cpu_id, index) \
89 (IS_E1H_OFFSET ? (0x8118 + (port * 0x280) + (cpu_id * 0x28) + \
90 (index * 0x4)) : (0x3058 + (port * 0x280) + (cpu_id * 0x28) + \
91 (index * 0x4)))
92#define CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, cpu_id, index) \
93 (IS_E1H_OFFSET ? (0xb018 + (port * 0x800) + (cpu_id * 0x80) + \
94 (index * 0x4)) : (0x4018 + (port * 0x800) + (cpu_id * 0x80) + \
95 (index * 0x4)))
96#define CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, cpu_id) \
97 (IS_E1H_OFFSET ? (0x8100 + (port * 0x280) + (cpu_id * 0x28)) : \
98 (0x3040 + (port * 0x280) + (cpu_id * 0x28)))
99#define CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, cpu_id) \
100 (IS_E1H_OFFSET ? (0xb000 + (port * 0x800) + (cpu_id * 0x80)) : \
101 (0x4000 + (port * 0x800) + (cpu_id * 0x80)))
102#define CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, cpu_id) \
103 (IS_E1H_OFFSET ? (0x8108 + (port * 0x280) + (cpu_id * 0x28)) : \
104 (0x3048 + (port * 0x280) + (cpu_id * 0x28)))
105#define CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, cpu_id) \
106 (IS_E1H_OFFSET ? (0xb008 + (port * 0x800) + (cpu_id * 0x80)) : \
107 (0x4008 + (port * 0x800) + (cpu_id * 0x80)))
108#define CSTORM_SB_STATUS_BLOCK_C_SIZE 0x10
109#define CSTORM_SB_STATUS_BLOCK_U_SIZE 0x60
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700110#define CSTORM_STATS_FLAGS_OFFSET(function) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700111 (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700112 (function * 0x8)))
113#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700114 (IS_E1H_OFFSET ? (0x3200 + (function * 0x20)) : 0xffffffff)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700115#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700116 (IS_E1H_OFFSET ? 0xa000 : 0x1000)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700117#define TSTORM_ASSERT_LIST_OFFSET(idx) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700118 (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700119#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700120 (IS_E1H_OFFSET ? (0x33a0 + (port * 0x1a0) + (client_id * 0x10)) \
121 : (0x9c0 + (port * 0x120) + (client_id * 0x10)))
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800122#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
Eilon Greensteinca003922009-08-12 22:53:28 -0700123 (IS_E1H_OFFSET ? 0x1ed8 : 0xffffffff)
124#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
125 (IS_E1H_OFFSET ? 0x1eda : 0xffffffff)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700126#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700127 (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
128 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
129 0x28) + (index * 0x4)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700130#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700131 (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
132 ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700133#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700134 (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
135 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700136#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700137 (IS_E1H_OFFSET ? (0x2940 + (function * 0x8)) : (0x4928 + \
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700138 (function * 0x8)))
139#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700140 (IS_E1H_OFFSET ? (0x3000 + (function * 0x40)) : (0x1500 + \
141 (function * 0x40)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700142#define TSTORM_FUNCTION_MODE_OFFSET \
Eilon Greensteinca003922009-08-12 22:53:28 -0700143 (IS_E1H_OFFSET ? 0x1ed0 : 0xffffffff)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700144#define TSTORM_HC_BTR_OFFSET(port) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700145 (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700146#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700147 (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700148 (function * 0x80)))
149#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
Eilon Greensteinca003922009-08-12 22:53:28 -0700150#define TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(function, pblEntry) \
151 (IS_E1H_OFFSET ? (0x60c0 + (function * 0x40) + (pblEntry * 0x8)) \
152 : (0x4c30 + (function * 0x40) + (pblEntry * 0x8)))
153#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
154 (IS_E1H_OFFSET ? (0x6340 + (function * 0x8)) : (0x4cd0 + \
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700155 (function * 0x8)))
Eilon Greensteinca003922009-08-12 22:53:28 -0700156#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
157 (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x4c04 + \
158 (function * 0x8)))
159#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
160 (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x4c02 + \
161 (function * 0x8)))
162#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
163 (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x4c00 + \
164 (function * 0x8)))
165#define TSTORM_ISCSI_RQ_SIZE_OFFSET(function) \
166 (IS_E1H_OFFSET ? (0x6080 + (function * 0x8)) : (0x4c20 + \
167 (function * 0x8)))
168#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
169 (IS_E1H_OFFSET ? (0x6040 + (function * 0x8)) : (0x4c10 + \
170 (function * 0x8)))
171#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(function) \
172 (IS_E1H_OFFSET ? (0x6042 + (function * 0x8)) : (0x4c12 + \
173 (function * 0x8)))
174#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(function) \
175 (IS_E1H_OFFSET ? (0x6044 + (function * 0x8)) : (0x4c14 + \
176 (function * 0x8)))
177#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
178 (IS_E1H_OFFSET ? (0x3008 + (function * 0x40)) : (0x1508 + \
179 (function * 0x40)))
180#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
181 (IS_E1H_OFFSET ? (0x2010 + (port * 0x490) + (stats_counter_id * \
182 0x40)) : (0x4010 + (port * 0x490) + (stats_counter_id * 0x40)))
183#define TSTORM_STATS_FLAGS_OFFSET(function) \
184 (IS_E1H_OFFSET ? (0x29c0 + (function * 0x8)) : (0x4948 + \
185 (function * 0x8)))
186#define TSTORM_TCP_MAX_CWND_OFFSET(function) \
187 (IS_E1H_OFFSET ? (0x4004 + (function * 0x8)) : (0x1fb4 + \
188 (function * 0x8)))
189#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa000 : 0x3000)
190#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2000 : 0x1000)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700191#define USTORM_ASSERT_LIST_INDEX_OFFSET \
Eilon Greensteinca003922009-08-12 22:53:28 -0700192 (IS_E1H_OFFSET ? 0x8000 : 0x1000)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700193#define USTORM_ASSERT_LIST_OFFSET(idx) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700194 (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700195#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700196 (IS_E1H_OFFSET ? (0x1010 + (port * 0x680) + (clientId * 0x40)) : \
197 (0x4010 + (port * 0x360) + (clientId * 0x30)))
198#define USTORM_CQE_PAGE_NEXT_OFFSET(port, clientId) \
199 (IS_E1H_OFFSET ? (0x1028 + (port * 0x680) + (clientId * 0x40)) : \
200 (0x4028 + (port * 0x360) + (clientId * 0x30)))
201#define USTORM_ETH_PAUSE_ENABLED_OFFSET(port) \
202 (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
Eilon Greenstein1c063282009-02-12 08:36:43 +0000203#define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700204 (IS_E1H_OFFSET ? (0x1030 + (port * 0x680) + (clientId * 0x40)) : \
Eilon Greenstein1c063282009-02-12 08:36:43 +0000205 0xffffffff)
Eilon Greensteinde832a52009-02-12 08:36:33 +0000206#define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700207 (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1dd0 + \
Eilon Greensteinde832a52009-02-12 08:36:33 +0000208 (function * 0x8)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700209#define USTORM_FUNCTION_MODE_OFFSET \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700210 (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
Eilon Greensteinca003922009-08-12 22:53:28 -0700211#define USTORM_ISCSI_CQ_SIZE_OFFSET(function) \
212 (IS_E1H_OFFSET ? (0x7044 + (function * 0x8)) : (0x2414 + \
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700213 (function * 0x8)))
Eilon Greensteinca003922009-08-12 22:53:28 -0700214#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
215 (IS_E1H_OFFSET ? (0x7046 + (function * 0x8)) : (0x2416 + \
216 (function * 0x8)))
217#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
218 (IS_E1H_OFFSET ? (0x7688 + (function * 0x8)) : (0x29c8 + \
219 (function * 0x8)))
220#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(function) \
221 (IS_E1H_OFFSET ? (0x7648 + (function * 0x8)) : (0x29b8 + \
222 (function * 0x8)))
223#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
224 (IS_E1H_OFFSET ? (0x7004 + (function * 0x8)) : (0x2404 + \
225 (function * 0x8)))
226#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
227 (IS_E1H_OFFSET ? (0x7002 + (function * 0x8)) : (0x2402 + \
228 (function * 0x8)))
229#define USTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
230 (IS_E1H_OFFSET ? (0x7000 + (function * 0x8)) : (0x2400 + \
231 (function * 0x8)))
232#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
233 (IS_E1H_OFFSET ? (0x7040 + (function * 0x8)) : (0x2410 + \
234 (function * 0x8)))
235#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(function) \
236 (IS_E1H_OFFSET ? (0x7080 + (function * 0x8)) : (0x2420 + \
237 (function * 0x8)))
238#define USTORM_ISCSI_RQ_SIZE_OFFSET(function) \
239 (IS_E1H_OFFSET ? (0x7084 + (function * 0x8)) : (0x2424 + \
240 (function * 0x8)))
241#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
242 (IS_E1H_OFFSET ? (0x1018 + (port * 0x680) + (clientId * 0x40)) : \
243 (0x4018 + (port * 0x360) + (clientId * 0x30)))
244#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
245 (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x1da8 + \
246 (function * 0x8)))
Eilon Greensteinde832a52009-02-12 08:36:33 +0000247#define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
248 (IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \
Eilon Greensteinca003922009-08-12 22:53:28 -0700249 0x28)) : (0x1500 + (port * 0x2d0) + (stats_counter_id * 0x28)))
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800250#define USTORM_RX_PRODS_OFFSET(port, client_id) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700251 (IS_E1H_OFFSET ? (0x1000 + (port * 0x680) + (client_id * 0x40)) \
252 : (0x4000 + (port * 0x360) + (client_id * 0x30)))
Eilon Greensteinde832a52009-02-12 08:36:33 +0000253#define USTORM_STATS_FLAGS_OFFSET(function) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700254 (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1db8 + \
Eilon Greensteinde832a52009-02-12 08:36:33 +0000255 (function * 0x8)))
Eilon Greensteinca003922009-08-12 22:53:28 -0700256#define USTORM_TPA_BTR_OFFSET (IS_E1H_OFFSET ? 0x3da5 : 0x5095)
257#define USTORM_TPA_BTR_SIZE 0x1
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700258#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700259 (IS_E1H_OFFSET ? 0x9000 : 0x1000)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700260#define XSTORM_ASSERT_LIST_OFFSET(idx) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700261 (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700262#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700263 (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3a80 + (port * 0x50)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700264#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700265 (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
266 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
267 0x28) + (index * 0x4)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700268#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700269 (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
270 ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700271#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700272 (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
273 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700274#define XSTORM_E1HOV_OFFSET(function) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700275 (IS_E1H_OFFSET ? (0x2c10 + (function * 0x8)) : 0xffffffff)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700276#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700277 (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3a50 + \
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700278 (function * 0x8)))
279#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700280 (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3b60 + \
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800281 (function * 0x90)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700282#define XSTORM_FUNCTION_MODE_OFFSET \
Eilon Greensteinca003922009-08-12 22:53:28 -0700283 (IS_E1H_OFFSET ? 0x2c50 : 0xffffffff)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700284#define XSTORM_HC_BTR_OFFSET(port) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700285 (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
Eilon Greensteinca003922009-08-12 22:53:28 -0700286#define XSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
287 (IS_E1H_OFFSET ? (0x80c0 + (function * 0x8)) : (0x1c30 + \
288 (function * 0x8)))
289#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(function) \
290 (IS_E1H_OFFSET ? (0x8080 + (function * 0x8)) : (0x1c20 + \
291 (function * 0x8)))
292#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(function) \
293 (IS_E1H_OFFSET ? (0x8081 + (function * 0x8)) : (0x1c21 + \
294 (function * 0x8)))
295#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(function) \
296 (IS_E1H_OFFSET ? (0x8082 + (function * 0x8)) : (0x1c22 + \
297 (function * 0x8)))
298#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(function) \
299 (IS_E1H_OFFSET ? (0x8083 + (function * 0x8)) : (0x1c23 + \
300 (function * 0x8)))
301#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(function) \
302 (IS_E1H_OFFSET ? (0x8084 + (function * 0x8)) : (0x1c24 + \
303 (function * 0x8)))
304#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(function) \
305 (IS_E1H_OFFSET ? (0x8085 + (function * 0x8)) : (0x1c25 + \
306 (function * 0x8)))
307#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(function) \
308 (IS_E1H_OFFSET ? (0x8086 + (function * 0x8)) : (0x1c26 + \
309 (function * 0x8)))
310#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
311 (IS_E1H_OFFSET ? (0x8004 + (function * 0x8)) : (0x1c04 + \
312 (function * 0x8)))
313#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
314 (IS_E1H_OFFSET ? (0x8002 + (function * 0x8)) : (0x1c02 + \
315 (function * 0x8)))
316#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
317 (IS_E1H_OFFSET ? (0x8000 + (function * 0x8)) : (0x1c00 + \
318 (function * 0x8)))
319#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
320 (IS_E1H_OFFSET ? (0x80c4 + (function * 0x8)) : (0x1c34 + \
321 (function * 0x8)))
322#define XSTORM_ISCSI_SQ_SIZE_OFFSET(function) \
323 (IS_E1H_OFFSET ? (0x80c2 + (function * 0x8)) : (0x1c32 + \
324 (function * 0x8)))
325#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(function) \
326 (IS_E1H_OFFSET ? (0x8043 + (function * 0x8)) : (0x1c13 + \
327 (function * 0x8)))
328#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
329 (IS_E1H_OFFSET ? (0x8042 + (function * 0x8)) : (0x1c12 + \
330 (function * 0x8)))
331#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(function) \
332 (IS_E1H_OFFSET ? (0x8041 + (function * 0x8)) : (0x1c11 + \
333 (function * 0x8)))
334#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(function) \
335 (IS_E1H_OFFSET ? (0x8040 + (function * 0x8)) : (0x1c10 + \
336 (function * 0x8)))
Yitchak Gertner66e855f2008-08-13 15:49:05 -0700337#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700338 (IS_E1H_OFFSET ? (0xc000 + (port * 0x360) + (stats_counter_id * \
339 0x30)) : (0x3378 + (port * 0x360) + (stats_counter_id * 0x30)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700340#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700341 (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3b20 + \
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800342 (function * 0x90)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700343#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700344 (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700345 (function * 0x10)))
346#define XSTORM_SPQ_PROD_OFFSET(function) \
Eilon Greenstein6378c022008-08-13 15:59:25 -0700347 (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700348 (function * 0x10)))
349#define XSTORM_STATS_FLAGS_OFFSET(function) \
Eilon Greensteinca003922009-08-12 22:53:28 -0700350 (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3a40 + \
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700351 (function * 0x8)))
Eilon Greensteinca003922009-08-12 22:53:28 -0700352#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port) \
353 (IS_E1H_OFFSET ? (0x4000 + (port * 0x8)) : (0x1960 + (port * 0x8)))
354#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port) \
355 (IS_E1H_OFFSET ? (0x4001 + (port * 0x8)) : (0x1961 + (port * 0x8)))
356#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(function) \
357 (IS_E1H_OFFSET ? (0x4060 + ((function>>1) * 0x8) + ((function&1) \
358 * 0x4)) : (0x1978 + (function * 0x4)))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200359#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
360
361/**
Eilon Greensteinf5372252009-02-12 08:38:30 +0000362* This file defines HSI constants for the ETH flow
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200363*/
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700364#ifdef _EVEREST_MICROCODE
365#include "microcode_constants.h"
366#include "eth_rx_bd.h"
367#include "eth_tx_bd.h"
368#include "eth_rx_cqe.h"
369#include "eth_rx_sge.h"
370#include "eth_rx_cqe_next_page.h"
371#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200372
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700373/* RSS hash types */
374#define DEFAULT_HASH_TYPE 0
375#define IPV4_HASH_TYPE 1
376#define TCP_IPV4_HASH_TYPE 2
377#define IPV6_HASH_TYPE 3
378#define TCP_IPV6_HASH_TYPE 4
Eilon Greensteinca003922009-08-12 22:53:28 -0700379#define VLAN_PRI_HASH_TYPE 5
380#define E1HOV_PRI_HASH_TYPE 6
381#define DSCP_HASH_TYPE 7
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700382
Eilon Greensteinf5372252009-02-12 08:38:30 +0000383
384/* Ethernet Ring parameters */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700385#define X_ETH_LOCAL_RING_SIZE 13
386#define FIRST_BD_IN_PKT 0
387#define PARSE_BD_INDEX 1
Eilon Greenstein356e2382009-02-12 08:38:32 +0000388#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
Eilon Greensteinca003922009-08-12 22:53:28 -0700389#define U_ETH_NUM_OF_SGES_TO_FETCH 8
390#define U_ETH_MAX_SGES_FOR_PACKET 3
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700391
392/* Rx ring params */
Eilon Greensteinca003922009-08-12 22:53:28 -0700393#define U_ETH_LOCAL_BD_RING_SIZE 8
394#define U_ETH_LOCAL_SGE_RING_SIZE 10
Eilon Greenstein356e2382009-02-12 08:38:32 +0000395#define U_ETH_SGL_SIZE 8
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700396
397
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700398#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
399 (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
400
Eilon Greensteinca003922009-08-12 22:53:28 -0700401#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700402#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
403#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
404
Eilon Greensteinca003922009-08-12 22:53:28 -0700405#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
406#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
407#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
408
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700409#define U_ETH_UNDEFINED_Q 0xFF
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200410
411/* values of command IDs in the ramrod message */
Eilon Greenstein356e2382009-02-12 08:38:32 +0000412#define RAMROD_CMD_ID_ETH_PORT_SETUP 80
413#define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85
414#define RAMROD_CMD_ID_ETH_STAT_QUERY 90
415#define RAMROD_CMD_ID_ETH_UPDATE 100
416#define RAMROD_CMD_ID_ETH_HALT 105
417#define RAMROD_CMD_ID_ETH_SET_MAC 110
418#define RAMROD_CMD_ID_ETH_CFC_DEL 115
419#define RAMROD_CMD_ID_ETH_PORT_DEL 120
420#define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200421
422
423/* command values for set mac command */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700424#define T_ETH_MAC_COMMAND_SET 0
425#define T_ETH_MAC_COMMAND_INVALIDATE 1
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200426
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700427#define T_ETH_INDIRECTION_TABLE_SIZE 128
428
429/*The CRC32 seed, that is used for the hash(reduction) multicast address */
430#define T_ETH_CRC32_HASH_SEED 0x00000000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200431
432/* Maximal L2 clients supported */
Eilon Greensteinca003922009-08-12 22:53:28 -0700433#define ETH_MAX_RX_CLIENTS_E1 18
434#define ETH_MAX_RX_CLIENTS_E1H 26
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700435
436/* Maximal aggregation queues supported */
Eilon Greenstein356e2382009-02-12 08:38:32 +0000437#define ETH_MAX_AGGREGATION_QUEUES_E1 32
438#define ETH_MAX_AGGREGATION_QUEUES_E1H 64
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700439
Eilon Greenstein555f6c72009-02-12 08:36:11 +0000440/* ETH RSS modes */
441#define ETH_RSS_MODE_DISABLED 0
442#define ETH_RSS_MODE_REGULAR 1
Eilon Greensteinca003922009-08-12 22:53:28 -0700443#define ETH_RSS_MODE_VLAN_PRI 2
444#define ETH_RSS_MODE_E1HOV_PRI 3
445#define ETH_RSS_MODE_IP_DSCP 4
Eilon Greenstein555f6c72009-02-12 08:36:11 +0000446
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200447
448/**
Eilon Greensteinf5372252009-02-12 08:38:30 +0000449* This file defines HSI constants common to all microcode flows
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200450*/
451
452/* Connection types */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700453#define ETH_CONNECTION_TYPE 0
454#define TOE_CONNECTION_TYPE 1
455#define RDMA_CONNECTION_TYPE 2
456#define ISCSI_CONNECTION_TYPE 3
457#define FCOE_CONNECTION_TYPE 4
458#define RESERVED_CONNECTION_TYPE_0 5
459#define RESERVED_CONNECTION_TYPE_1 6
460#define RESERVED_CONNECTION_TYPE_2 7
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200461
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200462
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700463#define PROTOCOL_STATE_BIT_OFFSET 6
464
465#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
466#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
467#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200468
469/* microcode fixed page page size 4K (chains and ring segments) */
Eilon Greenstein356e2382009-02-12 08:38:32 +0000470#define MC_PAGE_SIZE 4096
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700471
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200472
473/* Host coalescing constants */
474
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200475/* index numbers */
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800476#define HC_USTORM_DEF_SB_NUM_INDICES 8
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700477#define HC_CSTORM_DEF_SB_NUM_INDICES 8
478#define HC_XSTORM_DEF_SB_NUM_INDICES 4
479#define HC_TSTORM_DEF_SB_NUM_INDICES 4
480#define HC_USTORM_SB_NUM_INDICES 4
481#define HC_CSTORM_SB_NUM_INDICES 4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200482
Eilon Greensteinf5372252009-02-12 08:38:30 +0000483/* index values - which counter to update */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200484
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700485#define HC_INDEX_U_TOE_RX_CQ_CONS 0
486#define HC_INDEX_U_ETH_RX_CQ_CONS 1
487#define HC_INDEX_U_ETH_RX_BD_CONS 2
488#define HC_INDEX_U_FCOE_EQ_CONS 3
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200489
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700490#define HC_INDEX_C_TOE_TX_CQ_CONS 0
491#define HC_INDEX_C_ETH_TX_CQ_CONS 1
492#define HC_INDEX_C_ISCSI_EQ_CONS 2
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200493
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700494#define HC_INDEX_DEF_X_SPQ_CONS 0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200495
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700496#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
497#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
498#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
499#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
500#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
501#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
Eilon Greensteinca003922009-08-12 22:53:28 -0700502#define HC_INDEX_DEF_C_ETH_FCOE_CQ_CONS 6
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700503
504#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
505#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
506#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
507#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
Eilon Greensteinca003922009-08-12 22:53:28 -0700508#define HC_INDEX_DEF_U_ETH_FCOE_RX_CQ_CONS 4
509#define HC_INDEX_DEF_U_ETH_FCOE_RX_BD_CONS 5
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200510
511/* used by the driver to get the SB offset */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700512#define USTORM_ID 0
513#define CSTORM_ID 1
514#define XSTORM_ID 2
515#define TSTORM_ID 3
516#define ATTENTION_ID 4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200517
518/* max number of slow path commands per port */
Eilon Greenstein356e2382009-02-12 08:38:32 +0000519#define MAX_RAMRODS_PER_PORT 8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200520
521/* values for RX ETH CQE type field */
Eilon Greenstein356e2382009-02-12 08:38:32 +0000522#define RX_ETH_CQE_TYPE_ETH_FASTPATH 0
523#define RX_ETH_CQE_TYPE_ETH_RAMROD 1
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200524
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200525
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700526/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
Eilon Greenstein356e2382009-02-12 08:38:32 +0000527#define EMULATION_FREQUENCY_FACTOR 1600
528#define FPGA_FREQUENCY_FACTOR 100
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700529
530#define TIMERS_TICK_SIZE_CHIP (1e-3)
531#define TIMERS_TICK_SIZE_EMUL \
532 ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
533#define TIMERS_TICK_SIZE_FPGA \
534 ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
535
536#define TSEMI_CLK1_RESUL_CHIP (1e-3)
537#define TSEMI_CLK1_RESUL_EMUL \
538 ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
539#define TSEMI_CLK1_RESUL_FPGA \
540 ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
541
Eilon Greenstein356e2382009-02-12 08:38:32 +0000542#define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP)
543#define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL)
544#define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700545
546#define XSEMI_CLK1_RESUL_CHIP (1e-3)
547#define XSEMI_CLK1_RESUL_EMUL \
548 ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
549#define XSEMI_CLK1_RESUL_FPGA \
550 ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
551
552#define XSEMI_CLK2_RESUL_CHIP (1e-6)
553#define XSEMI_CLK2_RESUL_EMUL \
554 ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
555#define XSEMI_CLK2_RESUL_FPGA \
556 ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
557
558#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
559#define SDM_TIMER_TICK_RESUL_EMUL \
560 ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
561#define SDM_TIMER_TICK_RESUL_FPGA \
562 ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
563
564
565/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200566#define XSTORM_IP_ID_ROLL_HALF 0x8000
567#define XSTORM_IP_ID_ROLL_ALL 0
568
Eilon Greenstein356e2382009-02-12 08:38:32 +0000569#define FW_LOG_LIST_SIZE 50
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200570
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700571#define NUM_OF_PROTOCOLS 4
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800572#define NUM_OF_SAFC_BITS 16
573#define MAX_COS_NUMBER 4
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700574#define MAX_T_STAT_COUNTER_ID 18
575#define MAX_X_STAT_COUNTER_ID 18
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800576#define MAX_U_STAT_COUNTER_ID 18
577
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200578
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700579#define UNKNOWN_ADDRESS 0
580#define UNICAST_ADDRESS 1
581#define MULTICAST_ADDRESS 2
582#define BROADCAST_ADDRESS 3
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200583
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700584#define SINGLE_FUNCTION 0
585#define MULTI_FUNCTION 1
586
587#define IP_V4 0
588#define IP_V6 1
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200589