blob: 601b88c490cfe2f20a9bbce4f2a1ab65fb4cd9c8 [file] [log] [blame]
Jesper Nilsson035e1112007-11-29 17:11:23 +01001#include <linux/init.h>
2#include <linux/module.h>
3#include <linux/cpufreq.h>
4#include <hwregs/reg_map.h>
5#include <hwregs/reg_rdwr.h>
6#include <hwregs/clkgen_defs.h>
7#include <hwregs/ddr2_defs.h>
8
9static int
10cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
11 void *data);
12
13static struct notifier_block cris_sdram_freq_notifier_block = {
14 .notifier_call = cris_sdram_freq_notifier
15};
16
17static struct cpufreq_frequency_table cris_freq_table[] = {
Viresh Kumar7f4b0462014-03-28 19:11:47 +053018 {0, 0x01, 6000},
19 {0, 0x02, 200000},
20 {0, 0, CPUFREQ_TABLE_END},
Jesper Nilsson035e1112007-11-29 17:11:23 +010021};
22
23static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
24{
25 reg_clkgen_rw_clk_ctrl clk_ctrl;
26 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
27 return clk_ctrl.pll ? 200000 : 6000;
28}
29
Viresh Kumar9c0ebcf2013-10-25 19:45:48 +053030static int cris_freq_target(struct cpufreq_policy *policy, unsigned int state)
Jesper Nilsson035e1112007-11-29 17:11:23 +010031{
Jesper Nilsson035e1112007-11-29 17:11:23 +010032 reg_clkgen_rw_clk_ctrl clk_ctrl;
33 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
34
Jesper Nilsson035e1112007-11-29 17:11:23 +010035 local_irq_disable();
36
37 /* Even though we may be SMP they will share the same clock
38 * so all settings are made on CPU0. */
39 if (cris_freq_table[state].frequency == 200000)
40 clk_ctrl.pll = 1;
41 else
42 clk_ctrl.pll = 0;
43 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
44
45 local_irq_enable();
46
Jesper Nilsson035e1112007-11-29 17:11:23 +010047 return 0;
48}
49
50static int cris_freq_cpu_init(struct cpufreq_policy *policy)
51{
Viresh Kumar1870e112013-10-03 20:29:10 +053052 return cpufreq_generic_init(policy, cris_freq_table, 1000000);
Jesper Nilsson035e1112007-11-29 17:11:23 +010053}
54
Jesper Nilsson035e1112007-11-29 17:11:23 +010055static struct cpufreq_driver cris_freq_driver = {
56 .get = cris_freq_get_cpu_frequency,
Viresh Kumar361db102013-10-03 20:28:01 +053057 .verify = cpufreq_generic_frequency_table_verify,
Viresh Kumar9c0ebcf2013-10-25 19:45:48 +053058 .target_index = cris_freq_target,
Jesper Nilsson035e1112007-11-29 17:11:23 +010059 .init = cris_freq_cpu_init,
Jesper Nilsson035e1112007-11-29 17:11:23 +010060 .name = "cris_freq",
Viresh Kumar361db102013-10-03 20:28:01 +053061 .attr = cpufreq_generic_attr,
Jesper Nilsson035e1112007-11-29 17:11:23 +010062};
63
64static int __init cris_freq_init(void)
65{
66 int ret;
67 ret = cpufreq_register_driver(&cris_freq_driver);
68 cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
69 CPUFREQ_TRANSITION_NOTIFIER);
70 return ret;
71}
72
73static int
74cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
75 void *data)
76{
77 int i;
78 struct cpufreq_freqs *freqs = data;
79 if (val == CPUFREQ_PRECHANGE) {
80 reg_ddr2_rw_cfg cfg =
81 REG_RD(ddr2, regi_ddr2_ctrl, rw_cfg);
82 cfg.ref_interval = (freqs->new == 200000 ? 1560 : 46);
83
84 if (freqs->new == 200000)
85 for (i = 0; i < 50000; i++);
86 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
87 }
88 return 0;
89}
90
91
92module_init(cris_freq_init);