Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) ST-Ericsson SA 2011 |
| 3 | * |
| 4 | * License Terms: GNU General Public License v2 |
| 5 | * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson |
| 6 | * Author: Sundar Iyer for ST-Ericsson |
| 7 | * sched_clock implementation is based on: |
| 8 | * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com> |
| 9 | * |
| 10 | * DBx500-PRCMU Timer |
| 11 | * The PRCMU has 5 timers which are available in a always-on |
| 12 | * power domain. We use the Timer 4 for our always-on clock |
Fabio Baltieri | 807eba5 | 2013-01-21 13:09:32 +0100 | [diff] [blame] | 13 | * source on DB8500. |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 14 | */ |
Linus Walleij | 9d2aa8c | 2015-12-01 15:00:24 +0100 | [diff] [blame] | 15 | #include <linux/of.h> |
| 16 | #include <linux/of_address.h> |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 17 | #include <linux/clockchips.h> |
Stephen Boyd | 38ff87f | 2013-06-01 23:39:40 -0700 | [diff] [blame] | 18 | #include <linux/sched_clock.h> |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 19 | |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 20 | #define RATE_32K 32768 |
| 21 | |
| 22 | #define TIMER_MODE_CONTINOUS 0x1 |
| 23 | #define TIMER_DOWNCOUNT_VAL 0xffffffff |
| 24 | |
| 25 | #define PRCMU_TIMER_REF 0 |
| 26 | #define PRCMU_TIMER_DOWNCOUNT 0x4 |
| 27 | #define PRCMU_TIMER_MODE 0x8 |
| 28 | |
| 29 | #define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */ |
| 30 | |
Linus Walleij | b1e3be06 | 2011-10-03 09:30:20 +0200 | [diff] [blame] | 31 | static void __iomem *clksrc_dbx500_timer_base; |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 32 | |
Rabin Vincent | 5302822 | 2013-01-21 13:09:31 +0100 | [diff] [blame] | 33 | static cycle_t notrace clksrc_dbx500_prcmu_read(struct clocksource *cs) |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 34 | { |
Rabin Vincent | 5302822 | 2013-01-21 13:09:31 +0100 | [diff] [blame] | 35 | void __iomem *base = clksrc_dbx500_timer_base; |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 36 | u32 count, count2; |
| 37 | |
| 38 | do { |
Rabin Vincent | 5302822 | 2013-01-21 13:09:31 +0100 | [diff] [blame] | 39 | count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); |
| 40 | count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 41 | } while (count2 != count); |
| 42 | |
| 43 | /* Negate because the timer is a decrementing counter */ |
| 44 | return ~count; |
| 45 | } |
| 46 | |
| 47 | static struct clocksource clocksource_dbx500_prcmu = { |
| 48 | .name = "dbx500-prcmu-timer", |
| 49 | .rating = 300, |
| 50 | .read = clksrc_dbx500_prcmu_read, |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 51 | .mask = CLOCKSOURCE_MASK(32), |
| 52 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 53 | }; |
| 54 | |
| 55 | #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 56 | |
Stephen Boyd | 5602d7c | 2013-07-18 16:21:21 -0700 | [diff] [blame] | 57 | static u64 notrace dbx500_prcmu_sched_clock_read(void) |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 58 | { |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 59 | if (unlikely(!clksrc_dbx500_timer_base)) |
| 60 | return 0; |
| 61 | |
Linus Walleij | cfef032 | 2012-01-02 14:50:15 +0100 | [diff] [blame] | 62 | return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu); |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 63 | } |
| 64 | |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 65 | #endif |
| 66 | |
Linus Walleij | 9d2aa8c | 2015-12-01 15:00:24 +0100 | [diff] [blame] | 67 | static void __init clksrc_dbx500_prcmu_init(struct device_node *node) |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 68 | { |
Linus Walleij | 9d2aa8c | 2015-12-01 15:00:24 +0100 | [diff] [blame] | 69 | clksrc_dbx500_timer_base = of_iomap(node, 0); |
Linus Walleij | b1e3be06 | 2011-10-03 09:30:20 +0200 | [diff] [blame] | 70 | |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 71 | /* |
| 72 | * The A9 sub system expects the timer to be configured as |
| 73 | * a continous looping timer. |
| 74 | * The PRCMU should configure it but if it for some reason |
| 75 | * don't we do it here. |
| 76 | */ |
| 77 | if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) != |
| 78 | TIMER_MODE_CONTINOUS) { |
| 79 | writel(TIMER_MODE_CONTINOUS, |
| 80 | clksrc_dbx500_timer_base + PRCMU_TIMER_MODE); |
| 81 | writel(TIMER_DOWNCOUNT_VAL, |
| 82 | clksrc_dbx500_timer_base + PRCMU_TIMER_REF); |
| 83 | } |
| 84 | #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK |
Stephen Boyd | 5602d7c | 2013-07-18 16:21:21 -0700 | [diff] [blame] | 85 | sched_clock_register(dbx500_prcmu_sched_clock_read, 32, RATE_32K); |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 86 | #endif |
Yong Zhang | 13f0f03 | 2011-12-01 15:20:15 +0800 | [diff] [blame] | 87 | clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K); |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 88 | } |
Linus Walleij | 9d2aa8c | 2015-12-01 15:00:24 +0100 | [diff] [blame] | 89 | CLOCKSOURCE_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4", |
| 90 | clksrc_dbx500_prcmu_init); |