Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1 | /** |
| 2 | * core.h - DesignWare USB3 DRD Core Header |
| 3 | * |
| 4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 5 | * |
| 6 | * Authors: Felipe Balbi <balbi@ti.com>, |
| 7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> |
| 8 | * |
Felipe Balbi | 5945f78 | 2013-06-30 14:15:11 +0300 | [diff] [blame] | 9 | * This program is free software: you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 of |
| 11 | * the License as published by the Free Software Foundation. |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 12 | * |
Felipe Balbi | 5945f78 | 2013-06-30 14:15:11 +0300 | [diff] [blame] | 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #ifndef __DRIVERS_USB_DWC3_CORE_H |
| 20 | #define __DRIVERS_USB_DWC3_CORE_H |
| 21 | |
| 22 | #include <linux/device.h> |
| 23 | #include <linux/spinlock.h> |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 24 | #include <linux/ioport.h> |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 25 | #include <linux/list.h> |
| 26 | #include <linux/dma-mapping.h> |
| 27 | #include <linux/mm.h> |
| 28 | #include <linux/debugfs.h> |
| 29 | |
| 30 | #include <linux/usb/ch9.h> |
| 31 | #include <linux/usb/gadget.h> |
Ruchika Kharwar | a45c82b8 | 2013-07-06 07:52:49 -0500 | [diff] [blame] | 32 | #include <linux/usb/otg.h> |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 33 | |
Kishon Vijay Abraham I | 5730348 | 2014-03-03 17:08:11 +0530 | [diff] [blame] | 34 | #include <linux/phy/phy.h> |
| 35 | |
Felipe Balbi | 2c4cbe6e5 | 2014-04-30 17:45:10 -0500 | [diff] [blame] | 36 | #define DWC3_MSG_MAX 500 |
| 37 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 38 | /* Global constants */ |
Felipe Balbi | 3ef35fa | 2012-05-04 12:58:14 +0300 | [diff] [blame] | 39 | #define DWC3_EP0_BOUNCE_SIZE 512 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 40 | #define DWC3_ENDPOINTS_NUM 32 |
Ido Shayevitz | 51249dc | 2012-04-24 14:18:39 +0300 | [diff] [blame] | 41 | #define DWC3_XHCI_RESOURCES_NUM 2 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 42 | |
Felipe Balbi | 0ffcaf3 | 2013-12-19 13:04:28 -0600 | [diff] [blame] | 43 | #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ |
Felipe Balbi | 5da9347 | 2012-12-07 21:42:03 +0200 | [diff] [blame] | 44 | #define DWC3_EVENT_SIZE 4 /* bytes */ |
| 45 | #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ |
| 46 | #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 47 | #define DWC3_EVENT_TYPE_MASK 0xfe |
| 48 | |
| 49 | #define DWC3_EVENT_TYPE_DEV 0 |
| 50 | #define DWC3_EVENT_TYPE_CARKIT 3 |
| 51 | #define DWC3_EVENT_TYPE_I2C 4 |
| 52 | |
| 53 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 |
| 54 | #define DWC3_DEVICE_EVENT_RESET 1 |
| 55 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 |
| 56 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 |
| 57 | #define DWC3_DEVICE_EVENT_WAKEUP 4 |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 58 | #define DWC3_DEVICE_EVENT_HIBER_REQ 5 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 59 | #define DWC3_DEVICE_EVENT_EOPF 6 |
| 60 | #define DWC3_DEVICE_EVENT_SOF 7 |
| 61 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 |
| 62 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 |
| 63 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 |
| 64 | |
| 65 | #define DWC3_GEVNTCOUNT_MASK 0xfffc |
| 66 | #define DWC3_GSNPSID_MASK 0xffff0000 |
| 67 | #define DWC3_GSNPSREV_MASK 0xffff |
| 68 | |
Ido Shayevitz | 51249dc | 2012-04-24 14:18:39 +0300 | [diff] [blame] | 69 | /* DWC3 registers memory space boundries */ |
| 70 | #define DWC3_XHCI_REGS_START 0x0 |
| 71 | #define DWC3_XHCI_REGS_END 0x7fff |
| 72 | #define DWC3_GLOBALS_REGS_START 0xc100 |
| 73 | #define DWC3_GLOBALS_REGS_END 0xc6ff |
| 74 | #define DWC3_DEVICE_REGS_START 0xc700 |
| 75 | #define DWC3_DEVICE_REGS_END 0xcbff |
| 76 | #define DWC3_OTG_REGS_START 0xcc00 |
| 77 | #define DWC3_OTG_REGS_END 0xccff |
| 78 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 79 | /* Global Registers */ |
| 80 | #define DWC3_GSBUSCFG0 0xc100 |
| 81 | #define DWC3_GSBUSCFG1 0xc104 |
| 82 | #define DWC3_GTXTHRCFG 0xc108 |
| 83 | #define DWC3_GRXTHRCFG 0xc10c |
| 84 | #define DWC3_GCTL 0xc110 |
| 85 | #define DWC3_GEVTEN 0xc114 |
| 86 | #define DWC3_GSTS 0xc118 |
| 87 | #define DWC3_GSNPSID 0xc120 |
| 88 | #define DWC3_GGPIO 0xc124 |
| 89 | #define DWC3_GUID 0xc128 |
| 90 | #define DWC3_GUCTL 0xc12c |
| 91 | #define DWC3_GBUSERRADDR0 0xc130 |
| 92 | #define DWC3_GBUSERRADDR1 0xc134 |
| 93 | #define DWC3_GPRTBIMAP0 0xc138 |
| 94 | #define DWC3_GPRTBIMAP1 0xc13c |
| 95 | #define DWC3_GHWPARAMS0 0xc140 |
| 96 | #define DWC3_GHWPARAMS1 0xc144 |
| 97 | #define DWC3_GHWPARAMS2 0xc148 |
| 98 | #define DWC3_GHWPARAMS3 0xc14c |
| 99 | #define DWC3_GHWPARAMS4 0xc150 |
| 100 | #define DWC3_GHWPARAMS5 0xc154 |
| 101 | #define DWC3_GHWPARAMS6 0xc158 |
| 102 | #define DWC3_GHWPARAMS7 0xc15c |
| 103 | #define DWC3_GDBGFIFOSPACE 0xc160 |
| 104 | #define DWC3_GDBGLTSSM 0xc164 |
| 105 | #define DWC3_GPRTBIMAP_HS0 0xc180 |
| 106 | #define DWC3_GPRTBIMAP_HS1 0xc184 |
| 107 | #define DWC3_GPRTBIMAP_FS0 0xc188 |
| 108 | #define DWC3_GPRTBIMAP_FS1 0xc18c |
| 109 | |
| 110 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) |
| 111 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) |
| 112 | |
| 113 | #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) |
| 114 | |
| 115 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) |
| 116 | |
| 117 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) |
| 118 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) |
| 119 | |
| 120 | #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) |
| 121 | #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) |
| 122 | #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) |
| 123 | #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) |
| 124 | |
| 125 | #define DWC3_GHWPARAMS8 0xc600 |
| 126 | |
| 127 | /* Device Registers */ |
| 128 | #define DWC3_DCFG 0xc700 |
| 129 | #define DWC3_DCTL 0xc704 |
| 130 | #define DWC3_DEVTEN 0xc708 |
| 131 | #define DWC3_DSTS 0xc70c |
| 132 | #define DWC3_DGCMDPAR 0xc710 |
| 133 | #define DWC3_DGCMD 0xc714 |
| 134 | #define DWC3_DALEPENA 0xc720 |
| 135 | #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) |
| 136 | #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) |
| 137 | #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) |
| 138 | #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) |
| 139 | |
| 140 | /* OTG Registers */ |
| 141 | #define DWC3_OCFG 0xcc00 |
| 142 | #define DWC3_OCTL 0xcc04 |
George Cherian | d4436c3 | 2013-03-14 16:05:24 +0530 | [diff] [blame] | 143 | #define DWC3_OEVT 0xcc08 |
| 144 | #define DWC3_OEVTEN 0xcc0C |
| 145 | #define DWC3_OSTS 0xcc10 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 146 | |
| 147 | /* Bit fields */ |
| 148 | |
| 149 | /* Global Configuration Register */ |
Paul Zimmerman | 1d04679 | 2012-02-15 18:56:56 -0800 | [diff] [blame] | 150 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) |
Felipe Balbi | f4aadbe | 2011-09-08 17:39:59 +0300 | [diff] [blame] | 151 | #define DWC3_GCTL_U2RSTECN (1 << 16) |
Paul Zimmerman | 1d04679 | 2012-02-15 18:56:56 -0800 | [diff] [blame] | 152 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 153 | #define DWC3_GCTL_CLK_BUS (0) |
| 154 | #define DWC3_GCTL_CLK_PIPE (1) |
| 155 | #define DWC3_GCTL_CLK_PIPEHALF (2) |
| 156 | #define DWC3_GCTL_CLK_MASK (3) |
| 157 | |
Felipe Balbi | 0b9fe32 | 2011-10-17 08:50:39 +0300 | [diff] [blame] | 158 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
Paul Zimmerman | 1d04679 | 2012-02-15 18:56:56 -0800 | [diff] [blame] | 159 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 160 | #define DWC3_GCTL_PRTCAP_HOST 1 |
| 161 | #define DWC3_GCTL_PRTCAP_DEVICE 2 |
| 162 | #define DWC3_GCTL_PRTCAP_OTG 3 |
| 163 | |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 164 | #define DWC3_GCTL_CORESOFTRESET (1 << 11) |
Felipe Balbi | 183ca11 | 2014-02-25 14:08:51 -0600 | [diff] [blame] | 165 | #define DWC3_GCTL_SOFITPSYNC (1 << 10) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 166 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
| 167 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) |
| 168 | #define DWC3_GCTL_DISSCRAMBLE (1 << 3) |
Huang Rui | 9a5b2f3 | 2014-10-28 19:54:27 +0800 | [diff] [blame] | 169 | #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 170 | #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) |
| 171 | #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 172 | |
| 173 | /* Global USB2 PHY Configuration Register */ |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 174 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) |
| 175 | #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 176 | |
| 177 | /* Global USB3 PIPE Control Register */ |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 178 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) |
Huang Rui | b5a65c4 | 2014-10-28 19:54:28 +0800 | [diff] [blame] | 179 | #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) |
Huang Rui | df31f5b | 2014-10-28 19:54:29 +0800 | [diff] [blame] | 180 | #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) |
Huang Rui | a2a1d0f | 2014-10-28 19:54:30 +0800 | [diff] [blame] | 181 | #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) |
| 182 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) |
| 183 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) |
Huang Rui | 41c06ff | 2014-10-28 19:54:31 +0800 | [diff] [blame] | 184 | #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 185 | #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) |
Huang Rui | fb67afc | 2014-10-28 19:54:32 +0800 | [diff] [blame] | 186 | #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) |
Huang Rui | 14f4ac5 | 2014-10-28 19:54:33 +0800 | [diff] [blame] | 187 | #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) |
Huang Rui | 6b6a0c9 | 2014-10-31 11:11:12 +0800 | [diff] [blame] | 188 | #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) |
| 189 | #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 190 | |
Felipe Balbi | 457e84b | 2012-01-18 18:04:09 +0200 | [diff] [blame] | 191 | /* Global TX Fifo Size Register */ |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 192 | #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) |
| 193 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) |
Felipe Balbi | 457e84b | 2012-01-18 18:04:09 +0200 | [diff] [blame] | 194 | |
Felipe Balbi | 68d6a01 | 2013-06-12 21:09:26 +0300 | [diff] [blame] | 195 | /* Global Event Size Registers */ |
| 196 | #define DWC3_GEVNTSIZ_INTMASK (1 << 31) |
| 197 | #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) |
| 198 | |
Felipe Balbi | aabb707 | 2011-09-30 10:58:50 +0300 | [diff] [blame] | 199 | /* Global HWPARAMS1 Register */ |
Paul Zimmerman | 1d04679 | 2012-02-15 18:56:56 -0800 | [diff] [blame] | 200 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) |
Felipe Balbi | aabb707 | 2011-09-30 10:58:50 +0300 | [diff] [blame] | 201 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 |
| 202 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 203 | #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 |
| 204 | #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) |
| 205 | #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) |
| 206 | |
Paul Zimmerman | 0e1e5c4 | 2014-05-23 11:39:24 -0700 | [diff] [blame] | 207 | /* Global HWPARAMS3 Register */ |
| 208 | #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) |
| 209 | #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 |
| 210 | #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 |
| 211 | #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) |
| 212 | #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 |
| 213 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 |
| 214 | #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 |
| 215 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 |
| 216 | #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) |
| 217 | #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 |
| 218 | #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 |
| 219 | |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 220 | /* Global HWPARAMS4 Register */ |
| 221 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) |
| 222 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 |
Felipe Balbi | aabb707 | 2011-09-30 10:58:50 +0300 | [diff] [blame] | 223 | |
Huang Rui | 946bd57 | 2014-10-28 19:54:23 +0800 | [diff] [blame] | 224 | /* Global HWPARAMS6 Register */ |
| 225 | #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) |
| 226 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 227 | /* Device Configuration Register */ |
| 228 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) |
| 229 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) |
| 230 | |
| 231 | #define DWC3_DCFG_SPEED_MASK (7 << 0) |
| 232 | #define DWC3_DCFG_SUPERSPEED (4 << 0) |
| 233 | #define DWC3_DCFG_HIGHSPEED (0 << 0) |
| 234 | #define DWC3_DCFG_FULLSPEED2 (1 << 0) |
| 235 | #define DWC3_DCFG_LOWSPEED (2 << 0) |
| 236 | #define DWC3_DCFG_FULLSPEED1 (3 << 0) |
| 237 | |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 238 | #define DWC3_DCFG_LPM_CAP (1 << 22) |
| 239 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 240 | /* Device Control Register */ |
| 241 | #define DWC3_DCTL_RUN_STOP (1 << 31) |
| 242 | #define DWC3_DCTL_CSFTRST (1 << 30) |
| 243 | #define DWC3_DCTL_LSFTRST (1 << 29) |
| 244 | |
| 245 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) |
Pratyush Anand | 7e39b81 | 2012-06-06 19:18:29 +0530 | [diff] [blame] | 246 | #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 247 | |
| 248 | #define DWC3_DCTL_APPL1RES (1 << 23) |
| 249 | |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 250 | /* These apply for core versions 1.87a and earlier */ |
| 251 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) |
| 252 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) |
| 253 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) |
| 254 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) |
| 255 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) |
| 256 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) |
| 257 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) |
Felipe Balbi | 8db7ed1 | 2012-01-18 18:32:29 +0200 | [diff] [blame] | 258 | |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 259 | /* These apply for core versions 1.94a and later */ |
Huang Rui | 80caf7d | 2014-10-28 19:54:26 +0800 | [diff] [blame] | 260 | #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) |
| 261 | #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) |
Felipe Balbi | 8db7ed1 | 2012-01-18 18:32:29 +0200 | [diff] [blame] | 262 | |
Huang Rui | 80caf7d | 2014-10-28 19:54:26 +0800 | [diff] [blame] | 263 | #define DWC3_DCTL_KEEP_CONNECT (1 << 19) |
| 264 | #define DWC3_DCTL_L1_HIBER_EN (1 << 18) |
| 265 | #define DWC3_DCTL_CRS (1 << 17) |
| 266 | #define DWC3_DCTL_CSS (1 << 16) |
| 267 | |
| 268 | #define DWC3_DCTL_INITU2ENA (1 << 12) |
| 269 | #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) |
| 270 | #define DWC3_DCTL_INITU1ENA (1 << 10) |
| 271 | #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) |
| 272 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 273 | |
| 274 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) |
| 275 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) |
| 276 | |
| 277 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) |
| 278 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) |
| 279 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) |
| 280 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) |
| 281 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) |
| 282 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) |
| 283 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) |
| 284 | |
| 285 | /* Device Event Enable Register */ |
| 286 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) |
| 287 | #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) |
| 288 | #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) |
| 289 | #define DWC3_DEVTEN_ERRTICERREN (1 << 9) |
| 290 | #define DWC3_DEVTEN_SOFEN (1 << 7) |
| 291 | #define DWC3_DEVTEN_EOPFEN (1 << 6) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 292 | #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 293 | #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) |
| 294 | #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) |
| 295 | #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) |
| 296 | #define DWC3_DEVTEN_USBRSTEN (1 << 1) |
| 297 | #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) |
| 298 | |
| 299 | /* Device Status Register */ |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 300 | #define DWC3_DSTS_DCNRD (1 << 29) |
| 301 | |
| 302 | /* This applies for core versions 1.87a and earlier */ |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 303 | #define DWC3_DSTS_PWRUPREQ (1 << 24) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 304 | |
| 305 | /* These apply for core versions 1.94a and later */ |
| 306 | #define DWC3_DSTS_RSS (1 << 25) |
| 307 | #define DWC3_DSTS_SSS (1 << 24) |
| 308 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 309 | #define DWC3_DSTS_COREIDLE (1 << 23) |
| 310 | #define DWC3_DSTS_DEVCTRLHLT (1 << 22) |
| 311 | |
| 312 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) |
| 313 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) |
| 314 | |
| 315 | #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) |
| 316 | |
Pratyush Anand | d05b818 | 2012-05-21 14:51:30 +0530 | [diff] [blame] | 317 | #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 318 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) |
| 319 | |
| 320 | #define DWC3_DSTS_CONNECTSPD (7 << 0) |
| 321 | |
| 322 | #define DWC3_DSTS_SUPERSPEED (4 << 0) |
| 323 | #define DWC3_DSTS_HIGHSPEED (0 << 0) |
| 324 | #define DWC3_DSTS_FULLSPEED2 (1 << 0) |
| 325 | #define DWC3_DSTS_LOWSPEED (2 << 0) |
| 326 | #define DWC3_DSTS_FULLSPEED1 (3 << 0) |
| 327 | |
| 328 | /* Device Generic Command Register */ |
| 329 | #define DWC3_DGCMD_SET_LMP 0x01 |
| 330 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 |
| 331 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 332 | |
| 333 | /* These apply for core versions 1.94a and later */ |
| 334 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 |
| 335 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 |
| 336 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 337 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 |
| 338 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a |
| 339 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c |
| 340 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 |
| 341 | |
Felipe Balbi | b09bb64 | 2012-04-24 16:19:11 +0300 | [diff] [blame] | 342 | #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) |
| 343 | #define DWC3_DGCMD_CMDACT (1 << 10) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 344 | #define DWC3_DGCMD_CMDIOC (1 << 8) |
| 345 | |
| 346 | /* Device Generic Command Parameter Register */ |
| 347 | #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) |
| 348 | #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) |
| 349 | #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) |
| 350 | #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) |
| 351 | #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) |
| 352 | #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) |
Felipe Balbi | b09bb64 | 2012-04-24 16:19:11 +0300 | [diff] [blame] | 353 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 354 | /* Device Endpoint Command Register */ |
| 355 | #define DWC3_DEPCMD_PARAM_SHIFT 16 |
Paul Zimmerman | 1d04679 | 2012-02-15 18:56:56 -0800 | [diff] [blame] | 356 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) |
Felipe Balbi | 835fadb | 2013-12-19 14:02:53 -0600 | [diff] [blame] | 357 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) |
Felipe Balbi | b09bb64 | 2012-04-24 16:19:11 +0300 | [diff] [blame] | 358 | #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 359 | #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) |
| 360 | #define DWC3_DEPCMD_CMDACT (1 << 10) |
| 361 | #define DWC3_DEPCMD_CMDIOC (1 << 8) |
| 362 | |
| 363 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) |
| 364 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) |
| 365 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) |
| 366 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) |
| 367 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) |
| 368 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 369 | /* This applies for core versions 1.90a and earlier */ |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 370 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 371 | /* This applies for core versions 1.94a and later */ |
| 372 | #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 373 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) |
| 374 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) |
| 375 | |
| 376 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ |
| 377 | #define DWC3_DALEPENA_EP(n) (1 << n) |
| 378 | |
| 379 | #define DWC3_DEPCMD_TYPE_CONTROL 0 |
| 380 | #define DWC3_DEPCMD_TYPE_ISOC 1 |
| 381 | #define DWC3_DEPCMD_TYPE_BULK 2 |
| 382 | #define DWC3_DEPCMD_TYPE_INTR 3 |
| 383 | |
| 384 | /* Structures */ |
| 385 | |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 386 | struct dwc3_trb; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 387 | |
| 388 | /** |
| 389 | * struct dwc3_event_buffer - Software event buffer representation |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 390 | * @buf: _THE_ buffer |
| 391 | * @length: size of this buffer |
Felipe Balbi | abed411 | 2011-07-04 20:20:04 +0300 | [diff] [blame] | 392 | * @lpos: event offset |
Felipe Balbi | 60d04bb | 2011-07-04 20:23:14 +0300 | [diff] [blame] | 393 | * @count: cache of last read event count register |
Felipe Balbi | abed411 | 2011-07-04 20:20:04 +0300 | [diff] [blame] | 394 | * @flags: flags related to this event buffer |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 395 | * @dma: dma_addr_t |
| 396 | * @dwc: pointer to DWC controller |
| 397 | */ |
| 398 | struct dwc3_event_buffer { |
| 399 | void *buf; |
| 400 | unsigned length; |
| 401 | unsigned int lpos; |
Felipe Balbi | 60d04bb | 2011-07-04 20:23:14 +0300 | [diff] [blame] | 402 | unsigned int count; |
Felipe Balbi | abed411 | 2011-07-04 20:20:04 +0300 | [diff] [blame] | 403 | unsigned int flags; |
| 404 | |
| 405 | #define DWC3_EVENT_PENDING BIT(0) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 406 | |
| 407 | dma_addr_t dma; |
| 408 | |
| 409 | struct dwc3 *dwc; |
| 410 | }; |
| 411 | |
| 412 | #define DWC3_EP_FLAG_STALLED (1 << 0) |
| 413 | #define DWC3_EP_FLAG_WEDGED (1 << 1) |
| 414 | |
| 415 | #define DWC3_EP_DIRECTION_TX true |
| 416 | #define DWC3_EP_DIRECTION_RX false |
| 417 | |
| 418 | #define DWC3_TRB_NUM 32 |
| 419 | #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) |
| 420 | |
| 421 | /** |
| 422 | * struct dwc3_ep - device side endpoint representation |
| 423 | * @endpoint: usb endpoint |
| 424 | * @request_list: list of requests for this endpoint |
| 425 | * @req_queued: list of requests on this ep which have TRBs setup |
| 426 | * @trb_pool: array of transaction buffers |
| 427 | * @trb_pool_dma: dma address of @trb_pool |
| 428 | * @free_slot: next slot which is going to be used |
| 429 | * @busy_slot: first slot which is owned by HW |
| 430 | * @desc: usb_endpoint_descriptor pointer |
| 431 | * @dwc: pointer to DWC controller |
Paul Zimmerman | 4cfcf87 | 2012-04-27 13:56:23 +0300 | [diff] [blame] | 432 | * @saved_state: ep state saved during hibernation |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 433 | * @flags: endpoint flags (wedged, stalled, ...) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 434 | * @number: endpoint number (1 - 15) |
| 435 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK |
Felipe Balbi | b4996a8 | 2012-06-06 12:04:13 +0300 | [diff] [blame] | 436 | * @resource_index: Resource transfer index |
Huang Rui | c75f52f | 2013-06-12 23:43:11 +0800 | [diff] [blame] | 437 | * @interval: the interval on which the ISOC transfer is started |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 438 | * @name: a human readable name e.g. ep1out-bulk |
| 439 | * @direction: true for TX, false for RX |
Felipe Balbi | 879631a | 2011-09-30 10:58:47 +0300 | [diff] [blame] | 440 | * @stream_capable: true when streams are enabled |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 441 | */ |
| 442 | struct dwc3_ep { |
| 443 | struct usb_ep endpoint; |
| 444 | struct list_head request_list; |
| 445 | struct list_head req_queued; |
| 446 | |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 447 | struct dwc3_trb *trb_pool; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 448 | dma_addr_t trb_pool_dma; |
| 449 | u32 free_slot; |
| 450 | u32 busy_slot; |
Felipe Balbi | c90bfae | 2011-11-29 13:11:21 +0200 | [diff] [blame] | 451 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 452 | struct dwc3 *dwc; |
| 453 | |
Paul Zimmerman | 4cfcf87 | 2012-04-27 13:56:23 +0300 | [diff] [blame] | 454 | u32 saved_state; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 455 | unsigned flags; |
| 456 | #define DWC3_EP_ENABLED (1 << 0) |
| 457 | #define DWC3_EP_STALL (1 << 1) |
| 458 | #define DWC3_EP_WEDGE (1 << 2) |
| 459 | #define DWC3_EP_BUSY (1 << 4) |
| 460 | #define DWC3_EP_PENDING_REQUEST (1 << 5) |
Pratyush Anand | d6d6ec7 | 2012-05-25 18:54:56 +0530 | [diff] [blame] | 461 | #define DWC3_EP_MISSED_ISOC (1 << 6) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 462 | |
Felipe Balbi | 984f66a | 2011-08-27 22:26:00 +0300 | [diff] [blame] | 463 | /* This last one is specific to EP0 */ |
| 464 | #define DWC3_EP0_DIR_IN (1 << 31) |
| 465 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 466 | u8 number; |
| 467 | u8 type; |
Felipe Balbi | b4996a8 | 2012-06-06 12:04:13 +0300 | [diff] [blame] | 468 | u8 resource_index; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 469 | u32 interval; |
| 470 | |
| 471 | char name[20]; |
| 472 | |
| 473 | unsigned direction:1; |
Felipe Balbi | 879631a | 2011-09-30 10:58:47 +0300 | [diff] [blame] | 474 | unsigned stream_capable:1; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 475 | }; |
| 476 | |
| 477 | enum dwc3_phy { |
| 478 | DWC3_PHY_UNKNOWN = 0, |
| 479 | DWC3_PHY_USB3, |
| 480 | DWC3_PHY_USB2, |
| 481 | }; |
| 482 | |
Felipe Balbi | b53c772 | 2011-08-30 15:50:40 +0300 | [diff] [blame] | 483 | enum dwc3_ep0_next { |
| 484 | DWC3_EP0_UNKNOWN = 0, |
| 485 | DWC3_EP0_COMPLETE, |
Felipe Balbi | b53c772 | 2011-08-30 15:50:40 +0300 | [diff] [blame] | 486 | DWC3_EP0_NRDY_DATA, |
| 487 | DWC3_EP0_NRDY_STATUS, |
| 488 | }; |
| 489 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 490 | enum dwc3_ep0_state { |
| 491 | EP0_UNCONNECTED = 0, |
Felipe Balbi | c7fcdeb | 2011-08-27 22:28:36 +0300 | [diff] [blame] | 492 | EP0_SETUP_PHASE, |
| 493 | EP0_DATA_PHASE, |
| 494 | EP0_STATUS_PHASE, |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 495 | }; |
| 496 | |
| 497 | enum dwc3_link_state { |
| 498 | /* In SuperSpeed */ |
| 499 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ |
| 500 | DWC3_LINK_STATE_U1 = 0x01, |
| 501 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ |
| 502 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ |
| 503 | DWC3_LINK_STATE_SS_DIS = 0x04, |
| 504 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ |
| 505 | DWC3_LINK_STATE_SS_INACT = 0x06, |
| 506 | DWC3_LINK_STATE_POLL = 0x07, |
| 507 | DWC3_LINK_STATE_RECOV = 0x08, |
| 508 | DWC3_LINK_STATE_HRESET = 0x09, |
| 509 | DWC3_LINK_STATE_CMPLY = 0x0a, |
| 510 | DWC3_LINK_STATE_LPBK = 0x0b, |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 511 | DWC3_LINK_STATE_RESET = 0x0e, |
| 512 | DWC3_LINK_STATE_RESUME = 0x0f, |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 513 | DWC3_LINK_STATE_MASK = 0x0f, |
| 514 | }; |
| 515 | |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 516 | /* TRB Length, PCM and Status */ |
| 517 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) |
| 518 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) |
| 519 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) |
Pratyush Anand | 389f282 | 2012-05-21 12:46:26 +0530 | [diff] [blame] | 520 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 521 | |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 522 | #define DWC3_TRBSTS_OK 0 |
| 523 | #define DWC3_TRBSTS_MISSED_ISOC 1 |
| 524 | #define DWC3_TRBSTS_SETUP_PENDING 2 |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 525 | #define DWC3_TRB_STS_XFER_IN_PROG 4 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 526 | |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 527 | /* TRB Control */ |
| 528 | #define DWC3_TRB_CTRL_HWO (1 << 0) |
| 529 | #define DWC3_TRB_CTRL_LST (1 << 1) |
| 530 | #define DWC3_TRB_CTRL_CHN (1 << 2) |
| 531 | #define DWC3_TRB_CTRL_CSP (1 << 3) |
| 532 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) |
| 533 | #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) |
| 534 | #define DWC3_TRB_CTRL_IOC (1 << 11) |
| 535 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) |
| 536 | |
| 537 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) |
| 538 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) |
| 539 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) |
| 540 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) |
| 541 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) |
| 542 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) |
| 543 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) |
| 544 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 545 | |
| 546 | /** |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 547 | * struct dwc3_trb - transfer request block (hw format) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 548 | * @bpl: DW0-3 |
| 549 | * @bph: DW4-7 |
| 550 | * @size: DW8-B |
| 551 | * @trl: DWC-F |
| 552 | */ |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 553 | struct dwc3_trb { |
| 554 | u32 bpl; |
| 555 | u32 bph; |
| 556 | u32 size; |
| 557 | u32 ctrl; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 558 | } __packed; |
| 559 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 560 | /** |
Felipe Balbi | a329949 | 2011-09-30 10:58:48 +0300 | [diff] [blame] | 561 | * dwc3_hwparams - copy of HWPARAMS registers |
| 562 | * @hwparams0 - GHWPARAMS0 |
| 563 | * @hwparams1 - GHWPARAMS1 |
| 564 | * @hwparams2 - GHWPARAMS2 |
| 565 | * @hwparams3 - GHWPARAMS3 |
| 566 | * @hwparams4 - GHWPARAMS4 |
| 567 | * @hwparams5 - GHWPARAMS5 |
| 568 | * @hwparams6 - GHWPARAMS6 |
| 569 | * @hwparams7 - GHWPARAMS7 |
| 570 | * @hwparams8 - GHWPARAMS8 |
| 571 | */ |
| 572 | struct dwc3_hwparams { |
| 573 | u32 hwparams0; |
| 574 | u32 hwparams1; |
| 575 | u32 hwparams2; |
| 576 | u32 hwparams3; |
| 577 | u32 hwparams4; |
| 578 | u32 hwparams5; |
| 579 | u32 hwparams6; |
| 580 | u32 hwparams7; |
| 581 | u32 hwparams8; |
| 582 | }; |
| 583 | |
Felipe Balbi | 0949e99 | 2011-10-12 10:44:56 +0300 | [diff] [blame] | 584 | /* HWPARAMS0 */ |
| 585 | #define DWC3_MODE(n) ((n) & 0x7) |
| 586 | |
Felipe Balbi | 457e84b | 2012-01-18 18:04:09 +0200 | [diff] [blame] | 587 | #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) |
| 588 | |
Felipe Balbi | 0949e99 | 2011-10-12 10:44:56 +0300 | [diff] [blame] | 589 | /* HWPARAMS1 */ |
Felipe Balbi | 457e84b | 2012-01-18 18:04:09 +0200 | [diff] [blame] | 590 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
| 591 | |
Felipe Balbi | 789451f6 | 2011-05-05 15:53:10 +0300 | [diff] [blame] | 592 | /* HWPARAMS3 */ |
| 593 | #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) |
| 594 | #define DWC3_NUM_EPS_MASK (0x3f << 12) |
| 595 | #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ |
| 596 | (DWC3_NUM_EPS_MASK)) >> 12) |
| 597 | #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ |
| 598 | (DWC3_NUM_IN_EPS_MASK)) >> 18) |
| 599 | |
Felipe Balbi | 457e84b | 2012-01-18 18:04:09 +0200 | [diff] [blame] | 600 | /* HWPARAMS7 */ |
| 601 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) |
Felipe Balbi | 9f622b2 | 2011-10-12 10:31:04 +0300 | [diff] [blame] | 602 | |
Sebastian Andrzej Siewior | e0ce0b0 | 2011-11-25 12:03:46 +0100 | [diff] [blame] | 603 | struct dwc3_request { |
| 604 | struct usb_request request; |
| 605 | struct list_head list; |
| 606 | struct dwc3_ep *dep; |
Pratyush Anand | e5ba5ec | 2013-01-14 15:59:37 +0530 | [diff] [blame] | 607 | u32 start_slot; |
Sebastian Andrzej Siewior | e0ce0b0 | 2011-11-25 12:03:46 +0100 | [diff] [blame] | 608 | |
| 609 | u8 epnum; |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 610 | struct dwc3_trb *trb; |
Sebastian Andrzej Siewior | e0ce0b0 | 2011-11-25 12:03:46 +0100 | [diff] [blame] | 611 | dma_addr_t trb_dma; |
| 612 | |
| 613 | unsigned direction:1; |
| 614 | unsigned mapped:1; |
| 615 | unsigned queued:1; |
| 616 | }; |
| 617 | |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 618 | /* |
| 619 | * struct dwc3_scratchpad_array - hibernation scratchpad array |
| 620 | * (format defined by hw) |
| 621 | */ |
| 622 | struct dwc3_scratchpad_array { |
| 623 | __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; |
| 624 | }; |
| 625 | |
Felipe Balbi | a329949 | 2011-09-30 10:58:48 +0300 | [diff] [blame] | 626 | /** |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 627 | * struct dwc3 - representation of our controller |
Felipe Balbi | 91db07d | 2011-08-27 01:40:52 +0300 | [diff] [blame] | 628 | * @ctrl_req: usb control request which is used for ep0 |
| 629 | * @ep0_trb: trb which is used for the ctrl_req |
Felipe Balbi | 5812b1c | 2011-08-27 22:07:53 +0300 | [diff] [blame] | 630 | * @ep0_bounce: bounce buffer for ep0 |
Felipe Balbi | 91db07d | 2011-08-27 01:40:52 +0300 | [diff] [blame] | 631 | * @setup_buf: used while precessing STD USB requests |
| 632 | * @ctrl_req_addr: dma address of ctrl_req |
| 633 | * @ep0_trb: dma address of ep0_trb |
| 634 | * @ep0_usb_req: dummy req used while handling STD USB requests |
Felipe Balbi | 5812b1c | 2011-08-27 22:07:53 +0300 | [diff] [blame] | 635 | * @ep0_bounce_addr: dma address of ep0_bounce |
Felipe Balbi | 0ffcaf3 | 2013-12-19 13:04:28 -0600 | [diff] [blame] | 636 | * @scratch_addr: dma address of scratchbuf |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 637 | * @lock: for synchronizing |
| 638 | * @dev: pointer to our struct device |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 639 | * @xhci: pointer to our xHCI child |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 640 | * @event_buffer_list: a list of event buffers |
| 641 | * @gadget: device side representation of the peripheral controller |
| 642 | * @gadget_driver: pointer to the gadget driver |
| 643 | * @regs: base address for our registers |
| 644 | * @regs_size: address space size |
Felipe Balbi | 0ffcaf3 | 2013-12-19 13:04:28 -0600 | [diff] [blame] | 645 | * @nr_scratch: number of scratch buffers |
Felipe Balbi | 9f622b2 | 2011-10-12 10:31:04 +0300 | [diff] [blame] | 646 | * @num_event_buffers: calculated number of event buffers |
Felipe Balbi | fae2b90 | 2011-10-14 13:00:30 +0300 | [diff] [blame] | 647 | * @u1u2: only used on revisions <1.83a for workaround |
Felipe Balbi | 6c167fc | 2011-10-07 22:55:04 +0300 | [diff] [blame] | 648 | * @maximum_speed: maximum speed requested (mainly for testing purposes) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 649 | * @revision: revision register contents |
Ruchika Kharwar | a45c82b8 | 2013-07-06 07:52:49 -0500 | [diff] [blame] | 650 | * @dr_mode: requested mode of operation |
Felipe Balbi | 51e1e7b | 2012-07-19 14:09:48 +0300 | [diff] [blame] | 651 | * @usb2_phy: pointer to USB2 PHY |
| 652 | * @usb3_phy: pointer to USB3 PHY |
Kishon Vijay Abraham I | 5730348 | 2014-03-03 17:08:11 +0530 | [diff] [blame] | 653 | * @usb2_generic_phy: pointer to USB2 PHY |
| 654 | * @usb3_generic_phy: pointer to USB3 PHY |
Felipe Balbi | 7415f17 | 2012-04-30 14:56:33 +0300 | [diff] [blame] | 655 | * @dcfg: saved contents of DCFG register |
| 656 | * @gctl: saved contents of GCTL register |
Felipe Balbi | c12a0d8 | 2012-04-25 10:45:05 +0300 | [diff] [blame] | 657 | * @isoch_delay: wValue from Set Isochronous Delay request; |
Felipe Balbi | 865e09e | 2012-04-24 16:19:49 +0300 | [diff] [blame] | 658 | * @u2sel: parameter from Set SEL request. |
| 659 | * @u2pel: parameter from Set SEL request. |
| 660 | * @u1sel: parameter from Set SEL request. |
| 661 | * @u1pel: parameter from Set SEL request. |
Felipe Balbi | 789451f6 | 2011-05-05 15:53:10 +0300 | [diff] [blame] | 662 | * @num_out_eps: number of out endpoints |
| 663 | * @num_in_eps: number of in endpoints |
Felipe Balbi | b53c772 | 2011-08-30 15:50:40 +0300 | [diff] [blame] | 664 | * @ep0_next_event: hold the next expected event |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 665 | * @ep0state: state of endpoint zero |
| 666 | * @link_state: link state |
| 667 | * @speed: device speed (super, high, full, low) |
| 668 | * @mem: points to start of memory which is used for this struct. |
Felipe Balbi | a329949 | 2011-09-30 10:58:48 +0300 | [diff] [blame] | 669 | * @hwparams: copy of hwparams registers |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 670 | * @root: debugfs root folder pointer |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 671 | * @regset: debugfs pointer to regdump file |
| 672 | * @test_mode: true when we're entering a USB test mode |
| 673 | * @test_mode_nr: test feature selector |
Huang Rui | 80caf7d | 2014-10-28 19:54:26 +0800 | [diff] [blame] | 674 | * @lpm_nyet_threshold: LPM NYET response threshold |
Huang Rui | 460d098 | 2014-10-31 11:11:18 +0800 | [diff] [blame] | 675 | * @hird_threshold: HIRD threshold |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 676 | * @delayed_status: true when gadget driver asks for delayed status |
| 677 | * @ep0_bounced: true when we used bounce buffer |
| 678 | * @ep0_expect_in: true when we expect a DATA IN transfer |
Felipe Balbi | 81bc559 | 2013-12-19 12:14:29 -0600 | [diff] [blame] | 679 | * @has_hibernation: true when dwc3 was configured with Hibernation |
Huang Rui | 80caf7d | 2014-10-28 19:54:26 +0800 | [diff] [blame] | 680 | * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that |
| 681 | * there's now way for software to detect this in runtime. |
Huang Rui | 460d098 | 2014-10-31 11:11:18 +0800 | [diff] [blame] | 682 | * @is_utmi_l1_suspend: the core asserts output signal |
| 683 | * 0 - utmi_sleep_n |
| 684 | * 1 - utmi_l1_suspend_n |
Huang Rui | 946bd57 | 2014-10-28 19:54:23 +0800 | [diff] [blame] | 685 | * @is_fpga: true when we are using the FPGA board |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 686 | * @needs_fifo_resize: not all users might want fifo resizing, flag it |
| 687 | * @pullups_connected: true when Run/Stop bit is set |
| 688 | * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. |
| 689 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround |
| 690 | * @start_config_issued: true when StartConfig command has been issued |
| 691 | * @three_stage_setup: set if we perform a three phase setup |
Huang Rui | 3b81221 | 2014-10-28 19:54:25 +0800 | [diff] [blame] | 692 | * @disable_scramble_quirk: set if we enable the disable scramble quirk |
Huang Rui | 9a5b2f3 | 2014-10-28 19:54:27 +0800 | [diff] [blame] | 693 | * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk |
Huang Rui | b5a65c4 | 2014-10-28 19:54:28 +0800 | [diff] [blame] | 694 | * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk |
Huang Rui | df31f5b | 2014-10-28 19:54:29 +0800 | [diff] [blame] | 695 | * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk |
Huang Rui | a2a1d0f | 2014-10-28 19:54:30 +0800 | [diff] [blame] | 696 | * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk |
Huang Rui | 41c06ff | 2014-10-28 19:54:31 +0800 | [diff] [blame] | 697 | * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk |
Huang Rui | fb67afc | 2014-10-28 19:54:32 +0800 | [diff] [blame] | 698 | * @lfps_filter_quirk: set if we enable LFPS filter quirk |
Huang Rui | 14f4ac5 | 2014-10-28 19:54:33 +0800 | [diff] [blame] | 699 | * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk |
Huang Rui | 59acfa2 | 2014-10-31 11:11:13 +0800 | [diff] [blame] | 700 | * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy |
Huang Rui | 0effe0a | 2014-10-31 11:11:14 +0800 | [diff] [blame] | 701 | * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy |
Huang Rui | 6b6a0c9 | 2014-10-31 11:11:12 +0800 | [diff] [blame] | 702 | * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk |
| 703 | * @tx_de_emphasis: Tx de-emphasis value |
| 704 | * 0 - -6dB de-emphasis |
| 705 | * 1 - -3.5dB de-emphasis |
| 706 | * 2 - No de-emphasis |
| 707 | * 3 - Reserved |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 708 | */ |
| 709 | struct dwc3 { |
| 710 | struct usb_ctrlrequest *ctrl_req; |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 711 | struct dwc3_trb *ep0_trb; |
Felipe Balbi | 5812b1c | 2011-08-27 22:07:53 +0300 | [diff] [blame] | 712 | void *ep0_bounce; |
Felipe Balbi | 0ffcaf3 | 2013-12-19 13:04:28 -0600 | [diff] [blame] | 713 | void *scratchbuf; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 714 | u8 *setup_buf; |
| 715 | dma_addr_t ctrl_req_addr; |
| 716 | dma_addr_t ep0_trb_addr; |
Felipe Balbi | 5812b1c | 2011-08-27 22:07:53 +0300 | [diff] [blame] | 717 | dma_addr_t ep0_bounce_addr; |
Felipe Balbi | 0ffcaf3 | 2013-12-19 13:04:28 -0600 | [diff] [blame] | 718 | dma_addr_t scratch_addr; |
Sebastian Andrzej Siewior | e0ce0b0 | 2011-11-25 12:03:46 +0100 | [diff] [blame] | 719 | struct dwc3_request ep0_usb_req; |
Felipe Balbi | 789451f6 | 2011-05-05 15:53:10 +0300 | [diff] [blame] | 720 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 721 | /* device lock */ |
| 722 | spinlock_t lock; |
Felipe Balbi | 789451f6 | 2011-05-05 15:53:10 +0300 | [diff] [blame] | 723 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 724 | struct device *dev; |
| 725 | |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 726 | struct platform_device *xhci; |
Ido Shayevitz | 51249dc | 2012-04-24 14:18:39 +0300 | [diff] [blame] | 727 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 728 | |
Felipe Balbi | 457d3f2 | 2011-10-24 12:03:13 +0300 | [diff] [blame] | 729 | struct dwc3_event_buffer **ev_buffs; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 730 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
| 731 | |
| 732 | struct usb_gadget gadget; |
| 733 | struct usb_gadget_driver *gadget_driver; |
| 734 | |
Felipe Balbi | 51e1e7b | 2012-07-19 14:09:48 +0300 | [diff] [blame] | 735 | struct usb_phy *usb2_phy; |
| 736 | struct usb_phy *usb3_phy; |
| 737 | |
Kishon Vijay Abraham I | 5730348 | 2014-03-03 17:08:11 +0530 | [diff] [blame] | 738 | struct phy *usb2_generic_phy; |
| 739 | struct phy *usb3_generic_phy; |
| 740 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 741 | void __iomem *regs; |
| 742 | size_t regs_size; |
| 743 | |
Ruchika Kharwar | a45c82b8 | 2013-07-06 07:52:49 -0500 | [diff] [blame] | 744 | enum usb_dr_mode dr_mode; |
| 745 | |
Felipe Balbi | 7415f17 | 2012-04-30 14:56:33 +0300 | [diff] [blame] | 746 | /* used for suspend/resume */ |
| 747 | u32 dcfg; |
| 748 | u32 gctl; |
| 749 | |
Felipe Balbi | 0ffcaf3 | 2013-12-19 13:04:28 -0600 | [diff] [blame] | 750 | u32 nr_scratch; |
Felipe Balbi | 9f622b2 | 2011-10-12 10:31:04 +0300 | [diff] [blame] | 751 | u32 num_event_buffers; |
Felipe Balbi | fae2b90 | 2011-10-14 13:00:30 +0300 | [diff] [blame] | 752 | u32 u1u2; |
Felipe Balbi | 6c167fc | 2011-10-07 22:55:04 +0300 | [diff] [blame] | 753 | u32 maximum_speed; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 754 | u32 revision; |
| 755 | |
| 756 | #define DWC3_REVISION_173A 0x5533173a |
| 757 | #define DWC3_REVISION_175A 0x5533175a |
| 758 | #define DWC3_REVISION_180A 0x5533180a |
| 759 | #define DWC3_REVISION_183A 0x5533183a |
| 760 | #define DWC3_REVISION_185A 0x5533185a |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 761 | #define DWC3_REVISION_187A 0x5533187a |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 762 | #define DWC3_REVISION_188A 0x5533188a |
| 763 | #define DWC3_REVISION_190A 0x5533190a |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 764 | #define DWC3_REVISION_194A 0x5533194a |
Felipe Balbi | 1522d70 | 2012-03-23 12:10:48 +0200 | [diff] [blame] | 765 | #define DWC3_REVISION_200A 0x5533200a |
| 766 | #define DWC3_REVISION_202A 0x5533202a |
| 767 | #define DWC3_REVISION_210A 0x5533210a |
| 768 | #define DWC3_REVISION_220A 0x5533220a |
Felipe Balbi | 7ac6a59 | 2012-09-18 21:22:32 +0300 | [diff] [blame] | 769 | #define DWC3_REVISION_230A 0x5533230a |
| 770 | #define DWC3_REVISION_240A 0x5533240a |
| 771 | #define DWC3_REVISION_250A 0x5533250a |
Felipe Balbi | dbf5aaf | 2014-03-04 09:35:02 -0600 | [diff] [blame] | 772 | #define DWC3_REVISION_260A 0x5533260a |
| 773 | #define DWC3_REVISION_270A 0x5533270a |
| 774 | #define DWC3_REVISION_280A 0x5533280a |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 775 | |
Felipe Balbi | b53c772 | 2011-08-30 15:50:40 +0300 | [diff] [blame] | 776 | enum dwc3_ep0_next ep0_next_event; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 777 | enum dwc3_ep0_state ep0state; |
| 778 | enum dwc3_link_state link_state; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 779 | |
Felipe Balbi | c12a0d8 | 2012-04-25 10:45:05 +0300 | [diff] [blame] | 780 | u16 isoch_delay; |
Felipe Balbi | 865e09e | 2012-04-24 16:19:49 +0300 | [diff] [blame] | 781 | u16 u2sel; |
| 782 | u16 u2pel; |
| 783 | u8 u1sel; |
| 784 | u8 u1pel; |
| 785 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 786 | u8 speed; |
Felipe Balbi | 865e09e | 2012-04-24 16:19:49 +0300 | [diff] [blame] | 787 | |
Felipe Balbi | 789451f6 | 2011-05-05 15:53:10 +0300 | [diff] [blame] | 788 | u8 num_out_eps; |
| 789 | u8 num_in_eps; |
| 790 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 791 | void *mem; |
| 792 | |
Felipe Balbi | a329949 | 2011-09-30 10:58:48 +0300 | [diff] [blame] | 793 | struct dwc3_hwparams hwparams; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 794 | struct dentry *root; |
Felipe Balbi | d766802 | 2013-01-18 10:21:34 +0200 | [diff] [blame] | 795 | struct debugfs_regset32 *regset; |
Gerard Cauvy | 3b63736 | 2012-02-10 12:21:18 +0200 | [diff] [blame] | 796 | |
| 797 | u8 test_mode; |
| 798 | u8 test_mode_nr; |
Huang Rui | 80caf7d | 2014-10-28 19:54:26 +0800 | [diff] [blame] | 799 | u8 lpm_nyet_threshold; |
Huang Rui | 460d098 | 2014-10-31 11:11:18 +0800 | [diff] [blame] | 800 | u8 hird_threshold; |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 801 | |
| 802 | unsigned delayed_status:1; |
| 803 | unsigned ep0_bounced:1; |
| 804 | unsigned ep0_expect_in:1; |
Felipe Balbi | 81bc559 | 2013-12-19 12:14:29 -0600 | [diff] [blame] | 805 | unsigned has_hibernation:1; |
Huang Rui | 80caf7d | 2014-10-28 19:54:26 +0800 | [diff] [blame] | 806 | unsigned has_lpm_erratum:1; |
Huang Rui | 460d098 | 2014-10-31 11:11:18 +0800 | [diff] [blame] | 807 | unsigned is_utmi_l1_suspend:1; |
Huang Rui | 946bd57 | 2014-10-28 19:54:23 +0800 | [diff] [blame] | 808 | unsigned is_fpga:1; |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 809 | unsigned needs_fifo_resize:1; |
| 810 | unsigned pullups_connected:1; |
| 811 | unsigned resize_fifos:1; |
| 812 | unsigned setup_packet_pending:1; |
| 813 | unsigned start_config_issued:1; |
| 814 | unsigned three_stage_setup:1; |
Huang Rui | 3b81221 | 2014-10-28 19:54:25 +0800 | [diff] [blame] | 815 | |
| 816 | unsigned disable_scramble_quirk:1; |
Huang Rui | 9a5b2f3 | 2014-10-28 19:54:27 +0800 | [diff] [blame] | 817 | unsigned u2exit_lfps_quirk:1; |
Huang Rui | b5a65c4 | 2014-10-28 19:54:28 +0800 | [diff] [blame] | 818 | unsigned u2ss_inp3_quirk:1; |
Huang Rui | df31f5b | 2014-10-28 19:54:29 +0800 | [diff] [blame] | 819 | unsigned req_p1p2p3_quirk:1; |
Huang Rui | a2a1d0f | 2014-10-28 19:54:30 +0800 | [diff] [blame] | 820 | unsigned del_p1p2p3_quirk:1; |
Huang Rui | 41c06ff | 2014-10-28 19:54:31 +0800 | [diff] [blame] | 821 | unsigned del_phy_power_chg_quirk:1; |
Huang Rui | fb67afc | 2014-10-28 19:54:32 +0800 | [diff] [blame] | 822 | unsigned lfps_filter_quirk:1; |
Huang Rui | 14f4ac5 | 2014-10-28 19:54:33 +0800 | [diff] [blame] | 823 | unsigned rx_detect_poll_quirk:1; |
Huang Rui | 59acfa2 | 2014-10-31 11:11:13 +0800 | [diff] [blame] | 824 | unsigned dis_u3_susphy_quirk:1; |
Huang Rui | 0effe0a | 2014-10-31 11:11:14 +0800 | [diff] [blame] | 825 | unsigned dis_u2_susphy_quirk:1; |
Huang Rui | 6b6a0c9 | 2014-10-31 11:11:12 +0800 | [diff] [blame] | 826 | |
| 827 | unsigned tx_de_emphasis_quirk:1; |
| 828 | unsigned tx_de_emphasis:2; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 829 | }; |
| 830 | |
| 831 | /* -------------------------------------------------------------------------- */ |
| 832 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 833 | /* -------------------------------------------------------------------------- */ |
| 834 | |
| 835 | struct dwc3_event_type { |
| 836 | u32 is_devspec:1; |
Huang Rui | 1974d49 | 2013-06-27 01:08:11 +0800 | [diff] [blame] | 837 | u32 type:7; |
| 838 | u32 reserved8_31:24; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 839 | } __packed; |
| 840 | |
| 841 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 |
| 842 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 |
| 843 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 |
| 844 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 |
| 845 | #define DWC3_DEPEVT_STREAMEVT 0x06 |
| 846 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 |
| 847 | |
| 848 | /** |
| 849 | * struct dwc3_event_depvt - Device Endpoint Events |
| 850 | * @one_bit: indicates this is an endpoint event (not used) |
| 851 | * @endpoint_number: number of the endpoint |
| 852 | * @endpoint_event: The event we have: |
| 853 | * 0x00 - Reserved |
| 854 | * 0x01 - XferComplete |
| 855 | * 0x02 - XferInProgress |
| 856 | * 0x03 - XferNotReady |
| 857 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) |
| 858 | * 0x05 - Reserved |
| 859 | * 0x06 - StreamEvt |
| 860 | * 0x07 - EPCmdCmplt |
| 861 | * @reserved11_10: Reserved, don't use. |
| 862 | * @status: Indicates the status of the event. Refer to databook for |
| 863 | * more information. |
| 864 | * @parameters: Parameters of the current event. Refer to databook for |
| 865 | * more information. |
| 866 | */ |
| 867 | struct dwc3_event_depevt { |
| 868 | u32 one_bit:1; |
| 869 | u32 endpoint_number:5; |
| 870 | u32 endpoint_event:4; |
| 871 | u32 reserved11_10:2; |
| 872 | u32 status:4; |
Felipe Balbi | 40aa41fb | 2012-01-18 17:06:03 +0200 | [diff] [blame] | 873 | |
| 874 | /* Within XferNotReady */ |
| 875 | #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) |
| 876 | |
| 877 | /* Within XferComplete */ |
Paul Zimmerman | 1d04679 | 2012-02-15 18:56:56 -0800 | [diff] [blame] | 878 | #define DEPEVT_STATUS_BUSERR (1 << 0) |
| 879 | #define DEPEVT_STATUS_SHORT (1 << 1) |
| 880 | #define DEPEVT_STATUS_IOC (1 << 2) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 881 | #define DEPEVT_STATUS_LST (1 << 3) |
Felipe Balbi | dc137f0 | 2011-08-27 22:04:32 +0300 | [diff] [blame] | 882 | |
Felipe Balbi | 879631a | 2011-09-30 10:58:47 +0300 | [diff] [blame] | 883 | /* Stream event only */ |
| 884 | #define DEPEVT_STREAMEVT_FOUND 1 |
| 885 | #define DEPEVT_STREAMEVT_NOTFOUND 2 |
| 886 | |
Felipe Balbi | dc137f0 | 2011-08-27 22:04:32 +0300 | [diff] [blame] | 887 | /* Control-only Status */ |
Felipe Balbi | dc137f0 | 2011-08-27 22:04:32 +0300 | [diff] [blame] | 888 | #define DEPEVT_STATUS_CONTROL_DATA 1 |
| 889 | #define DEPEVT_STATUS_CONTROL_STATUS 2 |
| 890 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 891 | u32 parameters:16; |
| 892 | } __packed; |
| 893 | |
| 894 | /** |
| 895 | * struct dwc3_event_devt - Device Events |
| 896 | * @one_bit: indicates this is a non-endpoint event (not used) |
| 897 | * @device_event: indicates it's a device event. Should read as 0x00 |
| 898 | * @type: indicates the type of device event. |
| 899 | * 0 - DisconnEvt |
| 900 | * 1 - USBRst |
| 901 | * 2 - ConnectDone |
| 902 | * 3 - ULStChng |
| 903 | * 4 - WkUpEvt |
| 904 | * 5 - Reserved |
| 905 | * 6 - EOPF |
| 906 | * 7 - SOF |
| 907 | * 8 - Reserved |
| 908 | * 9 - ErrticErr |
| 909 | * 10 - CmdCmplt |
| 910 | * 11 - EvntOverflow |
| 911 | * 12 - VndrDevTstRcved |
| 912 | * @reserved15_12: Reserved, not used |
| 913 | * @event_info: Information about this event |
Huang Rui | 06f9b6e | 2014-01-07 17:45:50 +0800 | [diff] [blame] | 914 | * @reserved31_25: Reserved, not used |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 915 | */ |
| 916 | struct dwc3_event_devt { |
| 917 | u32 one_bit:1; |
| 918 | u32 device_event:7; |
| 919 | u32 type:4; |
| 920 | u32 reserved15_12:4; |
Huang Rui | 06f9b6e | 2014-01-07 17:45:50 +0800 | [diff] [blame] | 921 | u32 event_info:9; |
| 922 | u32 reserved31_25:7; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 923 | } __packed; |
| 924 | |
| 925 | /** |
| 926 | * struct dwc3_event_gevt - Other Core Events |
| 927 | * @one_bit: indicates this is a non-endpoint event (not used) |
| 928 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. |
| 929 | * @phy_port_number: self-explanatory |
| 930 | * @reserved31_12: Reserved, not used. |
| 931 | */ |
| 932 | struct dwc3_event_gevt { |
| 933 | u32 one_bit:1; |
| 934 | u32 device_event:7; |
| 935 | u32 phy_port_number:4; |
| 936 | u32 reserved31_12:20; |
| 937 | } __packed; |
| 938 | |
| 939 | /** |
| 940 | * union dwc3_event - representation of Event Buffer contents |
| 941 | * @raw: raw 32-bit event |
| 942 | * @type: the type of the event |
| 943 | * @depevt: Device Endpoint Event |
| 944 | * @devt: Device Event |
| 945 | * @gevt: Global Event |
| 946 | */ |
| 947 | union dwc3_event { |
| 948 | u32 raw; |
| 949 | struct dwc3_event_type type; |
| 950 | struct dwc3_event_depevt depevt; |
| 951 | struct dwc3_event_devt devt; |
| 952 | struct dwc3_event_gevt gevt; |
| 953 | }; |
| 954 | |
Felipe Balbi | 6101830 | 2014-03-04 09:23:50 -0600 | [diff] [blame] | 955 | /** |
| 956 | * struct dwc3_gadget_ep_cmd_params - representation of endpoint command |
| 957 | * parameters |
| 958 | * @param2: third parameter |
| 959 | * @param1: second parameter |
| 960 | * @param0: first parameter |
| 961 | */ |
| 962 | struct dwc3_gadget_ep_cmd_params { |
| 963 | u32 param2; |
| 964 | u32 param1; |
| 965 | u32 param0; |
| 966 | }; |
| 967 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 968 | /* |
| 969 | * DWC3 Features to be used as Driver Data |
| 970 | */ |
| 971 | |
| 972 | #define DWC3_HAS_PERIPHERAL BIT(0) |
| 973 | #define DWC3_HAS_XHCI BIT(1) |
| 974 | #define DWC3_HAS_OTG BIT(3) |
| 975 | |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 976 | /* prototypes */ |
Sebastian Andrzej Siewior | 3140e8c | 2011-10-31 22:25:40 +0100 | [diff] [blame] | 977 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
Felipe Balbi | 457e84b | 2012-01-18 18:04:09 +0200 | [diff] [blame] | 978 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); |
Sebastian Andrzej Siewior | 3140e8c | 2011-10-31 22:25:40 +0100 | [diff] [blame] | 979 | |
Vivek Gautam | 388e5c5 | 2013-01-15 16:09:21 +0530 | [diff] [blame] | 980 | #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 981 | int dwc3_host_init(struct dwc3 *dwc); |
| 982 | void dwc3_host_exit(struct dwc3 *dwc); |
Vivek Gautam | 388e5c5 | 2013-01-15 16:09:21 +0530 | [diff] [blame] | 983 | #else |
| 984 | static inline int dwc3_host_init(struct dwc3 *dwc) |
| 985 | { return 0; } |
| 986 | static inline void dwc3_host_exit(struct dwc3 *dwc) |
| 987 | { } |
| 988 | #endif |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 989 | |
Vivek Gautam | 388e5c5 | 2013-01-15 16:09:21 +0530 | [diff] [blame] | 990 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
Felipe Balbi | f80b45e | 2011-10-12 14:15:49 +0300 | [diff] [blame] | 991 | int dwc3_gadget_init(struct dwc3 *dwc); |
| 992 | void dwc3_gadget_exit(struct dwc3 *dwc); |
Felipe Balbi | 6101830 | 2014-03-04 09:23:50 -0600 | [diff] [blame] | 993 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); |
| 994 | int dwc3_gadget_get_link_state(struct dwc3 *dwc); |
| 995 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); |
| 996 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, |
| 997 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); |
Felipe Balbi | 3ece0ec | 2014-09-05 09:47:44 -0500 | [diff] [blame] | 998 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); |
Vivek Gautam | 388e5c5 | 2013-01-15 16:09:21 +0530 | [diff] [blame] | 999 | #else |
| 1000 | static inline int dwc3_gadget_init(struct dwc3 *dwc) |
| 1001 | { return 0; } |
| 1002 | static inline void dwc3_gadget_exit(struct dwc3 *dwc) |
| 1003 | { } |
Felipe Balbi | 6101830 | 2014-03-04 09:23:50 -0600 | [diff] [blame] | 1004 | static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) |
| 1005 | { return 0; } |
| 1006 | static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) |
| 1007 | { return 0; } |
| 1008 | static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, |
| 1009 | enum dwc3_link_state state) |
| 1010 | { return 0; } |
| 1011 | |
| 1012 | static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, |
| 1013 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) |
| 1014 | { return 0; } |
| 1015 | static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, |
| 1016 | int cmd, u32 param) |
| 1017 | { return 0; } |
Vivek Gautam | 388e5c5 | 2013-01-15 16:09:21 +0530 | [diff] [blame] | 1018 | #endif |
Felipe Balbi | f80b45e | 2011-10-12 14:15:49 +0300 | [diff] [blame] | 1019 | |
Felipe Balbi | 7415f17 | 2012-04-30 14:56:33 +0300 | [diff] [blame] | 1020 | /* power management interface */ |
| 1021 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) |
Felipe Balbi | 7415f17 | 2012-04-30 14:56:33 +0300 | [diff] [blame] | 1022 | int dwc3_gadget_suspend(struct dwc3 *dwc); |
| 1023 | int dwc3_gadget_resume(struct dwc3 *dwc); |
| 1024 | #else |
Felipe Balbi | 7415f17 | 2012-04-30 14:56:33 +0300 | [diff] [blame] | 1025 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) |
| 1026 | { |
| 1027 | return 0; |
| 1028 | } |
| 1029 | |
| 1030 | static inline int dwc3_gadget_resume(struct dwc3 *dwc) |
| 1031 | { |
| 1032 | return 0; |
| 1033 | } |
| 1034 | #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ |
| 1035 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1036 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |