blob: eb6e91efdec8bca0babc0d098e9e11aa7b66f257 [file] [log] [blame]
Alexey Charkov21f47fb2010-12-23 13:11:21 +01001/*
2 * arch/arm/mach-vt8500/irq.c
3 *
Tony Priske9a91de2012-08-03 21:00:06 +12004 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
Alexey Charkov21f47fb2010-12-23 13:11:21 +01005 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
Tony Priske9a91de2012-08-03 21:00:06 +120022/*
23 * This file is copied and modified from the original irq.c provided by
24 * Alexey Charkov. Minor changes have been made for Device Tree Support.
25 */
26
27#include <linux/slab.h>
Alexey Charkov21f47fb2010-12-23 13:11:21 +010028#include <linux/io.h>
29#include <linux/irq.h>
Tony Priske9a91de2012-08-03 21:00:06 +120030#include <linux/irqdomain.h>
Alexey Charkov21f47fb2010-12-23 13:11:21 +010031#include <linux/interrupt.h>
Tony Priske9a91de2012-08-03 21:00:06 +120032#include <linux/bitops.h>
33
34#include <linux/of.h>
35#include <linux/of_irq.h>
36#include <linux/of_address.h>
Alexey Charkov21f47fb2010-12-23 13:11:21 +010037
38#include <asm/irq.h>
Tony Prisk0c464d52012-10-10 20:59:32 +130039#include <asm/exception.h>
Tony Prisk06ff14c2013-03-24 01:12:25 +000040#include <asm/mach/irq.h>
41
42#include "irqchip.h"
Alexey Charkov21f47fb2010-12-23 13:11:21 +010043
Tony Priske9a91de2012-08-03 21:00:06 +120044#define VT8500_ICPC_IRQ 0x20
45#define VT8500_ICPC_FIQ 0x24
46#define VT8500_ICDC 0x40 /* Destination Control 64*u32 */
47#define VT8500_ICIS 0x80 /* Interrupt status, 16*u32 */
48
49/* ICPC */
50#define ICPC_MASK 0x3F
51#define ICPC_ROTATE BIT(6)
52
53/* IC_DCTR */
54#define ICDC_IRQ 0x00
55#define ICDC_FIQ 0x01
56#define ICDC_DSS0 0x02
57#define ICDC_DSS1 0x03
58#define ICDC_DSS2 0x04
59#define ICDC_DSS3 0x05
60#define ICDC_DSS4 0x06
61#define ICDC_DSS5 0x07
62
63#define VT8500_INT_DISABLE 0
64#define VT8500_INT_ENABLE BIT(3)
65
66#define VT8500_TRIGGER_HIGH 0
67#define VT8500_TRIGGER_RISING BIT(5)
68#define VT8500_TRIGGER_FALLING BIT(6)
Alexey Charkov21f47fb2010-12-23 13:11:21 +010069#define VT8500_EDGE ( VT8500_TRIGGER_RISING \
70 | VT8500_TRIGGER_FALLING)
Alexey Charkov21f47fb2010-12-23 13:11:21 +010071
Tony Prisk0c464d52012-10-10 20:59:32 +130072/* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
73#define VT8500_INTC_MAX 2
Tony Priske9a91de2012-08-03 21:00:06 +120074
Tony Prisk0c464d52012-10-10 20:59:32 +130075struct vt8500_irq_data {
76 void __iomem *base; /* IO Memory base address */
77 struct irq_domain *domain; /* Domain for this controller */
Tony Priske9a91de2012-08-03 21:00:06 +120078};
Alexey Charkov21f47fb2010-12-23 13:11:21 +010079
Tony Prisk0c464d52012-10-10 20:59:32 +130080/* Global variable for accessing io-mem addresses */
81static struct vt8500_irq_data intc[VT8500_INTC_MAX];
82static u32 active_cnt = 0;
83
Wolfram Sang2eb5af42011-06-28 09:53:20 +010084static void vt8500_irq_mask(struct irq_data *d)
Alexey Charkov21f47fb2010-12-23 13:11:21 +010085{
Tony Prisk0c464d52012-10-10 20:59:32 +130086 struct vt8500_irq_data *priv = d->domain->host_data;
Tony Priske9a91de2012-08-03 21:00:06 +120087 void __iomem *base = priv->base;
Tony Prisk0c464d52012-10-10 20:59:32 +130088 void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
89 u8 edge, dctr;
90 u32 status;
Alexey Charkov21f47fb2010-12-23 13:11:21 +010091
Tony Priske9a91de2012-08-03 21:00:06 +120092 edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
Alexey Charkov21f47fb2010-12-23 13:11:21 +010093 if (edge) {
Tony Prisk0c464d52012-10-10 20:59:32 +130094 status = readl(stat_reg);
Alexey Charkov21f47fb2010-12-23 13:11:21 +010095
Tony Priske9a91de2012-08-03 21:00:06 +120096 status |= (1 << (d->hwirq & 0x1f));
Alexey Charkov21f47fb2010-12-23 13:11:21 +010097 writel(status, stat_reg);
98 } else {
Tony Prisk0c464d52012-10-10 20:59:32 +130099 dctr = readb(base + VT8500_ICDC + d->hwirq);
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100100 dctr &= ~VT8500_INT_ENABLE;
Tony Priske9a91de2012-08-03 21:00:06 +1200101 writeb(dctr, base + VT8500_ICDC + d->hwirq);
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100102 }
103}
104
Wolfram Sang2eb5af42011-06-28 09:53:20 +0100105static void vt8500_irq_unmask(struct irq_data *d)
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100106{
Tony Prisk0c464d52012-10-10 20:59:32 +1300107 struct vt8500_irq_data *priv = d->domain->host_data;
Tony Priske9a91de2012-08-03 21:00:06 +1200108 void __iomem *base = priv->base;
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100109 u8 dctr;
110
Tony Priske9a91de2012-08-03 21:00:06 +1200111 dctr = readb(base + VT8500_ICDC + d->hwirq);
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100112 dctr |= VT8500_INT_ENABLE;
Tony Priske9a91de2012-08-03 21:00:06 +1200113 writeb(dctr, base + VT8500_ICDC + d->hwirq);
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100114}
115
Wolfram Sang2eb5af42011-06-28 09:53:20 +0100116static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100117{
Tony Prisk0c464d52012-10-10 20:59:32 +1300118 struct vt8500_irq_data *priv = d->domain->host_data;
Tony Priske9a91de2012-08-03 21:00:06 +1200119 void __iomem *base = priv->base;
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100120 u8 dctr;
121
Tony Priske9a91de2012-08-03 21:00:06 +1200122 dctr = readb(base + VT8500_ICDC + d->hwirq);
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100123 dctr &= ~VT8500_EDGE;
124
125 switch (flow_type) {
126 case IRQF_TRIGGER_LOW:
127 return -EINVAL;
128 case IRQF_TRIGGER_HIGH:
129 dctr |= VT8500_TRIGGER_HIGH;
Tony Priske9a91de2012-08-03 21:00:06 +1200130 __irq_set_handler_locked(d->irq, handle_level_irq);
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100131 break;
132 case IRQF_TRIGGER_FALLING:
133 dctr |= VT8500_TRIGGER_FALLING;
Tony Priske9a91de2012-08-03 21:00:06 +1200134 __irq_set_handler_locked(d->irq, handle_edge_irq);
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100135 break;
136 case IRQF_TRIGGER_RISING:
137 dctr |= VT8500_TRIGGER_RISING;
Tony Priske9a91de2012-08-03 21:00:06 +1200138 __irq_set_handler_locked(d->irq, handle_edge_irq);
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100139 break;
140 }
Tony Priske9a91de2012-08-03 21:00:06 +1200141 writeb(dctr, base + VT8500_ICDC + d->hwirq);
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100142
143 return 0;
144}
145
146static struct irq_chip vt8500_irq_chip = {
Wolfram Sang2eb5af42011-06-28 09:53:20 +0100147 .name = "vt8500",
148 .irq_ack = vt8500_irq_mask,
149 .irq_mask = vt8500_irq_mask,
150 .irq_unmask = vt8500_irq_unmask,
151 .irq_set_type = vt8500_irq_set_type,
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100152};
153
Tony Priske9a91de2012-08-03 21:00:06 +1200154static void __init vt8500_init_irq_hw(void __iomem *base)
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100155{
Tony Prisk0c464d52012-10-10 20:59:32 +1300156 u32 i;
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100157
Tony Priske9a91de2012-08-03 21:00:06 +1200158 /* Enable rotating priority for IRQ */
159 writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
160 writel(0x00, base + VT8500_ICPC_FIQ);
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100161
Tony Prisk0c464d52012-10-10 20:59:32 +1300162 /* Disable all interrupts and route them to IRQ */
163 for (i = 0; i < 64; i++)
164 writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100165}
166
Tony Priske9a91de2012-08-03 21:00:06 +1200167static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
168 irq_hw_number_t hw)
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100169{
Tony Priske9a91de2012-08-03 21:00:06 +1200170 irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
171 set_irq_flags(virq, IRQF_VALID);
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100172
Tony Priske9a91de2012-08-03 21:00:06 +1200173 return 0;
Alexey Charkov21f47fb2010-12-23 13:11:21 +0100174}
Tony Priske9a91de2012-08-03 21:00:06 +1200175
176static struct irq_domain_ops vt8500_irq_domain_ops = {
177 .map = vt8500_irq_map,
178 .xlate = irq_domain_xlate_onecell,
179};
180
Stephen Boyd8783dd32014-03-04 16:40:30 -0800181static void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
Tony Prisk0c464d52012-10-10 20:59:32 +1300182{
183 u32 stat, i;
184 int irqnr, virq;
185 void __iomem *base;
186
187 /* Loop through each active controller */
188 for (i=0; i<active_cnt; i++) {
189 base = intc[i].base;
190 irqnr = readl_relaxed(base) & 0x3F;
191 /*
192 Highest Priority register default = 63, so check that this
193 is a real interrupt by checking the status register
194 */
195 if (irqnr == 63) {
196 stat = readl_relaxed(base + VT8500_ICIS + 4);
197 if (!(stat & BIT(31)))
198 continue;
199 }
200
201 virq = irq_find_mapping(intc[i].domain, irqnr);
202 handle_IRQ(virq, regs);
203 }
204}
205
Axel Line6587182013-07-05 11:33:49 +0800206static int __init vt8500_irq_init(struct device_node *node,
207 struct device_node *parent)
Tony Priske9a91de2012-08-03 21:00:06 +1200208{
Tony Priske9a91de2012-08-03 21:00:06 +1200209 int irq, i;
210 struct device_node *np = node;
211
Tony Prisk0c464d52012-10-10 20:59:32 +1300212 if (active_cnt == VT8500_INTC_MAX) {
213 pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
214 __func__);
215 goto out;
216 }
Tony Priske9a91de2012-08-03 21:00:06 +1200217
Tony Prisk0c464d52012-10-10 20:59:32 +1300218 intc[active_cnt].base = of_iomap(np, 0);
219 intc[active_cnt].domain = irq_domain_add_linear(node, 64,
220 &vt8500_irq_domain_ops, &intc[active_cnt]);
Tony Priske9a91de2012-08-03 21:00:06 +1200221
Tony Prisk0c464d52012-10-10 20:59:32 +1300222 if (!intc[active_cnt].base) {
223 pr_err("%s: Unable to map IO memory\n", __func__);
224 goto out;
225 }
Tony Priske9a91de2012-08-03 21:00:06 +1200226
Tony Prisk0c464d52012-10-10 20:59:32 +1300227 if (!intc[active_cnt].domain) {
228 pr_err("%s: Unable to add irq domain!\n", __func__);
229 goto out;
230 }
Tony Priske9a91de2012-08-03 21:00:06 +1200231
Tony Prisk06ff14c2013-03-24 01:12:25 +0000232 set_handle_irq(vt8500_handle_irq);
233
Tony Prisk0c464d52012-10-10 20:59:32 +1300234 vt8500_init_irq_hw(intc[active_cnt].base);
235
236 pr_info("vt8500-irq: Added interrupt controller\n");
237
238 active_cnt++;
Tony Priske9a91de2012-08-03 21:00:06 +1200239
240 /* check if this is a slaved controller */
241 if (of_irq_count(np) != 0) {
242 /* check that we have the correct number of interrupts */
243 if (of_irq_count(np) != 8) {
Tony Prisk0c464d52012-10-10 20:59:32 +1300244 pr_err("%s: Incorrect IRQ map for slaved controller\n",
Tony Priske9a91de2012-08-03 21:00:06 +1200245 __func__);
246 return -EINVAL;
247 }
248
249 for (i = 0; i < 8; i++) {
250 irq = irq_of_parse_and_map(np, i);
251 enable_irq(irq);
252 }
253
254 pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
255 }
Tony Prisk0c464d52012-10-10 20:59:32 +1300256out:
Tony Priske9a91de2012-08-03 21:00:06 +1200257 return 0;
258}
259
Tony Prisk06ff14c2013-03-24 01:12:25 +0000260IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init);