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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/arm/mach-pxa/time.c
3 *
Bill Gatliff7bbb18c2007-07-21 03:39:36 +01004 * PXA clocksource, clockevents, and OST interrupt handlers.
5 * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
6 *
7 * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
8 * by MontaVista Software, Inc. (Nico, your code rocks!)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/kernel.h>
16#include <linux/init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/interrupt.h>
Robert Jarzmikab5354c2014-07-14 18:52:02 +020018#include <linux/clk.h>
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010019#include <linux/clockchips.h>
Robert Jarzmikab5354c2014-07-14 18:52:02 +020020#include <linux/of_address.h>
21#include <linux/of_irq.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070022#include <linux/sched_clock.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010024#include <asm/div64.h>
Robert Jarzmikab5354c2014-07-14 18:52:02 +020025
26#define OSMR0 0x00 /* OS Timer 0 Match Register */
27#define OSMR1 0x04 /* OS Timer 1 Match Register */
28#define OSMR2 0x08 /* OS Timer 2 Match Register */
29#define OSMR3 0x0C /* OS Timer 3 Match Register */
30
31#define OSCR 0x10 /* OS Timer Counter Register */
32#define OSSR 0x14 /* OS Timer Status Register */
33#define OWER 0x18 /* OS Timer Watchdog Enable Register */
34#define OIER 0x1C /* OS Timer Interrupt Enable Register */
35
36#define OSSR_M3 (1 << 3) /* Match status channel 3 */
37#define OSSR_M2 (1 << 2) /* Match status channel 2 */
38#define OSSR_M1 (1 << 1) /* Match status channel 1 */
39#define OSSR_M0 (1 << 0) /* Match status channel 0 */
40
41#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070042
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010043/*
44 * This is PXA's sched_clock implementation. This has a resolution
45 * of at least 308 ns and a maximum value of 208 days.
46 *
47 * The return value is guaranteed to be monotonic in that range as
48 * long as there is always less than 582 seconds between successive
49 * calls to sched_clock() which should always be the case in practice.
50 */
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010051
Robert Jarzmikab5354c2014-07-14 18:52:02 +020052#define timer_readl(reg) readl_relaxed(timer_base + (reg))
53#define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg))
54
55static void __iomem *timer_base;
56
Stephen Boyd364ed1e2013-11-15 15:26:19 -080057static u64 notrace pxa_read_sched_clock(void)
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010058{
Robert Jarzmikab5354c2014-07-14 18:52:02 +020059 return timer_readl(OSCR);
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010060}
61
62
Russell Kinga88264c2007-11-12 22:45:16 +000063#define MIN_OSCR_DELTA 16
64
Linus Torvalds1da177e2005-04-16 15:20:36 -070065static irqreturn_t
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010066pxa_ost0_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -070067{
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010068 struct clock_event_device *c = dev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -070069
Russell Kinga88264c2007-11-12 22:45:16 +000070 /* Disarm the compare/match, signal the event. */
Robert Jarzmikab5354c2014-07-14 18:52:02 +020071 timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
72 timer_writel(OSSR_M0, OSSR);
Russell Kinga88264c2007-11-12 22:45:16 +000073 c->event_handler(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75 return IRQ_HANDLED;
76}
77
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010078static int
79pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
80{
Uwe Kleine-Königa602f0f2009-12-17 12:43:29 +010081 unsigned long next, oscr;
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010082
Robert Jarzmikab5354c2014-07-14 18:52:02 +020083 timer_writel(timer_readl(OIER) | OIER_E0, OIER);
84 next = timer_readl(OSCR) + delta;
85 timer_writel(next, OSMR0);
86 oscr = timer_readl(OSCR);
Russell King91bc51d2007-11-08 23:35:46 +000087
88 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010089}
90
91static void
92pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
93{
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010094 switch (mode) {
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010095 case CLOCK_EVT_MODE_ONESHOT:
Robert Jarzmikab5354c2014-07-14 18:52:02 +020096 timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
97 timer_writel(OSSR_M0, OSSR);
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010098 break;
99
100 case CLOCK_EVT_MODE_UNUSED:
101 case CLOCK_EVT_MODE_SHUTDOWN:
102 /* initializing, released, or preparing for suspend */
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200103 timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
104 timer_writel(OSSR_M0, OSSR);
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100105 break;
Russell Kingdf433092007-10-27 15:15:49 +0100106
107 case CLOCK_EVT_MODE_RESUME:
Russell Kinga88264c2007-11-12 22:45:16 +0000108 case CLOCK_EVT_MODE_PERIODIC:
Russell Kingdf433092007-10-27 15:15:49 +0100109 break;
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100110 }
111}
112
Stephen Warren5b30d5b2012-11-07 16:34:13 -0700113#ifdef CONFIG_PM
114static unsigned long osmr[4], oier, oscr;
115
116static void pxa_timer_suspend(struct clock_event_device *cedev)
117{
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200118 osmr[0] = timer_readl(OSMR0);
119 osmr[1] = timer_readl(OSMR1);
120 osmr[2] = timer_readl(OSMR2);
121 osmr[3] = timer_readl(OSMR3);
122 oier = timer_readl(OIER);
123 oscr = timer_readl(OSCR);
Stephen Warren5b30d5b2012-11-07 16:34:13 -0700124}
125
126static void pxa_timer_resume(struct clock_event_device *cedev)
127{
128 /*
129 * Ensure that we have at least MIN_OSCR_DELTA between match
130 * register 0 and the OSCR, to guarantee that we will receive
131 * the one-shot timer interrupt. We adjust OSMR0 in preference
132 * to OSCR to guarantee that OSCR is monotonically incrementing.
133 */
134 if (osmr[0] - oscr < MIN_OSCR_DELTA)
135 osmr[0] += MIN_OSCR_DELTA;
136
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200137 timer_writel(osmr[0], OSMR0);
138 timer_writel(osmr[1], OSMR1);
139 timer_writel(osmr[2], OSMR2);
140 timer_writel(osmr[3], OSMR3);
141 timer_writel(oier, OIER);
142 timer_writel(oscr, OSCR);
Stephen Warren5b30d5b2012-11-07 16:34:13 -0700143}
144#else
145#define pxa_timer_suspend NULL
146#define pxa_timer_resume NULL
147#endif
148
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100149static struct clock_event_device ckevt_pxa_osmr0 = {
150 .name = "osmr0",
Russell Kinga88264c2007-11-12 22:45:16 +0000151 .features = CLOCK_EVT_FEAT_ONESHOT,
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100152 .rating = 200,
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100153 .set_next_event = pxa_osmr0_set_next_event,
154 .set_mode = pxa_osmr0_set_mode,
Stephen Warren5b30d5b2012-11-07 16:34:13 -0700155 .suspend = pxa_timer_suspend,
156 .resume = pxa_timer_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157};
158
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100159static struct irqaction pxa_ost0_irq = {
160 .name = "ost0",
Michael Opdenackered7936f2013-12-09 11:22:22 +0100161 .flags = IRQF_TIMER | IRQF_IRQPOLL,
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100162 .handler = pxa_ost0_interrupt,
163 .dev_id = &ckevt_pxa_osmr0,
164};
165
Robert Jarzmik6f2116e2015-01-31 23:40:40 +0100166static void __init pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167{
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200168 timer_writel(0, OIER);
169 timer_writel(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170
Stephen Boyd364ed1e2013-11-15 15:26:19 -0800171 sched_clock_register(pxa_read_sched_clock, 32, clock_tick_rate);
Nicolas Pitre6c3a1582007-08-17 16:55:22 +0100172
Rusty Russell320ab2b2008-12-13 21:20:26 +1030173 ckevt_pxa_osmr0.cpumask = cpumask_of(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200175 setup_irq(irq, &pxa_ost0_irq);
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100176
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200177 clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200,
178 32, clocksource_mmio_readl_up);
Olof Johansson8d849812013-01-14 10:20:02 -0800179 clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200180 MIN_OSCR_DELTA * 2, 0x7fffffff);
181}
182
183static void __init pxa_timer_dt_init(struct device_node *np)
184{
185 struct clk *clk;
186 int irq;
187
188 /* timer registers are shared with watchdog timer */
189 timer_base = of_iomap(np, 0);
190 if (!timer_base)
191 panic("%s: unable to map resource\n", np->name);
192
193 clk = of_clk_get(np, 0);
194 if (IS_ERR(clk)) {
195 pr_crit("%s: unable to get clk\n", np->name);
196 return;
197 }
198 clk_prepare_enable(clk);
199
200 /* we are only interested in OS-timer0 irq */
201 irq = irq_of_parse_and_map(np, 0);
202 if (irq <= 0) {
203 pr_crit("%s: unable to parse OS-timer0 irq\n", np->name);
204 return;
205 }
206
207 pxa_timer_common_init(irq, clk_get_rate(clk));
208}
209CLOCKSOURCE_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init);
210
211/*
212 * Legacy timer init for non device-tree boards.
213 */
214void __init pxa_timer_nodt_init(int irq, void __iomem *base,
215 unsigned long clock_tick_rate)
216{
217 struct clk *clk;
218
219 timer_base = base;
220 clk = clk_get(NULL, "OSTIMER0");
221 if (clk && !IS_ERR(clk))
222 clk_prepare_enable(clk);
223 else
224 pr_crit("%s: unable to get clk\n", __func__);
225
226 pxa_timer_common_init(irq, clock_tick_rate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227}