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Maxime Ripard67905542013-11-07 12:01:48 +01001/*
2 * Allwinner SoCs hstimer driver.
3 *
4 * Copyright (C) 2013 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/clk.h>
14#include <linux/clockchips.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/irqreturn.h>
Maxime Riparde50a00b2014-04-17 11:06:45 +020019#include <linux/reset.h>
Maxime Ripard67905542013-11-07 12:01:48 +010020#include <linux/sched_clock.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24
25#define TIMER_IRQ_EN_REG 0x00
26#define TIMER_IRQ_EN(val) BIT(val)
27#define TIMER_IRQ_ST_REG 0x04
28#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
29#define TIMER_CTL_ENABLE BIT(0)
30#define TIMER_CTL_RELOAD BIT(1)
31#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
32#define TIMER_CTL_ONESHOT BIT(7)
33#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
34#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
35#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
36#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
37
38#define TIMER_SYNC_TICKS 3
39
40static void __iomem *timer_base;
41static u32 ticks_per_jiffy;
42
43/*
44 * When we disable a timer, we need to wait at least for 2 cycles of
45 * the timer source clock. We will use for that the clocksource timer
46 * that is already setup and runs at the same frequency than the other
47 * timers, and we never will be disabled.
48 */
49static void sun5i_clkevt_sync(void)
50{
51 u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1));
52
53 while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
54 cpu_relax();
55}
56
57static void sun5i_clkevt_time_stop(u8 timer)
58{
59 u32 val = readl(timer_base + TIMER_CTL_REG(timer));
60 writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
61
62 sun5i_clkevt_sync();
63}
64
65static void sun5i_clkevt_time_setup(u8 timer, u32 delay)
66{
67 writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
68}
69
70static void sun5i_clkevt_time_start(u8 timer, bool periodic)
71{
72 u32 val = readl(timer_base + TIMER_CTL_REG(timer));
73
74 if (periodic)
75 val &= ~TIMER_CTL_ONESHOT;
76 else
77 val |= TIMER_CTL_ONESHOT;
78
79 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
80 timer_base + TIMER_CTL_REG(timer));
81}
82
83static void sun5i_clkevt_mode(enum clock_event_mode mode,
84 struct clock_event_device *clk)
85{
86 switch (mode) {
87 case CLOCK_EVT_MODE_PERIODIC:
88 sun5i_clkevt_time_stop(0);
89 sun5i_clkevt_time_setup(0, ticks_per_jiffy);
90 sun5i_clkevt_time_start(0, true);
91 break;
92 case CLOCK_EVT_MODE_ONESHOT:
93 sun5i_clkevt_time_stop(0);
94 sun5i_clkevt_time_start(0, false);
95 break;
96 case CLOCK_EVT_MODE_UNUSED:
97 case CLOCK_EVT_MODE_SHUTDOWN:
98 default:
99 sun5i_clkevt_time_stop(0);
100 break;
101 }
102}
103
104static int sun5i_clkevt_next_event(unsigned long evt,
105 struct clock_event_device *unused)
106{
107 sun5i_clkevt_time_stop(0);
108 sun5i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
109 sun5i_clkevt_time_start(0, false);
110
111 return 0;
112}
113
114static struct clock_event_device sun5i_clockevent = {
115 .name = "sun5i_tick",
116 .rating = 340,
117 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
118 .set_mode = sun5i_clkevt_mode,
119 .set_next_event = sun5i_clkevt_next_event,
120};
121
122
123static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
124{
125 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
126
127 writel(0x1, timer_base + TIMER_IRQ_ST_REG);
128 evt->event_handler(evt);
129
130 return IRQ_HANDLED;
131}
132
133static struct irqaction sun5i_timer_irq = {
134 .name = "sun5i_timer0",
135 .flags = IRQF_TIMER | IRQF_IRQPOLL,
136 .handler = sun5i_timer_interrupt,
137 .dev_id = &sun5i_clockevent,
138};
139
Stephen Boyd00e2bcd2014-01-16 17:38:06 -0800140static u64 sun5i_timer_sched_read(void)
Maxime Ripard67905542013-11-07 12:01:48 +0100141{
142 return ~readl(timer_base + TIMER_CNTVAL_LO_REG(1));
143}
144
145static void __init sun5i_timer_init(struct device_node *node)
146{
Maxime Riparde50a00b2014-04-17 11:06:45 +0200147 struct reset_control *rstc;
Maxime Ripard67905542013-11-07 12:01:48 +0100148 unsigned long rate;
149 struct clk *clk;
150 int ret, irq;
151 u32 val;
152
153 timer_base = of_iomap(node, 0);
154 if (!timer_base)
155 panic("Can't map registers");
156
157 irq = irq_of_parse_and_map(node, 0);
158 if (irq <= 0)
159 panic("Can't parse IRQ");
160
161 clk = of_clk_get(node, 0);
162 if (IS_ERR(clk))
163 panic("Can't get timer clock");
164 clk_prepare_enable(clk);
165 rate = clk_get_rate(clk);
166
Maxime Riparde50a00b2014-04-17 11:06:45 +0200167 rstc = of_reset_control_get(node, NULL);
168 if (!IS_ERR(rstc))
169 reset_control_deassert(rstc);
170
Maxime Ripard67905542013-11-07 12:01:48 +0100171 writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
172 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
173 timer_base + TIMER_CTL_REG(1));
174
Stephen Boyd00e2bcd2014-01-16 17:38:06 -0800175 sched_clock_register(sun5i_timer_sched_read, 32, rate);
Maxime Ripard67905542013-11-07 12:01:48 +0100176 clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name,
177 rate, 340, 32, clocksource_mmio_readl_down);
178
179 ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
180
181 ret = setup_irq(irq, &sun5i_timer_irq);
182 if (ret)
183 pr_warn("failed to setup irq %d\n", irq);
184
185 /* Enable timer0 interrupt */
186 val = readl(timer_base + TIMER_IRQ_EN_REG);
187 writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
188
189 sun5i_clockevent.cpumask = cpu_possible_mask;
190 sun5i_clockevent.irq = irq;
191
192 clockevents_config_and_register(&sun5i_clockevent, rate,
193 TIMER_SYNC_TICKS, 0xffffffff);
194}
195CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
196 sun5i_timer_init);
197CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
198 sun5i_timer_init);