Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* linux/drivers/mtd/nand/s3c2410.c |
| 2 | * |
Ben Dooks | 7e74a50 | 2008-05-20 17:32:27 +0100 | [diff] [blame] | 3 | * Copyright © 2004-2008 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ |
Ben Dooks | fdf2fd5 | 2005-02-18 14:46:15 +0000 | [diff] [blame] | 5 | * Ben Dooks <ben@simtec.co.uk> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
Ben Dooks | 7e74a50 | 2008-05-20 17:32:27 +0100 | [diff] [blame] | 7 | * Samsung S3C2410/S3C2440/S3C2412 NAND driver |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | */ |
| 23 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG |
| 25 | #define DEBUG |
| 26 | #endif |
| 27 | |
| 28 | #include <linux/module.h> |
| 29 | #include <linux/types.h> |
| 30 | #include <linux/init.h> |
| 31 | #include <linux/kernel.h> |
| 32 | #include <linux/string.h> |
| 33 | #include <linux/ioport.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 34 | #include <linux/platform_device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #include <linux/delay.h> |
| 36 | #include <linux/err.h> |
Tim Schmielau | 4e57b68 | 2005-10-30 15:03:48 -0800 | [diff] [blame] | 37 | #include <linux/slab.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 38 | #include <linux/clk.h> |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 39 | #include <linux/cpufreq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | |
| 41 | #include <linux/mtd/mtd.h> |
| 42 | #include <linux/mtd/nand.h> |
| 43 | #include <linux/mtd/nand_ecc.h> |
| 44 | #include <linux/mtd/partitions.h> |
| 45 | |
| 46 | #include <asm/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | |
Ben Dooks | 7926b5a | 2008-10-30 10:14:35 +0000 | [diff] [blame] | 48 | #include <plat/regs-nand.h> |
| 49 | #include <plat/nand.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
| 52 | static int hardware_ecc = 1; |
| 53 | #else |
| 54 | static int hardware_ecc = 0; |
| 55 | #endif |
| 56 | |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 57 | #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP |
| 58 | static int clock_stop = 1; |
| 59 | #else |
| 60 | static const int clock_stop = 0; |
| 61 | #endif |
| 62 | |
| 63 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | /* new oob placement block for use with hardware ecc generation |
| 65 | */ |
| 66 | |
Thomas Gleixner | 5bd34c0 | 2006-05-27 22:16:10 +0200 | [diff] [blame] | 67 | static struct nand_ecclayout nand_hw_eccoob = { |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 68 | .eccbytes = 3, |
| 69 | .eccpos = {0, 1, 2}, |
| 70 | .oobfree = {{8, 8}} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | /* controller and mtd information */ |
| 74 | |
| 75 | struct s3c2410_nand_info; |
| 76 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame^] | 77 | /** |
| 78 | * struct s3c2410_nand_mtd - driver MTD structure |
| 79 | * @mtd: The MTD instance to pass to the MTD layer. |
| 80 | * @chip: The NAND chip information. |
| 81 | * @set: The platform information supplied for this set of NAND chips. |
| 82 | * @info: Link back to the hardware information. |
| 83 | * @scan_res: The result from calling nand_scan_ident(). |
| 84 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | struct s3c2410_nand_mtd { |
| 86 | struct mtd_info mtd; |
| 87 | struct nand_chip chip; |
| 88 | struct s3c2410_nand_set *set; |
| 89 | struct s3c2410_nand_info *info; |
| 90 | int scan_res; |
| 91 | }; |
| 92 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 93 | enum s3c_cpu_type { |
| 94 | TYPE_S3C2410, |
| 95 | TYPE_S3C2412, |
| 96 | TYPE_S3C2440, |
| 97 | }; |
| 98 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 99 | /* overview of the s3c2410 nand state */ |
| 100 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame^] | 101 | /** |
| 102 | * struct s3c2410_nand_info - NAND controller state. |
| 103 | * @mtds: An array of MTD instances on this controoler. |
| 104 | * @platform: The platform data for this board. |
| 105 | * @device: The platform device we bound to. |
| 106 | * @area: The IO area resource that came from request_mem_region(). |
| 107 | * @clk: The clock resource for this controller. |
| 108 | * @regs: The area mapped for the hardware registers described by @area. |
| 109 | * @sel_reg: Pointer to the register controlling the NAND selection. |
| 110 | * @sel_bit: The bit in @sel_reg to select the NAND chip. |
| 111 | * @mtd_count: The number of MTDs created from this controller. |
| 112 | * @save_sel: The contents of @sel_reg to be saved over suspend. |
| 113 | * @clk_rate: The clock rate from @clk. |
| 114 | * @cpu_type: The exact type of this controller. |
| 115 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | struct s3c2410_nand_info { |
| 117 | /* mtd info */ |
| 118 | struct nand_hw_control controller; |
| 119 | struct s3c2410_nand_mtd *mtds; |
| 120 | struct s3c2410_platform_nand *platform; |
| 121 | |
| 122 | /* device info */ |
| 123 | struct device *device; |
| 124 | struct resource *area; |
| 125 | struct clk *clk; |
Ben Dooks | fdf2fd5 | 2005-02-18 14:46:15 +0000 | [diff] [blame] | 126 | void __iomem *regs; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 127 | void __iomem *sel_reg; |
| 128 | int sel_bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | int mtd_count; |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 130 | unsigned long save_sel; |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 131 | unsigned long clk_rate; |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 132 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 133 | enum s3c_cpu_type cpu_type; |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 134 | |
| 135 | #ifdef CONFIG_CPU_FREQ |
| 136 | struct notifier_block freq_transition; |
| 137 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 138 | }; |
| 139 | |
| 140 | /* conversion functions */ |
| 141 | |
| 142 | static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) |
| 143 | { |
| 144 | return container_of(mtd, struct s3c2410_nand_mtd, mtd); |
| 145 | } |
| 146 | |
| 147 | static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) |
| 148 | { |
| 149 | return s3c2410_nand_mtd_toours(mtd)->info; |
| 150 | } |
| 151 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 152 | static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 154 | return platform_get_drvdata(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | } |
| 156 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 157 | static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 159 | return dev->dev.platform_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | } |
| 161 | |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 162 | static inline int allow_clk_stop(struct s3c2410_nand_info *info) |
| 163 | { |
| 164 | return clock_stop; |
| 165 | } |
| 166 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | /* timing calculations */ |
| 168 | |
Ben Dooks | cfd320f | 2005-10-20 22:22:58 +0100 | [diff] [blame] | 169 | #define NS_IN_KHZ 1000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame^] | 171 | /** |
| 172 | * s3c_nand_calc_rate - calculate timing data. |
| 173 | * @wanted: The cycle time in nanoseconds. |
| 174 | * @clk: The clock rate in kHz. |
| 175 | * @max: The maximum divider value. |
| 176 | * |
| 177 | * Calculate the timing value from the given parameters. |
| 178 | */ |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 179 | static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | { |
| 181 | int result; |
| 182 | |
Ben Dooks | cfd320f | 2005-10-20 22:22:58 +0100 | [diff] [blame] | 183 | result = (wanted * clk) / NS_IN_KHZ; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 184 | result++; |
| 185 | |
| 186 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); |
| 187 | |
| 188 | if (result > max) { |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 189 | printk("%d ns is too big for current clock rate %ld\n", wanted, clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 190 | return -1; |
| 191 | } |
| 192 | |
| 193 | if (result < 1) |
| 194 | result = 1; |
| 195 | |
| 196 | return result; |
| 197 | } |
| 198 | |
Ben Dooks | cfd320f | 2005-10-20 22:22:58 +0100 | [diff] [blame] | 199 | #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | |
| 201 | /* controller setup */ |
| 202 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame^] | 203 | /** |
| 204 | * s3c2410_nand_setrate - setup controller timing information. |
| 205 | * @info: The controller instance. |
| 206 | * |
| 207 | * Given the information supplied by the platform, calculate and set |
| 208 | * the necessary timing registers in the hardware to generate the |
| 209 | * necessary timing cycles to the hardware. |
| 210 | */ |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 211 | static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | { |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 213 | struct s3c2410_platform_nand *plat = info->platform; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 214 | int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; |
Ben Dooks | cfd320f | 2005-10-20 22:22:58 +0100 | [diff] [blame] | 215 | int tacls, twrph0, twrph1; |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 216 | unsigned long clkrate = clk_get_rate(info->clk); |
| 217 | unsigned long set, cfg, mask; |
| 218 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | |
| 220 | /* calculate the timing information for the controller */ |
| 221 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 222 | info->clk_rate = clkrate; |
Ben Dooks | cfd320f | 2005-10-20 22:22:58 +0100 | [diff] [blame] | 223 | clkrate /= 1000; /* turn clock into kHz for ease of use */ |
| 224 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 225 | if (plat != NULL) { |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 226 | tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); |
| 227 | twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); |
| 228 | twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | } else { |
| 230 | /* default timings */ |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 231 | tacls = tacls_max; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 232 | twrph0 = 8; |
| 233 | twrph1 = 8; |
| 234 | } |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 235 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { |
Ben Dooks | 99974c6 | 2006-06-21 15:43:05 +0100 | [diff] [blame] | 237 | dev_err(info->device, "cannot get suitable timings\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | return -EINVAL; |
| 239 | } |
| 240 | |
Ben Dooks | 99974c6 | 2006-06-21 15:43:05 +0100 | [diff] [blame] | 241 | dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 242 | tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 244 | switch (info->cpu_type) { |
| 245 | case TYPE_S3C2410: |
| 246 | mask = (S3C2410_NFCONF_TACLS(3) | |
| 247 | S3C2410_NFCONF_TWRPH0(7) | |
| 248 | S3C2410_NFCONF_TWRPH1(7)); |
| 249 | set = S3C2410_NFCONF_EN; |
| 250 | set |= S3C2410_NFCONF_TACLS(tacls - 1); |
| 251 | set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); |
| 252 | set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); |
| 253 | break; |
| 254 | |
| 255 | case TYPE_S3C2440: |
| 256 | case TYPE_S3C2412: |
| 257 | mask = (S3C2410_NFCONF_TACLS(tacls_max - 1) | |
| 258 | S3C2410_NFCONF_TWRPH0(7) | |
| 259 | S3C2410_NFCONF_TWRPH1(7)); |
| 260 | |
| 261 | set = S3C2440_NFCONF_TACLS(tacls - 1); |
| 262 | set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); |
| 263 | set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); |
| 264 | break; |
| 265 | |
| 266 | default: |
| 267 | /* keep compiler happy */ |
| 268 | mask = 0; |
| 269 | set = 0; |
| 270 | BUG(); |
| 271 | } |
| 272 | |
| 273 | dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); |
| 274 | |
| 275 | local_irq_save(flags); |
| 276 | |
| 277 | cfg = readl(info->regs + S3C2410_NFCONF); |
| 278 | cfg &= ~mask; |
| 279 | cfg |= set; |
| 280 | writel(cfg, info->regs + S3C2410_NFCONF); |
| 281 | |
| 282 | local_irq_restore(flags); |
| 283 | |
| 284 | return 0; |
| 285 | } |
| 286 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame^] | 287 | /** |
| 288 | * s3c2410_nand_inithw - basic hardware initialisation |
| 289 | * @info: The hardware state. |
| 290 | * |
| 291 | * Do the basic initialisation of the hardware, using s3c2410_nand_setrate() |
| 292 | * to setup the hardware access speeds and set the controller to be enabled. |
| 293 | */ |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 294 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) |
| 295 | { |
| 296 | int ret; |
| 297 | |
| 298 | ret = s3c2410_nand_setrate(info); |
| 299 | if (ret < 0) |
| 300 | return ret; |
| 301 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 302 | switch (info->cpu_type) { |
| 303 | case TYPE_S3C2410: |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 304 | default: |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 305 | break; |
| 306 | |
| 307 | case TYPE_S3C2440: |
| 308 | case TYPE_S3C2412: |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 309 | /* enable the controller and de-assert nFCE */ |
| 310 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 311 | writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 312 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 313 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 314 | return 0; |
| 315 | } |
| 316 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame^] | 317 | /** |
| 318 | * s3c2410_nand_select_chip - select the given nand chip |
| 319 | * @mtd: The MTD instance for this chip. |
| 320 | * @chip: The chip number. |
| 321 | * |
| 322 | * This is called by the MTD layer to either select a given chip for the |
| 323 | * @mtd instance, or to indicate that the access has finished and the |
| 324 | * chip can be de-selected. |
| 325 | * |
| 326 | * The routine ensures that the nFCE line is correctly setup, and any |
| 327 | * platform specific selection code is called to route nFCE to the specific |
| 328 | * chip. |
| 329 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 330 | static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) |
| 331 | { |
| 332 | struct s3c2410_nand_info *info; |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 333 | struct s3c2410_nand_mtd *nmtd; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | struct nand_chip *this = mtd->priv; |
| 335 | unsigned long cur; |
| 336 | |
| 337 | nmtd = this->priv; |
| 338 | info = nmtd->info; |
| 339 | |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 340 | if (chip != -1 && allow_clk_stop(info)) |
| 341 | clk_enable(info->clk); |
| 342 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 343 | cur = readl(info->sel_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 344 | |
| 345 | if (chip == -1) { |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 346 | cur |= info->sel_bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 347 | } else { |
Ben Dooks | fb8d82a | 2005-07-06 21:05:10 +0100 | [diff] [blame] | 348 | if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { |
Ben Dooks | 99974c6 | 2006-06-21 15:43:05 +0100 | [diff] [blame] | 349 | dev_err(info->device, "invalid chip %d\n", chip); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 350 | return; |
| 351 | } |
| 352 | |
| 353 | if (info->platform != NULL) { |
| 354 | if (info->platform->select_chip != NULL) |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 355 | (info->platform->select_chip) (nmtd->set, chip); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | } |
| 357 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 358 | cur &= ~info->sel_bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 359 | } |
| 360 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 361 | writel(cur, info->sel_reg); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 362 | |
| 363 | if (chip == -1 && allow_clk_stop(info)) |
| 364 | clk_disable(info->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 365 | } |
| 366 | |
Ben Dooks | ad3b5fb | 2006-06-19 09:43:23 +0100 | [diff] [blame] | 367 | /* s3c2410_nand_hwcontrol |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 368 | * |
Ben Dooks | ad3b5fb | 2006-06-19 09:43:23 +0100 | [diff] [blame] | 369 | * Issue command and address cycles to the chip |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 370 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 371 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 372 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
David Woodhouse | f906887 | 2006-06-10 00:53:16 +0100 | [diff] [blame] | 373 | unsigned int ctrl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | { |
| 375 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
David Woodhouse | c9ac597 | 2006-11-30 08:17:38 +0000 | [diff] [blame] | 376 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 377 | if (cmd == NAND_CMD_NONE) |
| 378 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 379 | |
David Woodhouse | f906887 | 2006-06-10 00:53:16 +0100 | [diff] [blame] | 380 | if (ctrl & NAND_CLE) |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 381 | writeb(cmd, info->regs + S3C2410_NFCMD); |
| 382 | else |
| 383 | writeb(cmd, info->regs + S3C2410_NFADDR); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | /* command and control functions */ |
| 387 | |
David Woodhouse | f906887 | 2006-06-10 00:53:16 +0100 | [diff] [blame] | 388 | static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
| 389 | unsigned int ctrl) |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 390 | { |
| 391 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 392 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 393 | if (cmd == NAND_CMD_NONE) |
| 394 | return; |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 395 | |
David Woodhouse | f906887 | 2006-06-10 00:53:16 +0100 | [diff] [blame] | 396 | if (ctrl & NAND_CLE) |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 397 | writeb(cmd, info->regs + S3C2440_NFCMD); |
| 398 | else |
| 399 | writeb(cmd, info->regs + S3C2440_NFADDR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 400 | } |
| 401 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 402 | /* s3c2410_nand_devready() |
| 403 | * |
| 404 | * returns 0 if the nand is busy, 1 if it is ready |
| 405 | */ |
| 406 | |
| 407 | static int s3c2410_nand_devready(struct mtd_info *mtd) |
| 408 | { |
| 409 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 410 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; |
| 411 | } |
| 412 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 413 | static int s3c2440_nand_devready(struct mtd_info *mtd) |
| 414 | { |
| 415 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 416 | return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; |
| 417 | } |
| 418 | |
| 419 | static int s3c2412_nand_devready(struct mtd_info *mtd) |
| 420 | { |
| 421 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 422 | return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; |
| 423 | } |
| 424 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 425 | /* ECC handling functions */ |
| 426 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 427 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, |
| 428 | u_char *read_ecc, u_char *calc_ecc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | { |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 430 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 431 | unsigned int diff0, diff1, diff2; |
| 432 | unsigned int bit, byte; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 433 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 434 | pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 436 | diff0 = read_ecc[0] ^ calc_ecc[0]; |
| 437 | diff1 = read_ecc[1] ^ calc_ecc[1]; |
| 438 | diff2 = read_ecc[2] ^ calc_ecc[2]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 439 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 440 | pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n", |
| 441 | __func__, |
| 442 | read_ecc[0], read_ecc[1], read_ecc[2], |
| 443 | calc_ecc[0], calc_ecc[1], calc_ecc[2], |
| 444 | diff0, diff1, diff2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 445 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 446 | if (diff0 == 0 && diff1 == 0 && diff2 == 0) |
| 447 | return 0; /* ECC is ok */ |
| 448 | |
Ben Dooks | c45c6c6 | 2008-04-15 11:36:20 +0100 | [diff] [blame] | 449 | /* sometimes people do not think about using the ECC, so check |
| 450 | * to see if we have an 0xff,0xff,0xff read ECC and then ignore |
| 451 | * the error, on the assumption that this is an un-eccd page. |
| 452 | */ |
| 453 | if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff |
| 454 | && info->platform->ignore_unset_ecc) |
| 455 | return 0; |
| 456 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 457 | /* Can we correct this ECC (ie, one row and column change). |
| 458 | * Note, this is similar to the 256 error code on smartmedia */ |
| 459 | |
| 460 | if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && |
| 461 | ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && |
| 462 | ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { |
| 463 | /* calculate the bit position of the error */ |
| 464 | |
Matt Reimer | d0bf379 | 2007-10-18 18:02:43 -0700 | [diff] [blame] | 465 | bit = ((diff2 >> 3) & 1) | |
| 466 | ((diff2 >> 4) & 2) | |
| 467 | ((diff2 >> 5) & 4); |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 468 | |
| 469 | /* calculate the byte position of the error */ |
| 470 | |
Matt Reimer | d0bf379 | 2007-10-18 18:02:43 -0700 | [diff] [blame] | 471 | byte = ((diff2 << 7) & 0x100) | |
| 472 | ((diff1 << 0) & 0x80) | |
| 473 | ((diff1 << 1) & 0x40) | |
| 474 | ((diff1 << 2) & 0x20) | |
| 475 | ((diff1 << 3) & 0x10) | |
| 476 | ((diff0 >> 4) & 0x08) | |
| 477 | ((diff0 >> 3) & 0x04) | |
| 478 | ((diff0 >> 2) & 0x02) | |
| 479 | ((diff0 >> 1) & 0x01); |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 480 | |
| 481 | dev_dbg(info->device, "correcting error bit %d, byte %d\n", |
| 482 | bit, byte); |
| 483 | |
| 484 | dat[byte] ^= (1 << bit); |
| 485 | return 1; |
| 486 | } |
| 487 | |
| 488 | /* if there is only one bit difference in the ECC, then |
| 489 | * one of only a row or column parity has changed, which |
| 490 | * means the error is most probably in the ECC itself */ |
| 491 | |
| 492 | diff0 |= (diff1 << 8); |
| 493 | diff0 |= (diff2 << 16); |
| 494 | |
| 495 | if ((diff0 & ~(1<<fls(diff0))) == 0) |
| 496 | return 1; |
| 497 | |
Matt Reimer | 4fac9f6 | 2007-10-18 18:02:44 -0700 | [diff] [blame] | 498 | return -1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 499 | } |
| 500 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 501 | /* ECC functions |
| 502 | * |
| 503 | * These allow the s3c2410 and s3c2440 to use the controller's ECC |
| 504 | * generator block to ECC the data as it passes through] |
| 505 | */ |
| 506 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 507 | static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
| 508 | { |
| 509 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 510 | unsigned long ctrl; |
| 511 | |
| 512 | ctrl = readl(info->regs + S3C2410_NFCONF); |
| 513 | ctrl |= S3C2410_NFCONF_INITECC; |
| 514 | writel(ctrl, info->regs + S3C2410_NFCONF); |
| 515 | } |
| 516 | |
Matthieu CASTET | 4f65992 | 2007-02-13 12:30:38 +0100 | [diff] [blame] | 517 | static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
| 518 | { |
| 519 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 520 | unsigned long ctrl; |
| 521 | |
| 522 | ctrl = readl(info->regs + S3C2440_NFCONT); |
| 523 | writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT); |
| 524 | } |
| 525 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 526 | static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
| 527 | { |
| 528 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 529 | unsigned long ctrl; |
| 530 | |
| 531 | ctrl = readl(info->regs + S3C2440_NFCONT); |
| 532 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); |
| 533 | } |
| 534 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 535 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 536 | { |
| 537 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 538 | |
| 539 | ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); |
| 540 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); |
| 541 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); |
| 542 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 543 | pr_debug("%s: returning ecc %02x%02x%02x\n", __func__, |
| 544 | ecc_code[0], ecc_code[1], ecc_code[2]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 545 | |
| 546 | return 0; |
| 547 | } |
| 548 | |
Matthieu CASTET | 4f65992 | 2007-02-13 12:30:38 +0100 | [diff] [blame] | 549 | static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
| 550 | { |
| 551 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 552 | unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); |
| 553 | |
| 554 | ecc_code[0] = ecc; |
| 555 | ecc_code[1] = ecc >> 8; |
| 556 | ecc_code[2] = ecc >> 16; |
| 557 | |
| 558 | pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); |
| 559 | |
| 560 | return 0; |
| 561 | } |
| 562 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 563 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 564 | { |
| 565 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 566 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); |
| 567 | |
| 568 | ecc_code[0] = ecc; |
| 569 | ecc_code[1] = ecc >> 8; |
| 570 | ecc_code[2] = ecc >> 16; |
| 571 | |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 572 | pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 573 | |
| 574 | return 0; |
| 575 | } |
| 576 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 577 | /* over-ride the standard functions for a little more speed. We can |
| 578 | * use read/write block to move the data buffers to/from the controller |
| 579 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 580 | |
| 581 | static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
| 582 | { |
| 583 | struct nand_chip *this = mtd->priv; |
| 584 | readsb(this->IO_ADDR_R, buf, len); |
| 585 | } |
| 586 | |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 587 | static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
| 588 | { |
| 589 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 590 | readsl(info->regs + S3C2440_NFDATA, buf, len / 4); |
| 591 | } |
| 592 | |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 593 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 594 | { |
| 595 | struct nand_chip *this = mtd->priv; |
| 596 | writesb(this->IO_ADDR_W, buf, len); |
| 597 | } |
| 598 | |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 599 | static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
| 600 | { |
| 601 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 602 | writesl(info->regs + S3C2440_NFDATA, buf, len / 4); |
| 603 | } |
| 604 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 605 | /* cpufreq driver support */ |
| 606 | |
| 607 | #ifdef CONFIG_CPU_FREQ |
| 608 | |
| 609 | static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb, |
| 610 | unsigned long val, void *data) |
| 611 | { |
| 612 | struct s3c2410_nand_info *info; |
| 613 | unsigned long newclk; |
| 614 | |
| 615 | info = container_of(nb, struct s3c2410_nand_info, freq_transition); |
| 616 | newclk = clk_get_rate(info->clk); |
| 617 | |
| 618 | if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) || |
| 619 | (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) { |
| 620 | s3c2410_nand_setrate(info); |
| 621 | } |
| 622 | |
| 623 | return 0; |
| 624 | } |
| 625 | |
| 626 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) |
| 627 | { |
| 628 | info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition; |
| 629 | |
| 630 | return cpufreq_register_notifier(&info->freq_transition, |
| 631 | CPUFREQ_TRANSITION_NOTIFIER); |
| 632 | } |
| 633 | |
| 634 | static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) |
| 635 | { |
| 636 | cpufreq_unregister_notifier(&info->freq_transition, |
| 637 | CPUFREQ_TRANSITION_NOTIFIER); |
| 638 | } |
| 639 | |
| 640 | #else |
| 641 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) |
| 642 | { |
| 643 | return 0; |
| 644 | } |
| 645 | |
| 646 | static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) |
| 647 | { |
| 648 | } |
| 649 | #endif |
| 650 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 651 | /* device management functions */ |
| 652 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 653 | static int s3c24xx_nand_remove(struct platform_device *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 654 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 655 | struct s3c2410_nand_info *info = to_nand_info(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 656 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 657 | platform_set_drvdata(pdev, NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 658 | |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 659 | if (info == NULL) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 660 | return 0; |
| 661 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 662 | s3c2410_nand_cpufreq_deregister(info); |
| 663 | |
| 664 | /* Release all our mtds and their partitions, then go through |
| 665 | * freeing the resources used |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 666 | */ |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 667 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 668 | if (info->mtds != NULL) { |
| 669 | struct s3c2410_nand_mtd *ptr = info->mtds; |
| 670 | int mtdno; |
| 671 | |
| 672 | for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { |
| 673 | pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); |
| 674 | nand_release(&ptr->mtd); |
| 675 | } |
| 676 | |
| 677 | kfree(info->mtds); |
| 678 | } |
| 679 | |
| 680 | /* free the common resources */ |
| 681 | |
| 682 | if (info->clk != NULL && !IS_ERR(info->clk)) { |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 683 | if (!allow_clk_stop(info)) |
| 684 | clk_disable(info->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 685 | clk_put(info->clk); |
| 686 | } |
| 687 | |
| 688 | if (info->regs != NULL) { |
| 689 | iounmap(info->regs); |
| 690 | info->regs = NULL; |
| 691 | } |
| 692 | |
| 693 | if (info->area != NULL) { |
| 694 | release_resource(info->area); |
| 695 | kfree(info->area); |
| 696 | info->area = NULL; |
| 697 | } |
| 698 | |
| 699 | kfree(info); |
| 700 | |
| 701 | return 0; |
| 702 | } |
| 703 | |
| 704 | #ifdef CONFIG_MTD_PARTITIONS |
| 705 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, |
| 706 | struct s3c2410_nand_mtd *mtd, |
| 707 | struct s3c2410_nand_set *set) |
| 708 | { |
| 709 | if (set == NULL) |
| 710 | return add_mtd_device(&mtd->mtd); |
| 711 | |
| 712 | if (set->nr_partitions > 0 && set->partitions != NULL) { |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 713 | return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 714 | } |
| 715 | |
| 716 | return add_mtd_device(&mtd->mtd); |
| 717 | } |
| 718 | #else |
| 719 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, |
| 720 | struct s3c2410_nand_mtd *mtd, |
| 721 | struct s3c2410_nand_set *set) |
| 722 | { |
| 723 | return add_mtd_device(&mtd->mtd); |
| 724 | } |
| 725 | #endif |
| 726 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame^] | 727 | /** |
| 728 | * s3c2410_nand_init_chip - initialise a single instance of an chip |
| 729 | * @info: The base NAND controller the chip is on. |
| 730 | * @nmtd: The new controller MTD instance to fill in. |
| 731 | * @set: The information passed from the board specific platform data. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 732 | * |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame^] | 733 | * Initialise the given @nmtd from the information in @info and @set. This |
| 734 | * readies the structure for use with the MTD layer functions by ensuring |
| 735 | * all pointers are setup and the necessary control routines selected. |
| 736 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 737 | static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, |
| 738 | struct s3c2410_nand_mtd *nmtd, |
| 739 | struct s3c2410_nand_set *set) |
| 740 | { |
| 741 | struct nand_chip *chip = &nmtd->chip; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 742 | void __iomem *regs = info->regs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 743 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 744 | chip->write_buf = s3c2410_nand_write_buf; |
| 745 | chip->read_buf = s3c2410_nand_read_buf; |
| 746 | chip->select_chip = s3c2410_nand_select_chip; |
| 747 | chip->chip_delay = 50; |
| 748 | chip->priv = nmtd; |
| 749 | chip->options = 0; |
| 750 | chip->controller = &info->controller; |
| 751 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 752 | switch (info->cpu_type) { |
| 753 | case TYPE_S3C2410: |
| 754 | chip->IO_ADDR_W = regs + S3C2410_NFDATA; |
| 755 | info->sel_reg = regs + S3C2410_NFCONF; |
| 756 | info->sel_bit = S3C2410_NFCONF_nFCE; |
| 757 | chip->cmd_ctrl = s3c2410_nand_hwcontrol; |
| 758 | chip->dev_ready = s3c2410_nand_devready; |
| 759 | break; |
| 760 | |
| 761 | case TYPE_S3C2440: |
| 762 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; |
| 763 | info->sel_reg = regs + S3C2440_NFCONT; |
| 764 | info->sel_bit = S3C2440_NFCONT_nFCE; |
| 765 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; |
| 766 | chip->dev_ready = s3c2440_nand_devready; |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 767 | chip->read_buf = s3c2440_nand_read_buf; |
| 768 | chip->write_buf = s3c2440_nand_write_buf; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 769 | break; |
| 770 | |
| 771 | case TYPE_S3C2412: |
| 772 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; |
| 773 | info->sel_reg = regs + S3C2440_NFCONT; |
| 774 | info->sel_bit = S3C2412_NFCONT_nFCE0; |
| 775 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; |
| 776 | chip->dev_ready = s3c2412_nand_devready; |
| 777 | |
| 778 | if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) |
| 779 | dev_info(info->device, "System booted from NAND\n"); |
| 780 | |
| 781 | break; |
| 782 | } |
| 783 | |
| 784 | chip->IO_ADDR_R = chip->IO_ADDR_W; |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 785 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 786 | nmtd->info = info; |
| 787 | nmtd->mtd.priv = chip; |
David Woodhouse | 552d920 | 2006-05-14 01:20:46 +0100 | [diff] [blame] | 788 | nmtd->mtd.owner = THIS_MODULE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 789 | nmtd->set = set; |
| 790 | |
| 791 | if (hardware_ecc) { |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 792 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 793 | chip->ecc.correct = s3c2410_nand_correct_data; |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 794 | chip->ecc.mode = NAND_ECC_HW; |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 795 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 796 | switch (info->cpu_type) { |
| 797 | case TYPE_S3C2410: |
| 798 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; |
| 799 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
| 800 | break; |
| 801 | |
| 802 | case TYPE_S3C2412: |
Matthieu CASTET | 4f65992 | 2007-02-13 12:30:38 +0100 | [diff] [blame] | 803 | chip->ecc.hwctl = s3c2412_nand_enable_hwecc; |
| 804 | chip->ecc.calculate = s3c2412_nand_calculate_ecc; |
| 805 | break; |
| 806 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 807 | case TYPE_S3C2440: |
| 808 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; |
| 809 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; |
| 810 | break; |
| 811 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 812 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 813 | } else { |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 814 | chip->ecc.mode = NAND_ECC_SOFT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 815 | } |
Ben Dooks | 1c21ab6 | 2008-04-15 11:36:21 +0100 | [diff] [blame] | 816 | |
| 817 | if (set->ecc_layout != NULL) |
| 818 | chip->ecc.layout = set->ecc_layout; |
Ben Dooks | 37e5ffa | 2008-04-15 11:36:22 +0100 | [diff] [blame] | 819 | |
| 820 | if (set->disable_ecc) |
| 821 | chip->ecc.mode = NAND_ECC_NONE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 822 | } |
| 823 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame^] | 824 | /** |
| 825 | * s3c2410_nand_update_chip - post probe update |
| 826 | * @info: The controller instance. |
| 827 | * @nmtd: The driver version of the MTD instance. |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 828 | * |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame^] | 829 | * This routine is called after the chip probe has succesfully completed |
| 830 | * and the relevant per-chip information updated. This call ensure that |
| 831 | * we update the internal state accordingly. |
| 832 | * |
| 833 | * The internal state is currently limited to the ECC state information. |
| 834 | */ |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 835 | static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info, |
| 836 | struct s3c2410_nand_mtd *nmtd) |
| 837 | { |
| 838 | struct nand_chip *chip = &nmtd->chip; |
| 839 | |
Ben Dooks | 451d339 | 2008-05-20 17:32:14 +0100 | [diff] [blame] | 840 | dev_dbg(info->device, "chip %p => page shift %d\n", |
| 841 | chip, chip->page_shift); |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 842 | |
| 843 | if (hardware_ecc) { |
| 844 | /* change the behaviour depending on wether we are using |
| 845 | * the large or small page nand device */ |
| 846 | |
| 847 | if (chip->page_shift > 10) { |
| 848 | chip->ecc.size = 256; |
| 849 | chip->ecc.bytes = 3; |
| 850 | } else { |
| 851 | chip->ecc.size = 512; |
| 852 | chip->ecc.bytes = 3; |
| 853 | chip->ecc.layout = &nand_hw_eccoob; |
| 854 | } |
| 855 | } |
| 856 | } |
| 857 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 858 | /* s3c24xx_nand_probe |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 859 | * |
| 860 | * called by device layer when it finds a device matching |
| 861 | * one our driver can handled. This code checks to see if |
| 862 | * it can allocate all necessary resources then calls the |
| 863 | * nand layer to look for devices |
| 864 | */ |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 865 | static int s3c24xx_nand_probe(struct platform_device *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 866 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 867 | struct s3c2410_platform_nand *plat = to_nand_plat(pdev); |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 868 | enum s3c_cpu_type cpu_type; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 869 | struct s3c2410_nand_info *info; |
| 870 | struct s3c2410_nand_mtd *nmtd; |
| 871 | struct s3c2410_nand_set *sets; |
| 872 | struct resource *res; |
| 873 | int err = 0; |
| 874 | int size; |
| 875 | int nr_sets; |
| 876 | int setno; |
| 877 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 878 | cpu_type = platform_get_device_id(pdev)->driver_data; |
| 879 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 880 | pr_debug("s3c2410_nand_probe(%p)\n", pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 881 | |
| 882 | info = kmalloc(sizeof(*info), GFP_KERNEL); |
| 883 | if (info == NULL) { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 884 | dev_err(&pdev->dev, "no memory for flash info\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 885 | err = -ENOMEM; |
| 886 | goto exit_error; |
| 887 | } |
| 888 | |
Russell King | 59f0cb0 | 2008-10-27 11:24:09 +0000 | [diff] [blame] | 889 | memset(info, 0, sizeof(*info)); |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 890 | platform_set_drvdata(pdev, info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 891 | |
| 892 | spin_lock_init(&info->controller.lock); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 893 | init_waitqueue_head(&info->controller.wq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 894 | |
| 895 | /* get the clock source and enable it */ |
| 896 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 897 | info->clk = clk_get(&pdev->dev, "nand"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 898 | if (IS_ERR(info->clk)) { |
Joe Perches | 898eb71 | 2007-10-18 03:06:30 -0700 | [diff] [blame] | 899 | dev_err(&pdev->dev, "failed to get clock\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 900 | err = -ENOENT; |
| 901 | goto exit_error; |
| 902 | } |
| 903 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 904 | clk_enable(info->clk); |
| 905 | |
| 906 | /* allocate and map the resource */ |
| 907 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 908 | /* currently we assume we have the one resource */ |
| 909 | res = pdev->resource; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 910 | size = res->end - res->start + 1; |
| 911 | |
| 912 | info->area = request_mem_region(res->start, size, pdev->name); |
| 913 | |
| 914 | if (info->area == NULL) { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 915 | dev_err(&pdev->dev, "cannot reserve register region\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 916 | err = -ENOENT; |
| 917 | goto exit_error; |
| 918 | } |
| 919 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 920 | info->device = &pdev->dev; |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 921 | info->platform = plat; |
| 922 | info->regs = ioremap(res->start, size); |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 923 | info->cpu_type = cpu_type; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | |
| 925 | if (info->regs == NULL) { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 926 | dev_err(&pdev->dev, "cannot reserve register region\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 927 | err = -EIO; |
| 928 | goto exit_error; |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 929 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 930 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 931 | dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 932 | |
| 933 | /* initialise the hardware */ |
| 934 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 935 | err = s3c2410_nand_inithw(info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 936 | if (err != 0) |
| 937 | goto exit_error; |
| 938 | |
| 939 | sets = (plat != NULL) ? plat->sets : NULL; |
| 940 | nr_sets = (plat != NULL) ? plat->nr_sets : 1; |
| 941 | |
| 942 | info->mtd_count = nr_sets; |
| 943 | |
| 944 | /* allocate our information */ |
| 945 | |
| 946 | size = nr_sets * sizeof(*info->mtds); |
| 947 | info->mtds = kmalloc(size, GFP_KERNEL); |
| 948 | if (info->mtds == NULL) { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 949 | dev_err(&pdev->dev, "failed to allocate mtd storage\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 950 | err = -ENOMEM; |
| 951 | goto exit_error; |
| 952 | } |
| 953 | |
Russell King | 59f0cb0 | 2008-10-27 11:24:09 +0000 | [diff] [blame] | 954 | memset(info->mtds, 0, size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 955 | |
| 956 | /* initialise all possible chips */ |
| 957 | |
| 958 | nmtd = info->mtds; |
| 959 | |
| 960 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 961 | pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info); |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 962 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 963 | s3c2410_nand_init_chip(info, nmtd, sets); |
| 964 | |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 965 | nmtd->scan_res = nand_scan_ident(&nmtd->mtd, |
| 966 | (sets) ? sets->nr_chips : 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 967 | |
| 968 | if (nmtd->scan_res == 0) { |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 969 | s3c2410_nand_update_chip(info, nmtd); |
| 970 | nand_scan_tail(&nmtd->mtd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 971 | s3c2410_nand_add_partition(info, nmtd, sets); |
| 972 | } |
| 973 | |
| 974 | if (sets != NULL) |
| 975 | sets++; |
| 976 | } |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 977 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 978 | err = s3c2410_nand_cpufreq_register(info); |
| 979 | if (err < 0) { |
| 980 | dev_err(&pdev->dev, "failed to init cpufreq support\n"); |
| 981 | goto exit_error; |
| 982 | } |
| 983 | |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 984 | if (allow_clk_stop(info)) { |
| 985 | dev_info(&pdev->dev, "clock idle support enabled\n"); |
| 986 | clk_disable(info->clk); |
| 987 | } |
| 988 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 989 | pr_debug("initialised ok\n"); |
| 990 | return 0; |
| 991 | |
| 992 | exit_error: |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 993 | s3c24xx_nand_remove(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 994 | |
| 995 | if (err == 0) |
| 996 | err = -EINVAL; |
| 997 | return err; |
| 998 | } |
| 999 | |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1000 | /* PM Support */ |
| 1001 | #ifdef CONFIG_PM |
| 1002 | |
| 1003 | static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) |
| 1004 | { |
| 1005 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); |
| 1006 | |
| 1007 | if (info) { |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 1008 | info->save_sel = readl(info->sel_reg); |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 1009 | |
| 1010 | /* For the moment, we must ensure nFCE is high during |
| 1011 | * the time we are suspended. This really should be |
| 1012 | * handled by suspending the MTDs we are using, but |
| 1013 | * that is currently not the case. */ |
| 1014 | |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 1015 | writel(info->save_sel | info->sel_bit, info->sel_reg); |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 1016 | |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1017 | if (!allow_clk_stop(info)) |
| 1018 | clk_disable(info->clk); |
| 1019 | } |
| 1020 | |
| 1021 | return 0; |
| 1022 | } |
| 1023 | |
| 1024 | static int s3c24xx_nand_resume(struct platform_device *dev) |
| 1025 | { |
| 1026 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 1027 | unsigned long sel; |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1028 | |
| 1029 | if (info) { |
| 1030 | clk_enable(info->clk); |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 1031 | s3c2410_nand_inithw(info); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1032 | |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 1033 | /* Restore the state of the nFCE line. */ |
| 1034 | |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 1035 | sel = readl(info->sel_reg); |
| 1036 | sel &= ~info->sel_bit; |
| 1037 | sel |= info->save_sel & info->sel_bit; |
| 1038 | writel(sel, info->sel_reg); |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 1039 | |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1040 | if (allow_clk_stop(info)) |
| 1041 | clk_disable(info->clk); |
| 1042 | } |
| 1043 | |
| 1044 | return 0; |
| 1045 | } |
| 1046 | |
| 1047 | #else |
| 1048 | #define s3c24xx_nand_suspend NULL |
| 1049 | #define s3c24xx_nand_resume NULL |
| 1050 | #endif |
| 1051 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 1052 | /* driver device registration */ |
| 1053 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1054 | static struct platform_device_id s3c24xx_driver_ids[] = { |
| 1055 | { |
| 1056 | .name = "s3c2410-nand", |
| 1057 | .driver_data = TYPE_S3C2410, |
| 1058 | }, { |
| 1059 | .name = "s3c2440-nand", |
| 1060 | .driver_data = TYPE_S3C2440, |
| 1061 | }, { |
| 1062 | .name = "s3c2412-nand", |
| 1063 | .driver_data = TYPE_S3C2412, |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 1064 | }, |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1065 | { } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1066 | }; |
| 1067 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1068 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 1069 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1070 | static struct platform_driver s3c24xx_nand_driver = { |
| 1071 | .probe = s3c24xx_nand_probe, |
| 1072 | .remove = s3c24xx_nand_remove, |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 1073 | .suspend = s3c24xx_nand_suspend, |
| 1074 | .resume = s3c24xx_nand_resume, |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1075 | .id_table = s3c24xx_driver_ids, |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 1076 | .driver = { |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1077 | .name = "s3c24xx-nand", |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 1078 | .owner = THIS_MODULE, |
| 1079 | }, |
| 1080 | }; |
| 1081 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1082 | static int __init s3c2410_nand_init(void) |
| 1083 | { |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 1084 | printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n"); |
| 1085 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1086 | return platform_driver_register(&s3c24xx_nand_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1087 | } |
| 1088 | |
| 1089 | static void __exit s3c2410_nand_exit(void) |
| 1090 | { |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1091 | platform_driver_unregister(&s3c24xx_nand_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1092 | } |
| 1093 | |
| 1094 | module_init(s3c2410_nand_init); |
| 1095 | module_exit(s3c2410_nand_exit); |
| 1096 | |
| 1097 | MODULE_LICENSE("GPL"); |
| 1098 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 1099 | MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); |