blob: 4762c91cb587f03c19eddd58abef2ea449a2e941 [file] [log] [blame]
Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
Ben Hutchings906bb262009-11-29 15:16:19 +00004 * Copyright 2005-2009 Solarflare Communications Inc.
Ben Hutchings8ceee662008-04-27 12:55:59 +01005 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11/* Common definitions for all Efx net driver code */
12
13#ifndef EFX_NET_DRIVER_H
14#define EFX_NET_DRIVER_H
15
16#include <linux/version.h>
17#include <linux/netdevice.h>
18#include <linux/etherdevice.h>
19#include <linux/ethtool.h>
20#include <linux/if_vlan.h>
Ben Hutchings68e7f452009-04-29 08:05:08 +000021#include <linux/mdio.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010022#include <linux/list.h>
23#include <linux/pci.h>
24#include <linux/device.h>
25#include <linux/highmem.h>
26#include <linux/workqueue.h>
Ben Hutchings37b5a602008-05-30 22:27:04 +010027#include <linux/i2c.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010028
29#include "enum.h"
30#include "bitfield.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010031
Ben Hutchings8ceee662008-04-27 12:55:59 +010032/**************************************************************************
33 *
34 * Build definitions
35 *
36 **************************************************************************/
37#ifndef EFX_DRIVER_NAME
38#define EFX_DRIVER_NAME "sfc"
39#endif
Ben Hutchings906bb262009-11-29 15:16:19 +000040#define EFX_DRIVER_VERSION "3.0"
Ben Hutchings8ceee662008-04-27 12:55:59 +010041
42#ifdef EFX_ENABLE_DEBUG
43#define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
44#define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
45#else
46#define EFX_BUG_ON_PARANOID(x) do {} while (0)
47#define EFX_WARN_ON_PARANOID(x) do {} while (0)
48#endif
49
Ben Hutchings8ceee662008-04-27 12:55:59 +010050/* Un-rate-limited logging */
51#define EFX_ERR(efx, fmt, args...) \
Ben Hutchings55668612008-05-16 21:16:10 +010052dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args)
Ben Hutchings8ceee662008-04-27 12:55:59 +010053
54#define EFX_INFO(efx, fmt, args...) \
Ben Hutchings55668612008-05-16 21:16:10 +010055dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args)
Ben Hutchings8ceee662008-04-27 12:55:59 +010056
57#ifdef EFX_ENABLE_DEBUG
58#define EFX_LOG(efx, fmt, args...) \
Ben Hutchings55668612008-05-16 21:16:10 +010059dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
Ben Hutchings8ceee662008-04-27 12:55:59 +010060#else
61#define EFX_LOG(efx, fmt, args...) \
Ben Hutchings55668612008-05-16 21:16:10 +010062dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
Ben Hutchings8ceee662008-04-27 12:55:59 +010063#endif
64
65#define EFX_TRACE(efx, fmt, args...) do {} while (0)
66
67#define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
68
69/* Rate-limited logging */
70#define EFX_ERR_RL(efx, fmt, args...) \
71do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
72
73#define EFX_INFO_RL(efx, fmt, args...) \
74do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
75
76#define EFX_LOG_RL(efx, fmt, args...) \
77do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
78
Ben Hutchings8ceee662008-04-27 12:55:59 +010079/**************************************************************************
80 *
81 * Efx data structures
82 *
83 **************************************************************************/
84
85#define EFX_MAX_CHANNELS 32
Ben Hutchings8ceee662008-04-27 12:55:59 +010086#define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
87
Ben Hutchingsa4900ac2010-04-28 09:30:43 +000088/* Checksum generation is a per-queue option in hardware, so each
89 * queue visible to the networking core is backed by two hardware TX
90 * queues. */
91#define EFX_MAX_CORE_TX_QUEUES EFX_MAX_CHANNELS
92#define EFX_TXQ_TYPE_OFFLOAD 1
93#define EFX_TXQ_TYPES 2
94#define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CORE_TX_QUEUES)
Ben Hutchings60ac1062008-09-01 12:44:59 +010095
Ben Hutchings8ceee662008-04-27 12:55:59 +010096/**
97 * struct efx_special_buffer - An Efx special buffer
98 * @addr: CPU base address of the buffer
99 * @dma_addr: DMA base address of the buffer
100 * @len: Buffer length, in bytes
101 * @index: Buffer index within controller;s buffer table
102 * @entries: Number of buffer table entries
103 *
104 * Special buffers are used for the event queues and the TX and RX
105 * descriptor queues for each channel. They are *not* used for the
106 * actual transmit and receive buffers.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100107 */
108struct efx_special_buffer {
109 void *addr;
110 dma_addr_t dma_addr;
111 unsigned int len;
112 int index;
113 int entries;
114};
115
Ben Hutchings127e6e12009-11-25 16:09:55 +0000116enum efx_flush_state {
117 FLUSH_NONE,
118 FLUSH_PENDING,
119 FLUSH_FAILED,
120 FLUSH_DONE,
121};
122
Ben Hutchings8ceee662008-04-27 12:55:59 +0100123/**
124 * struct efx_tx_buffer - An Efx TX buffer
125 * @skb: The associated socket buffer.
126 * Set only on the final fragment of a packet; %NULL for all other
127 * fragments. When this fragment completes, then we can free this
128 * skb.
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100129 * @tsoh: The associated TSO header structure, or %NULL if this
130 * buffer is not a TSO header.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100131 * @dma_addr: DMA address of the fragment.
132 * @len: Length of this fragment.
133 * This field is zero when the queue slot is empty.
134 * @continuation: True if this fragment is not the end of a packet.
135 * @unmap_single: True if pci_unmap_single should be used.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100136 * @unmap_len: Length of this fragment to unmap
137 */
138struct efx_tx_buffer {
139 const struct sk_buff *skb;
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100140 struct efx_tso_header *tsoh;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100141 dma_addr_t dma_addr;
142 unsigned short len;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100143 bool continuation;
144 bool unmap_single;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100145 unsigned short unmap_len;
146};
147
148/**
149 * struct efx_tx_queue - An Efx TX queue
150 *
151 * This is a ring buffer of TX fragments.
152 * Since the TX completion path always executes on the same
153 * CPU and the xmit path can operate on different CPUs,
154 * performance is increased by ensuring that the completion
155 * path and the xmit path operate on different cache lines.
156 * This is particularly important if the xmit path is always
157 * executing on one CPU which is different from the completion
158 * path. There is also a cache line for members which are
159 * read but not written on the fast path.
160 *
161 * @efx: The associated Efx NIC
162 * @queue: DMA queue number
Ben Hutchings8ceee662008-04-27 12:55:59 +0100163 * @channel: The associated channel
164 * @buffer: The software buffer ring
165 * @txd: The hardware descriptor ring
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100166 * @flushed: Used when handling queue flushing
Ben Hutchings8ceee662008-04-27 12:55:59 +0100167 * @read_count: Current read pointer.
168 * This is the number of buffers that have been removed from both rings.
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100169 * @stopped: Stopped count.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100170 * Set if this TX queue is currently stopping its port.
171 * @insert_count: Current insert pointer
172 * This is the number of buffers that have been added to the
173 * software ring.
174 * @write_count: Current write pointer
175 * This is the number of buffers that have been added to the
176 * hardware ring.
177 * @old_read_count: The value of read_count when last checked.
178 * This is here for performance reasons. The xmit path will
179 * only get the up-to-date value of read_count if this
180 * variable indicates that the queue is full. This is to
181 * avoid cache-line ping-pong between the xmit path and the
182 * completion path.
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100183 * @tso_headers_free: A list of TSO headers allocated for this TX queue
184 * that are not in use, and so available for new TSO sends. The list
185 * is protected by the TX queue lock.
186 * @tso_bursts: Number of times TSO xmit invoked by kernel
187 * @tso_long_headers: Number of packets with headers too long for standard
188 * blocks
189 * @tso_packets: Number of packets via the TSO xmit path
Ben Hutchings8ceee662008-04-27 12:55:59 +0100190 */
191struct efx_tx_queue {
192 /* Members which don't change on the fast path */
193 struct efx_nic *efx ____cacheline_aligned_in_smp;
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000194 unsigned queue;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100195 struct efx_channel *channel;
196 struct efx_nic *nic;
197 struct efx_tx_buffer *buffer;
198 struct efx_special_buffer txd;
Ben Hutchings127e6e12009-11-25 16:09:55 +0000199 enum efx_flush_state flushed;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100200
201 /* Members used mainly on the completion path */
202 unsigned int read_count ____cacheline_aligned_in_smp;
203 int stopped;
204
205 /* Members used only on the xmit path */
206 unsigned int insert_count ____cacheline_aligned_in_smp;
207 unsigned int write_count;
208 unsigned int old_read_count;
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100209 struct efx_tso_header *tso_headers_free;
210 unsigned int tso_bursts;
211 unsigned int tso_long_headers;
212 unsigned int tso_packets;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100213};
214
215/**
216 * struct efx_rx_buffer - An Efx RX data buffer
217 * @dma_addr: DMA base address of the buffer
218 * @skb: The associated socket buffer, if any.
219 * If both this and page are %NULL, the buffer slot is currently free.
220 * @page: The associated page buffer, if any.
221 * If both this and skb are %NULL, the buffer slot is currently free.
222 * @data: Pointer to ethernet header
223 * @len: Buffer length, in bytes.
224 * @unmap_addr: DMA address to unmap
225 */
226struct efx_rx_buffer {
227 dma_addr_t dma_addr;
228 struct sk_buff *skb;
229 struct page *page;
230 char *data;
231 unsigned int len;
232 dma_addr_t unmap_addr;
233};
234
235/**
236 * struct efx_rx_queue - An Efx RX queue
237 * @efx: The associated Efx NIC
238 * @queue: DMA queue number
Ben Hutchings8ceee662008-04-27 12:55:59 +0100239 * @channel: The associated channel
240 * @buffer: The software buffer ring
241 * @rxd: The hardware descriptor ring
242 * @added_count: Number of buffers added to the receive queue.
243 * @notified_count: Number of buffers given to NIC (<= @added_count).
244 * @removed_count: Number of buffers removed from the receive queue.
245 * @add_lock: Receive queue descriptor add spin lock.
246 * This lock must be held in order to add buffers to the RX
247 * descriptor ring (rxd and buffer) and to update added_count (but
248 * not removed_count).
249 * @max_fill: RX descriptor maximum fill level (<= ring size)
250 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
251 * (<= @max_fill)
252 * @fast_fill_limit: The level to which a fast fill will fill
253 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
254 * @min_fill: RX descriptor minimum non-zero fill level.
255 * This records the minimum fill level observed when a ring
256 * refill was triggered.
257 * @min_overfill: RX descriptor minimum overflow fill level.
258 * This records the minimum fill level at which RX queue
259 * overflow was observed. It should never be set.
260 * @alloc_page_count: RX allocation strategy counter.
261 * @alloc_skb_count: RX allocation strategy counter.
262 * @work: Descriptor push work thread
263 * @buf_page: Page for next RX buffer.
264 * We can use a single page for multiple RX buffers. This tracks
265 * the remaining space in the allocation.
266 * @buf_dma_addr: Page's DMA address.
267 * @buf_data: Page's host address.
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100268 * @flushed: Use when handling queue flushing
Ben Hutchings8ceee662008-04-27 12:55:59 +0100269 */
270struct efx_rx_queue {
271 struct efx_nic *efx;
272 int queue;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100273 struct efx_channel *channel;
274 struct efx_rx_buffer *buffer;
275 struct efx_special_buffer rxd;
276
277 int added_count;
278 int notified_count;
279 int removed_count;
280 spinlock_t add_lock;
281 unsigned int max_fill;
282 unsigned int fast_fill_trigger;
283 unsigned int fast_fill_limit;
284 unsigned int min_fill;
285 unsigned int min_overfill;
286 unsigned int alloc_page_count;
287 unsigned int alloc_skb_count;
288 struct delayed_work work;
289 unsigned int slow_fill_count;
290
291 struct page *buf_page;
292 dma_addr_t buf_dma_addr;
293 char *buf_data;
Ben Hutchings127e6e12009-11-25 16:09:55 +0000294 enum efx_flush_state flushed;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100295};
296
297/**
298 * struct efx_buffer - An Efx general-purpose buffer
299 * @addr: host base address of the buffer
300 * @dma_addr: DMA base address of the buffer
301 * @len: Buffer length, in bytes
302 *
Ben Hutchings754c6532010-02-03 09:31:57 +0000303 * The NIC uses these buffers for its interrupt status registers and
Ben Hutchings8ceee662008-04-27 12:55:59 +0100304 * MAC stats dumps.
305 */
306struct efx_buffer {
307 void *addr;
308 dma_addr_t dma_addr;
309 unsigned int len;
310};
311
312
Ben Hutchings8ceee662008-04-27 12:55:59 +0100313enum efx_rx_alloc_method {
314 RX_ALLOC_METHOD_AUTO = 0,
315 RX_ALLOC_METHOD_SKB = 1,
316 RX_ALLOC_METHOD_PAGE = 2,
317};
318
319/**
320 * struct efx_channel - An Efx channel
321 *
322 * A channel comprises an event queue, at least one TX queue, at least
323 * one RX queue, and an associated tasklet for processing the event
324 * queue.
325 *
326 * @efx: Associated Efx NIC
Ben Hutchings8ceee662008-04-27 12:55:59 +0100327 * @channel: Channel instance number
Ben Hutchings56536e92008-12-12 21:37:02 -0800328 * @name: Name for channel and IRQ
Ben Hutchings8ceee662008-04-27 12:55:59 +0100329 * @enabled: Channel enabled indicator
330 * @irq: IRQ number (MSI and MSI-X only)
Ben Hutchings0d86ebd2009-10-23 08:32:13 +0000331 * @irq_moderation: IRQ moderation value (in hardware ticks)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100332 * @napi_dev: Net device used with NAPI
333 * @napi_str: NAPI control structure
334 * @reset_work: Scheduled reset work thread
335 * @work_pending: Is work pending via NAPI?
336 * @eventq: Event queue buffer
337 * @eventq_read_ptr: Event queue read pointer
338 * @last_eventq_read_ptr: Last event queue read pointer value.
339 * @eventq_magic: Event queue magic value for driver-generated test events
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000340 * @irq_count: Number of IRQs since last adaptive moderation decision
341 * @irq_mod_score: IRQ moderation score
Ben Hutchings8ceee662008-04-27 12:55:59 +0100342 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
343 * and diagnostic counters
344 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
345 * descriptors
Ben Hutchings8ceee662008-04-27 12:55:59 +0100346 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
Ben Hutchings8ceee662008-04-27 12:55:59 +0100347 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
348 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
Ben Hutchingsc1ac4032009-11-28 05:36:29 +0000349 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
Ben Hutchings8ceee662008-04-27 12:55:59 +0100350 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
351 * @n_rx_overlength: Count of RX_OVERLENGTH errors
352 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000353 * @tx_queue: Pointer to first TX queue, or %NULL if not used for TX
354 * @tx_stop_count: Core TX queue stop count
355 * @tx_stop_lock: Core TX queue stop lock
Ben Hutchings8ceee662008-04-27 12:55:59 +0100356 */
357struct efx_channel {
358 struct efx_nic *efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100359 int channel;
Ben Hutchings56536e92008-12-12 21:37:02 -0800360 char name[IFNAMSIZ + 6];
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100361 bool enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100362 int irq;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100363 unsigned int irq_moderation;
364 struct net_device *napi_dev;
365 struct napi_struct napi_str;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100366 bool work_pending;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100367 struct efx_special_buffer eventq;
368 unsigned int eventq_read_ptr;
369 unsigned int last_eventq_read_ptr;
370 unsigned int eventq_magic;
371
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000372 unsigned int irq_count;
373 unsigned int irq_mod_score;
374
Ben Hutchings8ceee662008-04-27 12:55:59 +0100375 int rx_alloc_level;
376 int rx_alloc_push_pages;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100377
378 unsigned n_rx_tobe_disc;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100379 unsigned n_rx_ip_hdr_chksum_err;
380 unsigned n_rx_tcp_udp_chksum_err;
Ben Hutchingsc1ac4032009-11-28 05:36:29 +0000381 unsigned n_rx_mcast_mismatch;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100382 unsigned n_rx_frm_trunc;
383 unsigned n_rx_overlength;
384 unsigned n_skbuff_leaks;
385
386 /* Used to pipeline received packets in order to optimise memory
387 * access with prefetches.
388 */
389 struct efx_rx_buffer *rx_pkt;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100390 bool rx_pkt_csummed;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100391
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000392 struct efx_tx_queue *tx_queue;
393 atomic_t tx_stop_count;
394 spinlock_t tx_stop_lock;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100395};
396
Ben Hutchings398468e2009-11-23 16:03:45 +0000397enum efx_led_mode {
398 EFX_LED_OFF = 0,
399 EFX_LED_ON = 1,
400 EFX_LED_DEFAULT = 2
401};
402
Ben Hutchingsc4593022009-11-23 16:08:17 +0000403#define STRING_TABLE_LOOKUP(val, member) \
404 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
405
406extern const char *efx_loopback_mode_names[];
407extern const unsigned int efx_loopback_mode_max;
408#define LOOPBACK_MODE(efx) \
409 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
410
411extern const char *efx_interrupt_mode_names[];
412extern const unsigned int efx_interrupt_mode_max;
413#define INT_MODE(efx) \
414 STRING_TABLE_LOOKUP(efx->interrupt_mode, efx_interrupt_mode)
415
416extern const char *efx_reset_type_names[];
417extern const unsigned int efx_reset_type_max;
418#define RESET_TYPE(type) \
419 STRING_TABLE_LOOKUP(type, efx_reset_type)
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100420
Ben Hutchings8ceee662008-04-27 12:55:59 +0100421enum efx_int_mode {
422 /* Be careful if altering to correct macro below */
423 EFX_INT_MODE_MSIX = 0,
424 EFX_INT_MODE_MSI = 1,
425 EFX_INT_MODE_LEGACY = 2,
426 EFX_INT_MODE_MAX /* Insert any new items before this */
427};
428#define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
429
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000430#define EFX_IS10G(efx) ((efx)->link_state.speed == 10000)
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800431
Ben Hutchings8ceee662008-04-27 12:55:59 +0100432enum nic_state {
433 STATE_INIT = 0,
434 STATE_RUNNING = 1,
435 STATE_FINI = 2,
Ben Hutchings3c787082008-09-01 12:49:08 +0100436 STATE_DISABLED = 3,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100437 STATE_MAX,
438};
439
440/*
441 * Alignment of page-allocated RX buffers
442 *
443 * Controls the number of bytes inserted at the start of an RX buffer.
444 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
445 * of the skb->head for hardware DMA].
446 */
Ben Hutchings13e9ab12008-09-01 12:50:28 +0100447#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
Ben Hutchings8ceee662008-04-27 12:55:59 +0100448#define EFX_PAGE_IP_ALIGN 0
449#else
450#define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
451#endif
452
453/*
454 * Alignment of the skb->head which wraps a page-allocated RX buffer
455 *
456 * The skb allocated to wrap an rx_buffer can have this alignment. Since
457 * the data is memcpy'd from the rx_buf, it does not need to be equal to
458 * EFX_PAGE_IP_ALIGN.
459 */
460#define EFX_PAGE_SKB_ALIGN 2
461
462/* Forward declaration */
463struct efx_nic;
464
465/* Pseudo bit-mask flow control field */
466enum efx_fc_type {
Ben Hutchings3f926da2009-04-29 08:20:37 +0000467 EFX_FC_RX = FLOW_CTRL_RX,
468 EFX_FC_TX = FLOW_CTRL_TX,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100469 EFX_FC_AUTO = 4,
470};
471
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800472/**
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000473 * struct efx_link_state - Current state of the link
474 * @up: Link is up
475 * @fd: Link is full-duplex
476 * @fc: Actual flow control flags
477 * @speed: Link speed (Mbps)
478 */
479struct efx_link_state {
480 bool up;
481 bool fd;
482 enum efx_fc_type fc;
483 unsigned int speed;
484};
485
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000486static inline bool efx_link_state_equal(const struct efx_link_state *left,
487 const struct efx_link_state *right)
488{
489 return left->up == right->up && left->fd == right->fd &&
490 left->fc == right->fc && left->speed == right->speed;
491}
492
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000493/**
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800494 * struct efx_mac_operations - Efx MAC operations table
495 * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
496 * @update_stats: Update statistics
Ben Hutchings9007b9f2009-11-25 16:12:01 +0000497 * @check_fault: Check fault state. True if fault present.
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800498 */
499struct efx_mac_operations {
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000500 int (*reconfigure) (struct efx_nic *efx);
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800501 void (*update_stats) (struct efx_nic *efx);
Ben Hutchings9007b9f2009-11-25 16:12:01 +0000502 bool (*check_fault)(struct efx_nic *efx);
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800503};
504
Ben Hutchings8ceee662008-04-27 12:55:59 +0100505/**
506 * struct efx_phy_operations - Efx PHY operations table
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000507 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
508 * efx->loopback_modes.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100509 * @init: Initialise PHY
510 * @fini: Shut down PHY
511 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000512 * @poll: Update @link_state and report whether it changed.
513 * Serialised by the mac_lock.
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800514 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
515 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000516 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800517 * (only needed where AN bit is set in mmds)
Ben Hutchings4f16c072010-02-03 09:30:50 +0000518 * @test_alive: Test that PHY is 'alive' (online)
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000519 * @test_name: Get the name of a PHY-specific test/result
Ben Hutchings4f16c072010-02-03 09:30:50 +0000520 * @run_tests: Run tests and record results as appropriate (offline).
Ben Hutchings17967212008-12-26 13:47:25 -0800521 * Flags are the ethtool tests flags.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100522 */
523struct efx_phy_operations {
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000524 int (*probe) (struct efx_nic *efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100525 int (*init) (struct efx_nic *efx);
526 void (*fini) (struct efx_nic *efx);
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000527 void (*remove) (struct efx_nic *efx);
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000528 int (*reconfigure) (struct efx_nic *efx);
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000529 bool (*poll) (struct efx_nic *efx);
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800530 void (*get_settings) (struct efx_nic *efx,
531 struct ethtool_cmd *ecmd);
532 int (*set_settings) (struct efx_nic *efx,
533 struct ethtool_cmd *ecmd);
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000534 void (*set_npage_adv) (struct efx_nic *efx, u32);
Ben Hutchings4f16c072010-02-03 09:30:50 +0000535 int (*test_alive) (struct efx_nic *efx);
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000536 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
Ben Hutchings17967212008-12-26 13:47:25 -0800537 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100538};
539
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100540/**
541 * @enum efx_phy_mode - PHY operating mode flags
542 * @PHY_MODE_NORMAL: on and should pass traffic
543 * @PHY_MODE_TX_DISABLED: on with TX disabled
Ben Hutchings3e133c42008-11-04 20:34:56 +0000544 * @PHY_MODE_LOW_POWER: set to low power through MDIO
545 * @PHY_MODE_OFF: switched off through external control
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100546 * @PHY_MODE_SPECIAL: on but will not pass traffic
547 */
548enum efx_phy_mode {
549 PHY_MODE_NORMAL = 0,
550 PHY_MODE_TX_DISABLED = 1,
Ben Hutchings3e133c42008-11-04 20:34:56 +0000551 PHY_MODE_LOW_POWER = 2,
552 PHY_MODE_OFF = 4,
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100553 PHY_MODE_SPECIAL = 8,
554};
555
556static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
557{
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100558 return !!(mode & ~PHY_MODE_TX_DISABLED);
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100559}
560
Ben Hutchings8ceee662008-04-27 12:55:59 +0100561/*
562 * Efx extended statistics
563 *
564 * Not all statistics are provided by all supported MACs. The purpose
565 * is this structure is to contain the raw statistics provided by each
566 * MAC.
567 */
568struct efx_mac_stats {
569 u64 tx_bytes;
570 u64 tx_good_bytes;
571 u64 tx_bad_bytes;
572 unsigned long tx_packets;
573 unsigned long tx_bad;
574 unsigned long tx_pause;
575 unsigned long tx_control;
576 unsigned long tx_unicast;
577 unsigned long tx_multicast;
578 unsigned long tx_broadcast;
579 unsigned long tx_lt64;
580 unsigned long tx_64;
581 unsigned long tx_65_to_127;
582 unsigned long tx_128_to_255;
583 unsigned long tx_256_to_511;
584 unsigned long tx_512_to_1023;
585 unsigned long tx_1024_to_15xx;
586 unsigned long tx_15xx_to_jumbo;
587 unsigned long tx_gtjumbo;
588 unsigned long tx_collision;
589 unsigned long tx_single_collision;
590 unsigned long tx_multiple_collision;
591 unsigned long tx_excessive_collision;
592 unsigned long tx_deferred;
593 unsigned long tx_late_collision;
594 unsigned long tx_excessive_deferred;
595 unsigned long tx_non_tcpudp;
596 unsigned long tx_mac_src_error;
597 unsigned long tx_ip_src_error;
598 u64 rx_bytes;
599 u64 rx_good_bytes;
600 u64 rx_bad_bytes;
601 unsigned long rx_packets;
602 unsigned long rx_good;
603 unsigned long rx_bad;
604 unsigned long rx_pause;
605 unsigned long rx_control;
606 unsigned long rx_unicast;
607 unsigned long rx_multicast;
608 unsigned long rx_broadcast;
609 unsigned long rx_lt64;
610 unsigned long rx_64;
611 unsigned long rx_65_to_127;
612 unsigned long rx_128_to_255;
613 unsigned long rx_256_to_511;
614 unsigned long rx_512_to_1023;
615 unsigned long rx_1024_to_15xx;
616 unsigned long rx_15xx_to_jumbo;
617 unsigned long rx_gtjumbo;
618 unsigned long rx_bad_lt64;
619 unsigned long rx_bad_64_to_15xx;
620 unsigned long rx_bad_15xx_to_jumbo;
621 unsigned long rx_bad_gtjumbo;
622 unsigned long rx_overflow;
623 unsigned long rx_missed;
624 unsigned long rx_false_carrier;
625 unsigned long rx_symbol_error;
626 unsigned long rx_align_error;
627 unsigned long rx_length_error;
628 unsigned long rx_internal_error;
629 unsigned long rx_good_lt64;
630};
631
632/* Number of bits used in a multicast filter hash address */
633#define EFX_MCAST_HASH_BITS 8
634
635/* Number of (single-bit) entries in a multicast filter hash */
636#define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
637
638/* An Efx multicast filter hash */
639union efx_multicast_hash {
640 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
641 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
642};
643
644/**
645 * struct efx_nic - an Efx NIC
646 * @name: Device name (net device name or bus id before net device registered)
647 * @pci_dev: The PCI device
648 * @type: Controller type attributes
649 * @legacy_irq: IRQ number
Ben Hutchings8d9853d2008-07-18 19:01:20 +0100650 * @workqueue: Workqueue for port reconfigures and the HW monitor.
651 * Work items do not hold and must not acquire RTNL.
Ben Hutchings6977dc62008-12-26 13:44:39 -0800652 * @workqueue_name: Name of workqueue
Ben Hutchings8ceee662008-04-27 12:55:59 +0100653 * @reset_work: Scheduled reset workitem
654 * @monitor_work: Hardware monitor workitem
655 * @membase_phys: Memory BAR value as physical address
656 * @membase: Memory BAR value
657 * @biu_lock: BIU (bus interface unit) lock
658 * @interrupt_mode: Interrupt mode
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000659 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
660 * @irq_rx_moderation: IRQ moderation time for RX event queues
Ben Hutchings8ceee662008-04-27 12:55:59 +0100661 * @state: Device state flag. Serialised by the rtnl_lock.
662 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
663 * @tx_queue: TX DMA queues
664 * @rx_queue: RX DMA queues
665 * @channel: Channels
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000666 * @next_buffer_table: First available buffer table id
Neil Turton28b581a2008-12-12 21:41:06 -0800667 * @n_channels: Number of channels in use
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000668 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
669 * @n_tx_channels: Number of channels used for TX
Ben Hutchings8ceee662008-04-27 12:55:59 +0100670 * @rx_buffer_len: RX buffer length
671 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000672 * @int_error_count: Number of internal errors seen recently
673 * @int_error_expire: Time at which error count will be expired
Ben Hutchings8ceee662008-04-27 12:55:59 +0100674 * @irq_status: Interrupt status buffer
675 * @last_irq_cpu: Last CPU to handle interrupt.
676 * This register is written with the SMP processor ID whenever an
Ben Hutchings754c6532010-02-03 09:31:57 +0000677 * interrupt is handled. It is used by efx_nic_test_interrupt()
Ben Hutchings8ceee662008-04-27 12:55:59 +0100678 * to verify that an interrupt has occurred.
Ben Hutchingsc28884c2010-04-28 09:30:00 +0000679 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
Steve Hodgson63695452010-04-28 09:27:36 +0000680 * @fatal_irq_level: IRQ level (bit number) used for serious errors
Ben Hutchings4a5b5042008-09-01 12:47:16 +0100681 * @spi_flash: SPI flash device
Ben Hutchings76884832009-11-29 15:10:44 +0000682 * This field will be %NULL if no flash device is present (or for Siena).
Ben Hutchings4a5b5042008-09-01 12:47:16 +0100683 * @spi_eeprom: SPI EEPROM device
Ben Hutchings76884832009-11-29 15:10:44 +0000684 * This field will be %NULL if no EEPROM device is present (or for Siena).
Ben Hutchingsf4150722008-11-04 20:34:28 +0000685 * @spi_lock: SPI bus lock
Ben Hutchings76884832009-11-29 15:10:44 +0000686 * @mtd_list: List of MTDs attached to the NIC
Ben Hutchings8ceee662008-04-27 12:55:59 +0100687 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
688 * @nic_data: Hardware dependant state
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100689 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
690 * @port_inhibited, efx_monitor() and efx_reconfigure_port()
Ben Hutchings8ceee662008-04-27 12:55:59 +0100691 * @port_enabled: Port enabled indicator.
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000692 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
693 * efx_mac_work() with kernel interfaces. Safe to read under any
694 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
695 * be held to modify it.
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100696 * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
Ben Hutchings8ceee662008-04-27 12:55:59 +0100697 * @port_initialized: Port initialized?
698 * @net_dev: Operating system network device. Consider holding the rtnl lock
699 * @rx_checksum_enabled: RX checksumming enabled
Ben Hutchings8ceee662008-04-27 12:55:59 +0100700 * @mac_stats: MAC statistics. These include all statistics the MACs
701 * can provide. Generic code converts these into a standard
702 * &struct net_device_stats.
703 * @stats_buffer: DMA buffer for statistics
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100704 * @stats_lock: Statistics update lock. Serialises statistics fetches
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800705 * @mac_op: MAC interface
Ben Hutchings8ceee662008-04-27 12:55:59 +0100706 * @mac_address: Permanent MAC address
707 * @phy_type: PHY type
Steve Hodgsonab867462009-11-28 05:34:44 +0000708 * @mdio_lock: MDIO lock
Ben Hutchings8ceee662008-04-27 12:55:59 +0100709 * @phy_op: PHY interface
710 * @phy_data: PHY private data (including PHY-specific stats)
Ben Hutchings68e7f452009-04-29 08:05:08 +0000711 * @mdio: PHY MDIO interface
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000712 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100713 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
Ben Hutchings9007b9f2009-11-25 16:12:01 +0000714 * @xmac_poll_required: XMAC link state needs polling
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000715 * @link_advertising: Autonegotiation advertising flags
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000716 * @link_state: Current state of the link
Ben Hutchings8ceee662008-04-27 12:55:59 +0100717 * @n_link_state_changes: Number of times the link has changed state
718 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
719 * @multicast_hash: Multicast hash table
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800720 * @wanted_fc: Wanted flow control flags
Ben Hutchings8be4f3e2009-11-25 16:12:16 +0000721 * @mac_work: Work item for changing MAC promiscuity and multicast hash
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100722 * @loopback_mode: Loopback status
723 * @loopback_modes: Supported loopback mode bitmask
724 * @loopback_selftest: Offline self-test private state
Ben Hutchings8ceee662008-04-27 12:55:59 +0100725 *
Ben Hutchings754c6532010-02-03 09:31:57 +0000726 * This is stored in the private area of the &struct net_device.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100727 */
728struct efx_nic {
729 char name[IFNAMSIZ];
730 struct pci_dev *pci_dev;
731 const struct efx_nic_type *type;
732 int legacy_irq;
733 struct workqueue_struct *workqueue;
Ben Hutchings6977dc62008-12-26 13:44:39 -0800734 char workqueue_name[16];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100735 struct work_struct reset_work;
736 struct delayed_work monitor_work;
Ben Hutchings086ea352008-05-16 21:17:06 +0100737 resource_size_t membase_phys;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100738 void __iomem *membase;
739 spinlock_t biu_lock;
740 enum efx_int_mode interrupt_mode;
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000741 bool irq_rx_adaptive;
742 unsigned int irq_rx_moderation;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100743
Ben Hutchings8ceee662008-04-27 12:55:59 +0100744 enum nic_state state;
745 enum reset_type reset_pending;
746
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000747 struct efx_tx_queue tx_queue[EFX_MAX_TX_QUEUES];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100748 struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
749 struct efx_channel channel[EFX_MAX_CHANNELS];
750
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000751 unsigned next_buffer_table;
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000752 unsigned n_channels;
753 unsigned n_rx_channels;
754 unsigned n_tx_channels;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100755 unsigned int rx_buffer_len;
756 unsigned int rx_buffer_order;
757
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000758 unsigned int_error_count;
759 unsigned long int_error_expire;
760
Ben Hutchings8ceee662008-04-27 12:55:59 +0100761 struct efx_buffer irq_status;
762 volatile signed int last_irq_cpu;
Ben Hutchingsc28884c2010-04-28 09:30:00 +0000763 unsigned irq_zero_count;
Steve Hodgson63695452010-04-28 09:27:36 +0000764 unsigned fatal_irq_level;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100765
Ben Hutchings4a5b5042008-09-01 12:47:16 +0100766 struct efx_spi_device *spi_flash;
767 struct efx_spi_device *spi_eeprom;
Ben Hutchingsf4150722008-11-04 20:34:28 +0000768 struct mutex spi_lock;
Ben Hutchings76884832009-11-29 15:10:44 +0000769#ifdef CONFIG_SFC_MTD
770 struct list_head mtd_list;
771#endif
Ben Hutchings4a5b5042008-09-01 12:47:16 +0100772
Ben Hutchings8ceee662008-04-27 12:55:59 +0100773 unsigned n_rx_nodesc_drop_cnt;
774
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000775 void *nic_data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100776
777 struct mutex mac_lock;
Ben Hutchings766ca0f2008-12-12 21:59:24 -0800778 struct work_struct mac_work;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100779 bool port_enabled;
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100780 bool port_inhibited;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100781
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100782 bool port_initialized;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100783 struct net_device *net_dev;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100784 bool rx_checksum_enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100785
Ben Hutchings8ceee662008-04-27 12:55:59 +0100786 struct efx_mac_stats mac_stats;
787 struct efx_buffer stats_buffer;
788 spinlock_t stats_lock;
789
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800790 struct efx_mac_operations *mac_op;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100791 unsigned char mac_address[ETH_ALEN];
792
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000793 unsigned int phy_type;
Steve Hodgsonab867462009-11-28 05:34:44 +0000794 struct mutex mdio_lock;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100795 struct efx_phy_operations *phy_op;
796 void *phy_data;
Ben Hutchings68e7f452009-04-29 08:05:08 +0000797 struct mdio_if_info mdio;
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000798 unsigned int mdio_bus;
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100799 enum efx_phy_mode phy_mode;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100800
Ben Hutchings9007b9f2009-11-25 16:12:01 +0000801 bool xmac_poll_required;
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000802 u32 link_advertising;
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000803 struct efx_link_state link_state;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100804 unsigned int n_link_state_changes;
805
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100806 bool promiscuous;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100807 union efx_multicast_hash multicast_hash;
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800808 enum efx_fc_type wanted_fc;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100809
810 atomic_t rx_reset;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100811 enum efx_loopback_mode loopback_mode;
Ben Hutchingse58f69f2009-11-29 15:08:41 +0000812 u64 loopback_modes;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100813
814 void *loopback_selftest;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100815};
816
Ben Hutchings55668612008-05-16 21:16:10 +0100817static inline int efx_dev_registered(struct efx_nic *efx)
818{
819 return efx->net_dev->reg_state == NETREG_REGISTERED;
820}
821
822/* Net device name, for inclusion in log messages if it has been registered.
823 * Use efx->name not efx->net_dev->name so that races with (un)registration
824 * are harmless.
825 */
826static inline const char *efx_dev_name(struct efx_nic *efx)
827{
828 return efx_dev_registered(efx) ? efx->name : "";
829}
830
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000831static inline unsigned int efx_port_num(struct efx_nic *efx)
832{
Ben Hutchings3df95ce2010-06-02 10:39:56 +0000833 return efx->net_dev->dev_id;
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000834}
835
Ben Hutchings8ceee662008-04-27 12:55:59 +0100836/**
837 * struct efx_nic_type - Efx device type definition
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000838 * @probe: Probe the controller
839 * @remove: Free resources allocated by probe()
840 * @init: Initialise the controller
841 * @fini: Shut down the controller
842 * @monitor: Periodic function for polling link state and hardware monitor
843 * @reset: Reset the controller hardware and possibly the PHY. This will
844 * be called while the controller is uninitialised.
845 * @probe_port: Probe the MAC and PHY
846 * @remove_port: Free resources allocated by probe_port()
847 * @prepare_flush: Prepare the hardware for flushing the DMA queues
848 * @update_stats: Update statistics not provided by event handling
849 * @start_stats: Start the regular fetching of statistics
850 * @stop_stats: Stop the regular fetching of statistics
Ben Hutchings06629f02009-11-29 03:43:43 +0000851 * @set_id_led: Set state of identifying LED or revert to automatic function
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000852 * @push_irq_moderation: Apply interrupt moderation value
853 * @push_multicast_hash: Apply multicast hash table
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000854 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
Ben Hutchings89c758f2009-11-29 03:43:07 +0000855 * @get_wol: Get WoL configuration from driver state
856 * @set_wol: Push WoL configuration to the NIC
857 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
Ben Hutchings9bfc4bb2009-11-29 03:43:23 +0000858 * @test_registers: Test read/write functionality of control registers
Ben Hutchings0aa3fba2009-11-29 03:43:33 +0000859 * @test_nvram: Test validity of NVRAM contents
Steve Hodgsonb895d732009-11-28 05:35:00 +0000860 * @default_mac_ops: efx_mac_operations to set at startup
Ben Hutchingsdaeda632009-11-28 05:36:04 +0000861 * @revision: Hardware architecture revision
Ben Hutchings8ceee662008-04-27 12:55:59 +0100862 * @mem_map_size: Memory BAR mapped size
863 * @txd_ptr_tbl_base: TX descriptor ring base address
864 * @rxd_ptr_tbl_base: RX descriptor ring base address
865 * @buf_tbl_base: Buffer table base address
866 * @evq_ptr_tbl_base: Event queue pointer table base address
867 * @evq_rptr_tbl_base: Event queue read-pointer table base address
Ben Hutchings8ceee662008-04-27 12:55:59 +0100868 * @max_dma_mask: Maximum possible DMA mask
Ben Hutchings8ceee662008-04-27 12:55:59 +0100869 * @rx_buffer_padding: Padding added to each RX buffer
870 * @max_interrupt_mode: Highest capability interrupt mode supported
871 * from &enum efx_init_mode.
872 * @phys_addr_channels: Number of channels with physically addressed
873 * descriptors
Ben Hutchings0228f5cdb02009-11-28 05:36:12 +0000874 * @tx_dc_base: Base address in SRAM of TX queue descriptor caches
875 * @rx_dc_base: Base address in SRAM of RX queue descriptor caches
Ben Hutchingsc383b532009-11-29 15:11:02 +0000876 * @offload_features: net_device feature flags for protocol offload
877 * features implemented in hardware
Ben Hutchingseb9f6742009-11-29 03:43:15 +0000878 * @reset_world_flags: Flags for additional components covered by
879 * reset method RESET_TYPE_WORLD
Ben Hutchings8ceee662008-04-27 12:55:59 +0100880 */
881struct efx_nic_type {
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000882 int (*probe)(struct efx_nic *efx);
883 void (*remove)(struct efx_nic *efx);
884 int (*init)(struct efx_nic *efx);
885 void (*fini)(struct efx_nic *efx);
886 void (*monitor)(struct efx_nic *efx);
887 int (*reset)(struct efx_nic *efx, enum reset_type method);
888 int (*probe_port)(struct efx_nic *efx);
889 void (*remove_port)(struct efx_nic *efx);
890 void (*prepare_flush)(struct efx_nic *efx);
891 void (*update_stats)(struct efx_nic *efx);
892 void (*start_stats)(struct efx_nic *efx);
893 void (*stop_stats)(struct efx_nic *efx);
Ben Hutchings06629f02009-11-29 03:43:43 +0000894 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000895 void (*push_irq_moderation)(struct efx_channel *channel);
896 void (*push_multicast_hash)(struct efx_nic *efx);
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000897 int (*reconfigure_port)(struct efx_nic *efx);
Ben Hutchings89c758f2009-11-29 03:43:07 +0000898 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
899 int (*set_wol)(struct efx_nic *efx, u32 type);
900 void (*resume_wol)(struct efx_nic *efx);
Ben Hutchings9bfc4bb2009-11-29 03:43:23 +0000901 int (*test_registers)(struct efx_nic *efx);
Ben Hutchings0aa3fba2009-11-29 03:43:33 +0000902 int (*test_nvram)(struct efx_nic *efx);
Steve Hodgsonb895d732009-11-28 05:35:00 +0000903 struct efx_mac_operations *default_mac_ops;
904
Ben Hutchingsdaeda632009-11-28 05:36:04 +0000905 int revision;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100906 unsigned int mem_map_size;
907 unsigned int txd_ptr_tbl_base;
908 unsigned int rxd_ptr_tbl_base;
909 unsigned int buf_tbl_base;
910 unsigned int evq_ptr_tbl_base;
911 unsigned int evq_rptr_tbl_base;
Ben Hutchings9bbd7d92008-05-16 21:18:48 +0100912 u64 max_dma_mask;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100913 unsigned int rx_buffer_padding;
914 unsigned int max_interrupt_mode;
915 unsigned int phys_addr_channels;
Ben Hutchings0228f5cdb02009-11-28 05:36:12 +0000916 unsigned int tx_dc_base;
917 unsigned int rx_dc_base;
Ben Hutchingsc383b532009-11-29 15:11:02 +0000918 unsigned long offload_features;
Ben Hutchingseb9f6742009-11-29 03:43:15 +0000919 u32 reset_world_flags;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100920};
921
922/**************************************************************************
923 *
924 * Prototypes and inline functions
925 *
926 *************************************************************************/
927
928/* Iterate over all used channels */
929#define efx_for_each_channel(_channel, _efx) \
Ben Hutchings3d07df12010-04-28 09:29:50 +0000930 for (_channel = &((_efx)->channel[0]); \
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000931 _channel < &((_efx)->channel[(efx)->n_channels]); \
932 _channel++)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100933
Ben Hutchings8ceee662008-04-27 12:55:59 +0100934/* Iterate over all used TX queues */
935#define efx_for_each_tx_queue(_tx_queue, _efx) \
Ben Hutchings3d07df12010-04-28 09:29:50 +0000936 for (_tx_queue = &((_efx)->tx_queue[0]); \
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000937 _tx_queue < &((_efx)->tx_queue[EFX_TXQ_TYPES * \
938 (_efx)->n_tx_channels]); \
Ben Hutchings60ac1062008-09-01 12:44:59 +0100939 _tx_queue++)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100940
941/* Iterate over all TX queues belonging to a channel */
942#define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000943 for (_tx_queue = (_channel)->tx_queue; \
944 _tx_queue && _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
945 _tx_queue++)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100946
947/* Iterate over all used RX queues */
948#define efx_for_each_rx_queue(_rx_queue, _efx) \
Ben Hutchings3d07df12010-04-28 09:29:50 +0000949 for (_rx_queue = &((_efx)->rx_queue[0]); \
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000950 _rx_queue < &((_efx)->rx_queue[(_efx)->n_rx_channels]); \
Ben Hutchings8831da72008-09-01 12:47:48 +0100951 _rx_queue++)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100952
953/* Iterate over all RX queues belonging to a channel */
954#define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
Ben Hutchings3d07df12010-04-28 09:29:50 +0000955 for (_rx_queue = &((_channel)->efx->rx_queue[(_channel)->channel]); \
Ben Hutchingsa2589022008-09-01 12:47:57 +0100956 _rx_queue; \
957 _rx_queue = NULL) \
Ben Hutchings3d07df12010-04-28 09:29:50 +0000958 if (_rx_queue->channel != (_channel)) \
Ben Hutchings8ceee662008-04-27 12:55:59 +0100959 continue; \
960 else
961
962/* Returns a pointer to the specified receive buffer in the RX
963 * descriptor queue.
964 */
965static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
966 unsigned int index)
967{
968 return (&rx_queue->buffer[index]);
969}
970
971/* Set bit in a little-endian bitfield */
Ben Hutchings18c2fc02008-09-01 12:43:39 +0100972static inline void set_bit_le(unsigned nr, unsigned char *addr)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100973{
974 addr[nr / 8] |= (1 << (nr % 8));
975}
976
977/* Clear bit in a little-endian bitfield */
Ben Hutchings18c2fc02008-09-01 12:43:39 +0100978static inline void clear_bit_le(unsigned nr, unsigned char *addr)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100979{
980 addr[nr / 8] &= ~(1 << (nr % 8));
981}
982
983
984/**
985 * EFX_MAX_FRAME_LEN - calculate maximum frame length
986 *
987 * This calculates the maximum frame length that will be used for a
988 * given MTU. The frame length will be equal to the MTU plus a
989 * constant amount of header space and padding. This is the quantity
990 * that the net driver will program into the MAC as the maximum frame
991 * length.
992 *
Ben Hutchings754c6532010-02-03 09:31:57 +0000993 * The 10G MAC requires 8-byte alignment on the frame
Ben Hutchings8ceee662008-04-27 12:55:59 +0100994 * length, so we round up to the nearest 8.
Ben Hutchingscc117632009-08-26 08:17:59 +0000995 *
996 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
997 * XGMII cycle). If the frame length reaches the maximum value in the
998 * same cycle, the XMAC can miss the IPG altogether. We work around
999 * this by adding a further 16 bytes.
Ben Hutchings8ceee662008-04-27 12:55:59 +01001000 */
1001#define EFX_MAX_FRAME_LEN(mtu) \
Ben Hutchingscc117632009-08-26 08:17:59 +00001002 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001003
1004
1005#endif /* EFX_NET_DRIVER_H */