blob: c9399c8688c5c62555137d2db5a6ba060e2240c4 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Ported to libata by:
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
11 *
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 *
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
17 *
18 *
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
21 *
22 * Hardware information only available under NDA.
23 *
24 */
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi.h>
33#include <scsi/scsi_host.h>
34#include <scsi/scsi_cmnd.h>
35#include <linux/libata.h>
Jeff Garzik669a5db2006-08-29 18:12:40 -040036
37#define DRV_NAME "pata_pdc2027x"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040038#define DRV_VERSION "1.0"
Jeff Garzik669a5db2006-08-29 18:12:40 -040039#undef PDC_DEBUG
40
41#ifdef PDC_DEBUG
Harvey Harrison7f5e4e82008-03-05 18:24:52 -080042#define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
Jeff Garzik669a5db2006-08-29 18:12:40 -040043#else
44#define PDPRINTK(fmt, args...)
45#endif
46
47enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090048 PDC_MMIO_BAR = 5,
49
Jeff Garzik669a5db2006-08-29 18:12:40 -040050 PDC_UDMA_100 = 0,
51 PDC_UDMA_133 = 1,
52
53 PDC_100_MHZ = 100000000,
54 PDC_133_MHZ = 133333333,
55
56 PDC_SYS_CTL = 0x1100,
57 PDC_ATA_CTL = 0x1104,
58 PDC_GLOBAL_CTL = 0x1108,
59 PDC_CTCR0 = 0x110C,
60 PDC_CTCR1 = 0x1110,
61 PDC_BYTE_COUNT = 0x1120,
62 PDC_PLL_CTL = 0x1202,
63};
64
65static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Bartlomiej Zolnierkiewiczadacaf12011-10-13 12:57:51 +020066static int pdc2027x_reinit_one(struct pci_dev *pdev);
Tejun Heoa1efdab2008-03-25 12:22:50 +090067static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -040068static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
69static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
Jeff Garzik669a5db2006-08-29 18:12:40 -040070static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
Alan Cox9bedb792007-04-11 00:19:00 +010071static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
72static int pdc2027x_cable_detect(struct ata_port *ap);
Tejun Heo02607312007-08-06 18:36:23 +090073static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
Jeff Garzik669a5db2006-08-29 18:12:40 -040074
75/*
76 * ATA Timing Tables based on 133MHz controller clock.
77 * These tables are only used when the controller is in 133MHz clock.
78 * If the controller is in 100MHz clock, the ASIC hardware will
79 * set the timing registers automatically when "set feature" command
80 * is issued to the device. However, if the controller clock is 133MHz,
81 * the following tables must be used.
82 */
83static struct pdc2027x_pio_timing {
84 u8 value0, value1, value2;
85} pdc2027x_pio_timing_tbl [] = {
86 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
87 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
88 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
89 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
90 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
91};
92
93static struct pdc2027x_mdma_timing {
94 u8 value0, value1;
95} pdc2027x_mdma_timing_tbl [] = {
96 { 0xdf, 0x5f }, /* MDMA mode 0 */
97 { 0x6b, 0x27 }, /* MDMA mode 1 */
98 { 0x69, 0x25 }, /* MDMA mode 2 */
99};
100
101static struct pdc2027x_udma_timing {
102 u8 value0, value1, value2;
103} pdc2027x_udma_timing_tbl [] = {
104 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
105 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
106 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
107 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
108 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
109 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
110 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
111};
112
113static const struct pci_device_id pdc2027x_pci_tbl[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
120 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
121
Jeff Garzik669a5db2006-08-29 18:12:40 -0400122 { } /* terminate list */
123};
124
125static struct pci_driver pdc2027x_pci_driver = {
126 .name = DRV_NAME,
127 .id_table = pdc2027x_pci_tbl,
128 .probe = pdc2027x_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900129 .remove = ata_pci_remove_one,
Bartlomiej Zolnierkiewiczadacaf12011-10-13 12:57:51 +0200130#ifdef CONFIG_PM
131 .suspend = ata_pci_device_suspend,
132 .resume = pdc2027x_reinit_one,
133#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400134};
135
136static struct scsi_host_template pdc2027x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900137 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400138};
139
140static struct ata_port_operations pdc2027x_pata100_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900141 .inherits = &ata_bmdma_port_ops,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400142 .check_atapi_dma = pdc2027x_check_atapi_dma,
Alan Cox9bedb792007-04-11 00:19:00 +0100143 .cable_detect = pdc2027x_cable_detect,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900144 .prereset = pdc2027x_prereset,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400145};
146
147static struct ata_port_operations pdc2027x_pata133_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900148 .inherits = &pdc2027x_pata100_ops,
149 .mode_filter = pdc2027x_mode_filter,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400150 .set_piomode = pdc2027x_set_piomode,
151 .set_dmamode = pdc2027x_set_dmamode,
Alan Cox9bedb792007-04-11 00:19:00 +0100152 .set_mode = pdc2027x_set_mode,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400153};
154
155static struct ata_port_info pdc2027x_port_info[] = {
156 /* PDC_UDMA_100 */
157 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300158 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100159 .pio_mask = ATA_PIO4,
160 .mwdma_mask = ATA_MWDMA2,
161 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400162 .port_ops = &pdc2027x_pata100_ops,
163 },
164 /* PDC_UDMA_133 */
165 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300166 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100167 .pio_mask = ATA_PIO4,
168 .mwdma_mask = ATA_MWDMA2,
169 .udma_mask = ATA_UDMA6,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400170 .port_ops = &pdc2027x_pata133_ops,
171 },
172};
173
174MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
175MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
176MODULE_LICENSE("GPL");
177MODULE_VERSION(DRV_VERSION);
178MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
179
180/**
181 * port_mmio - Get the MMIO address of PDC2027x extended registers
182 * @ap: Port
183 * @offset: offset from mmio base
184 */
Al Viro7c250412006-09-25 02:57:57 +0100185static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400186{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900187 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400188}
189
190/**
191 * dev_mmio - Get the MMIO address of PDC2027x extended registers
192 * @ap: Port
193 * @adev: device
194 * @offset: offset from mmio base
195 */
Al Viro7c250412006-09-25 02:57:57 +0100196static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400197{
198 u8 adj = (adev->devno) ? 0x08 : 0x00;
199 return port_mmio(ap, offset) + adj;
200}
201
202/**
Alan Cox9bedb792007-04-11 00:19:00 +0100203 * pdc2027x_pata_cable_detect - Probe host controller cable detect info
Jeff Garzik669a5db2006-08-29 18:12:40 -0400204 * @ap: Port for which cable detect info is desired
205 *
206 * Read 80c cable indicator from Promise extended register.
207 * This register is latched when the system is reset.
208 *
209 * LOCKING:
210 * None (inherited from caller).
211 */
Alan Cox9bedb792007-04-11 00:19:00 +0100212static int pdc2027x_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400213{
214 u32 cgcr;
215
216 /* check cable detect results */
Alan Coxd2a84f42007-09-20 15:07:12 +0100217 cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400218 if (cgcr & (1 << 26))
219 goto cbl40;
220
221 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
222
Alan Cox9bedb792007-04-11 00:19:00 +0100223 return ATA_CBL_PATA80;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400224cbl40:
225 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
Alan Cox9bedb792007-04-11 00:19:00 +0100226 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400227}
228
229/**
230 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
231 * @ap: Port to check
232 */
233static inline int pdc2027x_port_enabled(struct ata_port *ap)
234{
Alan Coxd2a84f42007-09-20 15:07:12 +0100235 return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400236}
237
238/**
239 * pdc2027x_prereset - prereset for PATA host controller
Tejun Heocc0680a2007-08-06 18:36:23 +0900240 * @link: Target link
Tejun Heod4b2bab2007-02-02 16:50:52 +0900241 * @deadline: deadline jiffies for the operation
Jeff Garzik669a5db2006-08-29 18:12:40 -0400242 *
243 * Probeinit including cable detection.
244 *
245 * LOCKING:
246 * None (inherited from caller).
247 */
248
Tejun Heocc0680a2007-08-06 18:36:23 +0900249static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400250{
251 /* Check whether port enabled */
Tejun Heocc0680a2007-08-06 18:36:23 +0900252 if (!pdc2027x_port_enabled(link->ap))
Alan Coxc9619222006-09-26 17:53:38 +0100253 return -ENOENT;
Tejun Heo9363c382008-04-07 22:47:16 +0900254 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400255}
256
257/**
Alan Cox9bedb792007-04-11 00:19:00 +0100258 * pdc2720x_mode_filter - mode selection filter
259 * @adev: ATA device
260 * @mask: list of modes proposed
261 *
262 * Block UDMA on devices that cause trouble with this controller.
263 */
264
265static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
266{
267 unsigned char model_num[ATA_ID_PROD_LEN + 1];
268 struct ata_device *pair = ata_dev_pair(adev);
269
270 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
Tejun Heoc7087652010-05-10 21:41:34 +0200271 return mask;
Alan Cox9bedb792007-04-11 00:19:00 +0100272
273 /* Check for slave of a Maxtor at UDMA6 */
274 ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
275 ATA_ID_PROD_LEN + 1);
276 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
Al Viro4ca4e432007-12-30 09:32:22 +0000277 if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
Alan Cox9bedb792007-04-11 00:19:00 +0100278 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
279
Tejun Heoc7087652010-05-10 21:41:34 +0200280 return mask;
Alan Cox9bedb792007-04-11 00:19:00 +0100281}
282
283/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400284 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
285 * @ap: Port to configure
286 * @adev: um
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287 *
288 * Set PIO mode for device.
289 *
290 * LOCKING:
291 * None (inherited from caller).
292 */
293
294static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
295{
296 unsigned int pio = adev->pio_mode - XFER_PIO_0;
297 u32 ctcr0, ctcr1;
298
299 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
300
301 /* Sanity check */
302 if (pio > 4) {
303 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
304 return;
305
306 }
307
308 /* Set the PIO timing registers using value table for 133MHz */
309 PDPRINTK("Set pio regs... \n");
310
Alan Coxd2a84f42007-09-20 15:07:12 +0100311 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400312 ctcr0 &= 0xffff0000;
313 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
314 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
Alan Coxd2a84f42007-09-20 15:07:12 +0100315 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400316
Alan Coxd2a84f42007-09-20 15:07:12 +0100317 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400318 ctcr1 &= 0x00ffffff;
319 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
Alan Coxd2a84f42007-09-20 15:07:12 +0100320 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400321
322 PDPRINTK("Set pio regs done\n");
323
324 PDPRINTK("Set to pio mode[%u] \n", pio);
325}
326
327/**
328 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
329 * @ap: Port to configure
330 * @adev: um
Jeff Garzik669a5db2006-08-29 18:12:40 -0400331 *
332 * Set UDMA mode for device.
333 *
334 * LOCKING:
335 * None (inherited from caller).
336 */
337static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
338{
339 unsigned int dma_mode = adev->dma_mode;
340 u32 ctcr0, ctcr1;
341
342 if ((dma_mode >= XFER_UDMA_0) &&
343 (dma_mode <= XFER_UDMA_6)) {
344 /* Set the UDMA timing registers with value table for 133MHz */
345 unsigned int udma_mode = dma_mode & 0x07;
346
347 if (dma_mode == XFER_UDMA_2) {
348 /*
349 * Turn off tHOLD.
350 * If tHOLD is '1', the hardware will add half clock for data hold time.
351 * This code segment seems to be no effect. tHOLD will be overwritten below.
352 */
Alan Coxd2a84f42007-09-20 15:07:12 +0100353 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
354 iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400355 }
356
357 PDPRINTK("Set udma regs... \n");
358
Alan Coxd2a84f42007-09-20 15:07:12 +0100359 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400360 ctcr1 &= 0xff000000;
361 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
362 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
363 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
Alan Coxd2a84f42007-09-20 15:07:12 +0100364 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400365
366 PDPRINTK("Set udma regs done\n");
367
368 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
369
370 } else if ((dma_mode >= XFER_MW_DMA_0) &&
371 (dma_mode <= XFER_MW_DMA_2)) {
372 /* Set the MDMA timing registers with value table for 133MHz */
373 unsigned int mdma_mode = dma_mode & 0x07;
374
375 PDPRINTK("Set mdma regs... \n");
Alan Coxd2a84f42007-09-20 15:07:12 +0100376 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400377
378 ctcr0 &= 0x0000ffff;
379 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
380 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
381
Alan Coxd2a84f42007-09-20 15:07:12 +0100382 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400383 PDPRINTK("Set mdma regs done\n");
384
385 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
386 } else {
387 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
388 }
389}
390
391/**
Alan Cox9bedb792007-04-11 00:19:00 +0100392 * pdc2027x_set_mode - Set the timing registers back to correct values.
Tejun Heo02607312007-08-06 18:36:23 +0900393 * @link: link to configure
Alan Cox9bedb792007-04-11 00:19:00 +0100394 * @r_failed: Returned device for failure
Jeff Garzik669a5db2006-08-29 18:12:40 -0400395 *
396 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
397 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
398 * This function overwrites the possibly incorrect values set by the hardware to be correct.
399 */
Tejun Heo02607312007-08-06 18:36:23 +0900400static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400401{
Tejun Heo02607312007-08-06 18:36:23 +0900402 struct ata_port *ap = link->ap;
Tejun Heof58229f2007-08-06 18:36:23 +0900403 struct ata_device *dev;
404 int rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400405
Tejun Heo02607312007-08-06 18:36:23 +0900406 rc = ata_do_set_mode(link, r_failed);
Tejun Heof58229f2007-08-06 18:36:23 +0900407 if (rc < 0)
408 return rc;
Alan Cox9bedb792007-04-11 00:19:00 +0100409
Tejun Heo1eca4362008-11-03 20:03:17 +0900410 ata_for_each_dev(dev, link, ENABLED) {
411 pdc2027x_set_piomode(ap, dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400412
Tejun Heo1eca4362008-11-03 20:03:17 +0900413 /*
414 * Enable prefetch if the device support PIO only.
415 */
416 if (dev->xfer_shift == ATA_SHIFT_PIO) {
417 u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1));
418 ctcr1 |= (1 << 25);
419 iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400420
Tejun Heo1eca4362008-11-03 20:03:17 +0900421 PDPRINTK("Turn on prefetch\n");
422 } else {
423 pdc2027x_set_dmamode(ap, dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400424 }
425 }
Alan Cox9bedb792007-04-11 00:19:00 +0100426 return 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400427}
428
429/**
430 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
431 * @qc: Metadata associated with taskfile to check
432 *
433 * LOCKING:
434 * None (inherited from caller).
435 *
436 * RETURNS: 0 when ATAPI DMA can be used
437 * 1 otherwise
438 */
439static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
440{
441 struct scsi_cmnd *cmd = qc->scsicmd;
442 u8 *scsicmd = cmd->cmnd;
443 int rc = 1; /* atapi dma off by default */
444
445 /*
446 * This workaround is from Promise's GPL driver.
447 * If ATAPI DMA is used for commands not in the
448 * following white list, say MODE_SENSE and REQUEST_SENSE,
449 * pdc2027x might hit the irq lost problem.
450 */
451 switch (scsicmd[0]) {
452 case READ_10:
453 case WRITE_10:
454 case READ_12:
455 case WRITE_12:
456 case READ_6:
457 case WRITE_6:
458 case 0xad: /* READ_DVD_STRUCTURE */
459 case 0xbe: /* READ_CD */
460 /* ATAPI DMA is ok */
461 rc = 0;
462 break;
463 default:
464 ;
465 }
466
467 return rc;
468}
469
470/**
471 * pdc_read_counter - Read the ctr counter
Tejun Heo5d728822007-04-17 23:44:08 +0900472 * @host: target ATA host
Jeff Garzik669a5db2006-08-29 18:12:40 -0400473 */
474
Tejun Heo5d728822007-04-17 23:44:08 +0900475static long pdc_read_counter(struct ata_host *host)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400476{
Tejun Heo5d728822007-04-17 23:44:08 +0900477 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400478 long counter;
479 int retry = 1;
480 u32 bccrl, bccrh, bccrlv, bccrhv;
481
482retry:
Alan Coxd2a84f42007-09-20 15:07:12 +0100483 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
484 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400485
486 /* Read the counter values again for verification */
Alan Coxd2a84f42007-09-20 15:07:12 +0100487 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
488 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400489
490 counter = (bccrh << 15) | bccrl;
491
492 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
493 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
494
495 /*
496 * The 30-bit decreasing counter are read by 2 pieces.
497 * Incorrect value may be read when both bccrh and bccrl are changing.
498 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
499 */
500 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
501 retry--;
502 PDPRINTK("rereading counter\n");
503 goto retry;
504 }
505
506 return counter;
507}
508
509/**
510 * adjust_pll - Adjust the PLL input clock in Hz.
511 *
512 * @pdc_controller: controller specific information
Tejun Heo5d728822007-04-17 23:44:08 +0900513 * @host: target ATA host
Jeff Garzik669a5db2006-08-29 18:12:40 -0400514 * @pll_clock: The input of PLL in HZ
515 */
Tejun Heo5d728822007-04-17 23:44:08 +0900516static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400517{
Tejun Heo5d728822007-04-17 23:44:08 +0900518 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400519 u16 pll_ctl;
520 long pll_clock_khz = pll_clock / 1000;
521 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
522 long ratio = pout_required / pll_clock_khz;
523 int F, R;
524
525 /* Sanity check */
526 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
527 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
528 return;
529 }
530
531#ifdef PDC_DEBUG
532 PDPRINTK("pout_required is %ld\n", pout_required);
533
534 /* Show the current clock value of PLL control register
535 * (maybe already configured by the firmware)
536 */
Alan Coxd2a84f42007-09-20 15:07:12 +0100537 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400538
539 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
540#endif
541
542 /*
543 * Calculate the ratio of F, R and OD
544 * POUT = (F + 2) / (( R + 2) * NO)
545 */
546 if (ratio < 8600L) { /* 8.6x */
547 /* Using NO = 0x01, R = 0x0D */
548 R = 0x0d;
549 } else if (ratio < 12900L) { /* 12.9x */
550 /* Using NO = 0x01, R = 0x08 */
551 R = 0x08;
552 } else if (ratio < 16100L) { /* 16.1x */
553 /* Using NO = 0x01, R = 0x06 */
554 R = 0x06;
555 } else if (ratio < 64000L) { /* 64x */
556 R = 0x00;
557 } else {
558 /* Invalid ratio */
559 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
560 return;
561 }
562
563 F = (ratio * (R+2)) / 1000 - 2;
564
565 if (unlikely(F < 0 || F > 127)) {
566 /* Invalid F */
567 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
568 return;
569 }
570
571 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
572
573 pll_ctl = (R << 8) | F;
574
575 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
576
Alan Coxd2a84f42007-09-20 15:07:12 +0100577 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
578 ioread16(mmio_base + PDC_PLL_CTL); /* flush */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400579
580 /* Wait the PLL circuit to be stable */
581 mdelay(30);
582
583#ifdef PDC_DEBUG
584 /*
585 * Show the current clock value of PLL control register
586 * (maybe configured by the firmware)
587 */
Alan Coxd2a84f42007-09-20 15:07:12 +0100588 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400589
590 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
591#endif
592
593 return;
594}
595
596/**
597 * detect_pll_input_clock - Detect the PLL input clock in Hz.
Tejun Heo5d728822007-04-17 23:44:08 +0900598 * @host: target ATA host
Jeff Garzik669a5db2006-08-29 18:12:40 -0400599 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
600 * Half of the PCI clock.
601 */
Tejun Heo5d728822007-04-17 23:44:08 +0900602static long pdc_detect_pll_input_clock(struct ata_host *host)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400603{
Tejun Heo5d728822007-04-17 23:44:08 +0900604 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400605 u32 scr;
606 long start_count, end_count;
Albert Lee8c781bf2007-06-26 13:43:15 +0800607 struct timeval start_time, end_time;
608 long pll_clock, usec_elapsed;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400609
Jeff Garzik669a5db2006-08-29 18:12:40 -0400610 /* Start the test mode */
Alan Coxd2a84f42007-09-20 15:07:12 +0100611 scr = ioread32(mmio_base + PDC_SYS_CTL);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400612 PDPRINTK("scr[%X]\n", scr);
Alan Coxd2a84f42007-09-20 15:07:12 +0100613 iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
614 ioread32(mmio_base + PDC_SYS_CTL); /* flush */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400615
Mikael Pettersson78c4af02007-08-18 22:58:53 +0200616 /* Read current counter value */
617 start_count = pdc_read_counter(host);
618 do_gettimeofday(&start_time);
619
Jeff Garzik669a5db2006-08-29 18:12:40 -0400620 /* Let the counter run for 100 ms. */
621 mdelay(100);
622
623 /* Read the counter values again */
Tejun Heo5d728822007-04-17 23:44:08 +0900624 end_count = pdc_read_counter(host);
Albert Lee8c781bf2007-06-26 13:43:15 +0800625 do_gettimeofday(&end_time);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400626
627 /* Stop the test mode */
Alan Coxd2a84f42007-09-20 15:07:12 +0100628 scr = ioread32(mmio_base + PDC_SYS_CTL);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400629 PDPRINTK("scr[%X]\n", scr);
Alan Coxd2a84f42007-09-20 15:07:12 +0100630 iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
631 ioread32(mmio_base + PDC_SYS_CTL); /* flush */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400632
633 /* calculate the input clock in Hz */
Albert Lee8c781bf2007-06-26 13:43:15 +0800634 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
635 (end_time.tv_usec - start_time.tv_usec);
636
Mikael Pettersson78c4af02007-08-18 22:58:53 +0200637 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
Albert Lee8c781bf2007-06-26 13:43:15 +0800638 (100000000 / usec_elapsed);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400639
640 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
641 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
642
643 return pll_clock;
644}
645
646/**
647 * pdc_hardware_init - Initialize the hardware.
Tejun Heo5d728822007-04-17 23:44:08 +0900648 * @host: target ATA host
649 * @board_idx: board identifier
Jeff Garzik669a5db2006-08-29 18:12:40 -0400650 */
Tejun Heo5d728822007-04-17 23:44:08 +0900651static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400652{
653 long pll_clock;
654
655 /*
656 * Detect PLL input clock rate.
657 * On some system, where PCI bus is running at non-standard clock rate.
658 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
659 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
660 */
Tejun Heo5d728822007-04-17 23:44:08 +0900661 pll_clock = pdc_detect_pll_input_clock(host);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400662
Joe Perchesa44fec12011-04-15 15:51:58 -0700663 dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400664
665 /* Adjust PLL control register */
Tejun Heo5d728822007-04-17 23:44:08 +0900666 pdc_adjust_pll(host, pll_clock, board_idx);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400667
668 return 0;
669}
670
671/**
672 * pdc_ata_setup_port - setup the mmio address
673 * @port: ata ioports to setup
674 * @base: base address
675 */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900676static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400677{
678 port->cmd_addr =
679 port->data_addr = base;
680 port->feature_addr =
681 port->error_addr = base + 0x05;
682 port->nsect_addr = base + 0x0a;
683 port->lbal_addr = base + 0x0f;
684 port->lbam_addr = base + 0x10;
685 port->lbah_addr = base + 0x15;
686 port->device_addr = base + 0x1a;
687 port->command_addr =
688 port->status_addr = base + 0x1f;
689 port->altstatus_addr =
690 port->ctl_addr = base + 0x81a;
691}
692
693/**
694 * pdc2027x_init_one - PCI probe function
695 * Called when an instance of PCI adapter is inserted.
696 * This function checks whether the hardware is supported,
697 * initialize hardware and register an instance of ata_host to
Tejun Heo5d728822007-04-17 23:44:08 +0900698 * libata. (implements struct pci_driver.probe() )
Jeff Garzik669a5db2006-08-29 18:12:40 -0400699 *
700 * @pdev: instance of pci_dev found
701 * @ent: matching entry in the id_tbl[]
702 */
703static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
704{
Tejun Heocbcdd872007-08-18 13:14:55 +0900705 static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 };
706 static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400707 unsigned int board_idx = (unsigned int) ent->driver_data;
Tejun Heo5d728822007-04-17 23:44:08 +0900708 const struct ata_port_info *ppi[] =
709 { &pdc2027x_port_info[board_idx], NULL };
710 struct ata_host *host;
Al Viro7c250412006-09-25 02:57:57 +0100711 void __iomem *mmio_base;
Tejun Heocbcdd872007-08-18 13:14:55 +0900712 int i, rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400713
Joe Perches06296a12011-04-15 15:52:00 -0700714 ata_print_version_once(&pdev->dev, DRV_VERSION);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400715
Tejun Heo5d728822007-04-17 23:44:08 +0900716 /* alloc host */
717 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
718 if (!host)
719 return -ENOMEM;
720
721 /* acquire resources and fill host */
Tejun Heo24dc5f32007-01-20 16:00:28 +0900722 rc = pcim_enable_device(pdev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400723 if (rc)
724 return rc;
725
Tejun Heo0d5ff562007-02-01 15:06:36 +0900726 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400727 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900728 return rc;
Tejun Heo5d728822007-04-17 23:44:08 +0900729 host->iomap = pcim_iomap_table(pdev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400730
731 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
732 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900733 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400734
735 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
736 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900737 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400738
Tejun Heo5d728822007-04-17 23:44:08 +0900739 mmio_base = host->iomap[PDC_MMIO_BAR];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400740
Tejun Heocbcdd872007-08-18 13:14:55 +0900741 for (i = 0; i < 2; i++) {
742 struct ata_port *ap = host->ports[i];
743
744 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);
745 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];
746
747 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
748 ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd");
749 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400750
Jeff Garzik669a5db2006-08-29 18:12:40 -0400751 //pci_enable_intx(pdev);
752
753 /* initialize adapter */
Tejun Heo5d728822007-04-17 23:44:08 +0900754 if (pdc_hardware_init(host, board_idx) != 0)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900755 return -EIO;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400756
Tejun Heo5d728822007-04-17 23:44:08 +0900757 pci_set_master(pdev);
Tejun Heoc3b28892010-05-19 22:10:21 +0200758 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
Tejun Heo9363c382008-04-07 22:47:16 +0900759 IRQF_SHARED, &pdc2027x_sht);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400760}
761
Bartlomiej Zolnierkiewiczadacaf12011-10-13 12:57:51 +0200762#ifdef CONFIG_PM
763static int pdc2027x_reinit_one(struct pci_dev *pdev)
764{
765 struct ata_host *host = dev_get_drvdata(&pdev->dev);
766 unsigned int board_idx;
767 int rc;
768
769 rc = ata_pci_device_do_resume(pdev);
770 if (rc)
771 return rc;
772
773 if (pdev->device == PCI_DEVICE_ID_PROMISE_20268 ||
774 pdev->device == PCI_DEVICE_ID_PROMISE_20270)
775 board_idx = PDC_UDMA_100;
776 else
777 board_idx = PDC_UDMA_133;
778
779 if (pdc_hardware_init(host, board_idx))
780 return -EIO;
781
782 ata_host_resume(host);
783 return 0;
784}
785#endif
786
Axel Lin2fc75da2012-04-19 13:43:05 +0800787module_pci_driver(pdc2027x_pci_driver);