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Rafał Miłecki8369ae32011-05-09 18:56:46 +02001/*
2 * Broadcom specific AMBA
3 * PCI Core
4 *
Hauke Mehrtens49dc9572012-01-31 00:03:35 +01005 * Copyright 2005, 2011, Broadcom Corporation
Michael Büscheb032b92011-07-04 20:50:05 +02006 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +01007 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
Rafał Miłecki8369ae32011-05-09 18:56:46 +02008 *
9 * Licensed under the GNU/GPL. See COPYING for details.
10 */
11
12#include "bcma_private.h"
Paul Gortmaker44a8e372011-07-27 21:21:04 -040013#include <linux/export.h>
Rafał Miłecki8369ae32011-05-09 18:56:46 +020014#include <linux/bcma/bcma.h>
15
16/**************************************************
17 * R/W ops.
18 **************************************************/
19
Hauke Mehrtens4b259a52012-01-31 00:03:33 +010020u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
Rafał Miłecki8369ae32011-05-09 18:56:46 +020021{
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010022 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
23 pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
24 return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020025}
26
Rafał Miłecki8369ae32011-05-09 18:56:46 +020027static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
28{
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010029 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
30 pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
31 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020032}
Rafał Miłecki8369ae32011-05-09 18:56:46 +020033
34static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
35{
Rafał Miłecki8369ae32011-05-09 18:56:46 +020036 u32 v;
37 int i;
38
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010039 v = BCMA_CORE_PCI_MDIODATA_START;
40 v |= BCMA_CORE_PCI_MDIODATA_WRITE;
41 v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
42 BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
43 v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
44 BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
45 v |= BCMA_CORE_PCI_MDIODATA_TA;
Rafał Miłecki8369ae32011-05-09 18:56:46 +020046 v |= (phy << 4);
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010047 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020048
49 udelay(10);
50 for (i = 0; i < 200; i++) {
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010051 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
52 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
Rafał Miłecki8369ae32011-05-09 18:56:46 +020053 break;
54 msleep(1);
55 }
56}
57
58static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
59{
Rafał Miłecki8369ae32011-05-09 18:56:46 +020060 int max_retries = 10;
61 u16 ret = 0;
62 u32 v;
63 int i;
64
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010065 /* enable mdio access to SERDES */
66 v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
67 v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
68 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020069
70 if (pc->core->id.rev >= 10) {
71 max_retries = 200;
72 bcma_pcie_mdio_set_phy(pc, device);
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010073 v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
74 BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
75 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
76 } else {
77 v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
78 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020079 }
80
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010081 v = BCMA_CORE_PCI_MDIODATA_START;
82 v |= BCMA_CORE_PCI_MDIODATA_READ;
83 v |= BCMA_CORE_PCI_MDIODATA_TA;
84
85 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020086 /* Wait for the device to complete the transaction */
87 udelay(10);
Rafał Miłeckif1a9c1e2011-05-12 00:01:47 +020088 for (i = 0; i < max_retries; i++) {
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010089 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
90 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
Rafał Miłecki8369ae32011-05-09 18:56:46 +020091 udelay(10);
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010092 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020093 break;
94 }
95 msleep(1);
96 }
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010097 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020098 return ret;
99}
100
101static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
102 u8 address, u16 data)
103{
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200104 int max_retries = 10;
105 u32 v;
106 int i;
107
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100108 /* enable mdio access to SERDES */
109 v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
110 v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
111 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200112
113 if (pc->core->id.rev >= 10) {
114 max_retries = 200;
115 bcma_pcie_mdio_set_phy(pc, device);
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100116 v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
117 BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
118 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
119 } else {
120 v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
121 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200122 }
123
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100124 v = BCMA_CORE_PCI_MDIODATA_START;
125 v |= BCMA_CORE_PCI_MDIODATA_WRITE;
126 v |= BCMA_CORE_PCI_MDIODATA_TA;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200127 v |= data;
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100128 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200129 /* Wait for the device to complete the transaction */
130 udelay(10);
131 for (i = 0; i < max_retries; i++) {
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100132 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
133 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200134 break;
135 msleep(1);
136 }
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100137 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200138}
139
140/**************************************************
141 * Workarounds.
142 **************************************************/
143
144static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
145{
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100146 u32 tmp;
147
148 tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
149 if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
150 return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
151 BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
152 else
153 return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200154}
155
156static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
157{
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200158 u16 tmp;
159
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100160 bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
161 BCMA_CORE_PCI_SERDES_RX_CTRL,
162 bcma_pcicore_polarity_workaround(pc));
163 tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
164 BCMA_CORE_PCI_SERDES_PLL_CTRL);
165 if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
166 bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
167 BCMA_CORE_PCI_SERDES_PLL_CTRL,
168 tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200169}
170
Hauke Mehrtensec00f372012-04-29 02:18:51 +0200171static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
172{
173 struct bcma_device *core = pc->core;
174 u16 val16, core_index;
175 uint regoff;
176
177 regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
178 core_index = (u16)core->core_index;
179
180 val16 = pcicore_read16(pc, regoff);
181 if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
182 != core_index) {
183 val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
184 (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
185 pcicore_write16(pc, regoff, val16);
186 }
187}
188
Hauke Mehrtens2b2715b2012-04-29 02:18:52 +0200189/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
190/* Needs to happen when coming out of 'standby'/'hibernate' */
191static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
192{
193 u16 val16;
194 uint regoff;
195
196 regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
197
198 val16 = pcicore_read16(pc, regoff);
199
200 if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
201 val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
202 pcicore_write16(pc, regoff, val16);
203 }
204}
205
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200206/**************************************************
207 * Init.
208 **************************************************/
209
Hauke Mehrtensd1a7a8e2012-01-31 00:03:34 +0100210static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200211{
Hauke Mehrtensec00f372012-04-29 02:18:51 +0200212 bcma_core_pci_fixcfg(pc);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200213 bcma_pcicore_serdes_workaround(pc);
Hauke Mehrtens2b2715b2012-04-29 02:18:52 +0200214 bcma_core_pci_config_fixup(pc);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200215}
Rafał Miłecki1de520f2011-05-19 14:08:22 +0200216
Hauke Mehrtensd1a7a8e2012-01-31 00:03:34 +0100217void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
Rafał Miłecki9352f692011-07-05 19:48:26 +0200218{
Hauke Mehrtens517f43e2011-07-23 01:20:07 +0200219 if (pc->setup_done)
220 return;
221
Rafał Miłecki9352f692011-07-05 19:48:26 +0200222#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
Hauke Mehrtens49dc9572012-01-31 00:03:35 +0100223 pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
224 if (pc->hostmode)
Rafał Miłecki9352f692011-07-05 19:48:26 +0200225 bcma_core_pci_hostmode_init(pc);
Rafał Miłecki9352f692011-07-05 19:48:26 +0200226#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
Hauke Mehrtens517f43e2011-07-23 01:20:07 +0200227
Hauke Mehrtens49dc9572012-01-31 00:03:35 +0100228 if (!pc->hostmode)
229 bcma_core_pci_clientmode_init(pc);
Rafał Miłecki9352f692011-07-05 19:48:26 +0200230}
231
Rafał Miłecki1de520f2011-05-19 14:08:22 +0200232int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
233 bool enable)
234{
Hauke Mehrtense7027072012-06-05 20:58:20 +0200235 struct pci_dev *pdev;
Rafał Miłecki1de520f2011-05-19 14:08:22 +0200236 u32 coremask, tmp;
Hauke Mehrtensecd177c2011-07-23 01:20:08 +0200237 int err = 0;
238
Hauke Mehrtense7027072012-06-05 20:58:20 +0200239 if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
Hauke Mehrtensecd177c2011-07-23 01:20:08 +0200240 /* This bcma device is not on a PCI host-bus. So the IRQs are
241 * not routed through the PCI core.
242 * So we must not enable routing through the PCI core. */
243 goto out;
244 }
Rafał Miłecki1de520f2011-05-19 14:08:22 +0200245
Hauke Mehrtense7027072012-06-05 20:58:20 +0200246 pdev = pc->core->bus->host_pci;
247
Rafał Miłecki1de520f2011-05-19 14:08:22 +0200248 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
249 if (err)
250 goto out;
251
252 coremask = BIT(core->core_index) << 8;
253 if (enable)
254 tmp |= coremask;
255 else
256 tmp &= ~coremask;
257
258 err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
259
260out:
261 return err;
262}
Rafał Miłecki440ca982011-06-18 01:01:59 +0200263EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
Hauke Mehrtens29f6b3d2012-04-29 02:18:50 +0200264
265void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
266{
267 u32 w;
268
269 w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
270 if (extend)
271 w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
272 else
273 w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
274 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
275 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
276}
277EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);