blob: c79869d4a652d78507e06ae3987701cae8ab0d81 [file] [log] [blame]
Linas Vepstas172ca922005-11-03 18:50:04 -06001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
Gavin Shancb3bc9d2012-02-27 20:03:51 +00003 * Copyright 2001-2012 IBM Corporation.
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
Linas Vepstas172ca922005-11-03 18:50:04 -06009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Linas Vepstas172ca922005-11-03 18:50:04 -060014 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070015 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +000020#ifndef _POWERPC_EEH_H
21#define _POWERPC_EEH_H
Arnd Bergmann88ced032005-12-16 22:43:46 +010022#ifdef __KERNEL__
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/string.h>
Gavin Shan5a719782013-06-20 13:21:01 +080027#include <linux/time.h>
Gavin Shan05ec4242014-06-10 11:41:55 +100028#include <linux/atomic.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30struct pci_dev;
John Rose827c1a62006-02-24 11:34:23 -060031struct pci_bus;
Linus Torvalds1da177e2005-04-16 15:20:36 -070032struct device_node;
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
34#ifdef CONFIG_EEH
35
Gavin Shan8a5ad352014-04-24 18:00:17 +100036/* EEH subsystem flags */
Gavin Shandc561fb2014-07-17 14:41:39 +100037#define EEH_ENABLED 0x01 /* EEH enabled */
38#define EEH_FORCE_DISABLED 0x02 /* EEH disabled */
39#define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */
40#define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */
41#define EEH_ENABLE_IO_FOR_LOG 0x10 /* Enable IO for log */
Gavin Shan8a5ad352014-04-24 18:00:17 +100042
Gavin Shanaa1e6372012-02-27 20:03:53 +000043/*
Gavin Shan26833a52014-04-24 18:00:23 +100044 * Delay for PE reset, all in ms
45 *
46 * PCI specification has reset hold time of 100 milliseconds.
47 * We have 250 milliseconds here. The PCI bus settlement time
48 * is specified as 1.5 seconds and we have 1.8 seconds.
49 */
50#define EEH_PE_RST_HOLD_TIME 250
51#define EEH_PE_RST_SETTLE_TIME 1800
52
53/*
Gavin Shan968f9682012-09-07 22:44:05 +000054 * The struct is used to trace PE related EEH functionality.
55 * In theory, there will have one instance of the struct to
56 * be created against particular PE. In nature, PEs corelate
57 * to each other. the struct has to reflect that hierarchy in
58 * order to easily pick up those affected PEs when one particular
59 * PE has EEH errors.
60 *
61 * Also, one particular PE might be composed of PCI device, PCI
62 * bus and its subordinate components. The struct also need ship
63 * the information. Further more, one particular PE is only meaingful
64 * in the corresponding PHB. Therefore, the root PEs should be created
65 * against existing PHBs in on-to-one fashion.
66 */
Gavin Shan5efc3ad2012-09-11 19:16:16 +000067#define EEH_PE_INVALID (1 << 0) /* Invalid */
68#define EEH_PE_PHB (1 << 1) /* PHB PE */
69#define EEH_PE_DEVICE (1 << 2) /* Device PE */
70#define EEH_PE_BUS (1 << 3) /* Bus PE */
Gavin Shan968f9682012-09-07 22:44:05 +000071
72#define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */
73#define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */
Gavin Shand0914f52014-04-24 18:00:12 +100074#define EEH_PE_RESET (1 << 2) /* PE reset in progress */
Gavin Shan968f9682012-09-07 22:44:05 +000075
Gavin Shan807a8272013-07-24 10:24:55 +080076#define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */
77
Gavin Shan968f9682012-09-07 22:44:05 +000078struct eeh_pe {
79 int type; /* PE type: PHB/Bus/Device */
80 int state; /* PE EEH dependent mode */
81 int config_addr; /* Traditional PCI address */
82 int addr; /* PE configuration address */
83 struct pci_controller *phb; /* Associated PHB */
Gavin Shan8cdb2832013-06-20 13:20:55 +080084 struct pci_bus *bus; /* Top PCI bus for bus PE */
Gavin Shan968f9682012-09-07 22:44:05 +000085 int check_count; /* Times of ignored error */
86 int freeze_count; /* Times of froze up */
Gavin Shan5a719782013-06-20 13:21:01 +080087 struct timeval tstamp; /* Time on first-time freeze */
Gavin Shan968f9682012-09-07 22:44:05 +000088 int false_positives; /* Times of reported #ff's */
Gavin Shan05ec4242014-06-10 11:41:55 +100089 atomic_t pass_dev_cnt; /* Count of passed through devs */
Gavin Shan968f9682012-09-07 22:44:05 +000090 struct eeh_pe *parent; /* Parent PE */
Gavin Shanbb593c02014-07-17 14:41:43 +100091 void *data; /* PE auxillary data */
Gavin Shan968f9682012-09-07 22:44:05 +000092 struct list_head child_list; /* Link PE to the child list */
93 struct list_head edevs; /* Link list of EEH devices */
94 struct list_head child; /* Child PEs */
95};
96
Gavin Shan9feed422013-07-24 10:24:56 +080097#define eeh_pe_for_each_dev(pe, edev, tmp) \
98 list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
Gavin Shan5b663522012-09-07 22:44:12 +000099
Gavin Shan05ec4242014-06-10 11:41:55 +1000100static inline bool eeh_pe_passed(struct eeh_pe *pe)
101{
102 return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
103}
104
Gavin Shan968f9682012-09-07 22:44:05 +0000105/*
Gavin Shaneb740b52012-02-27 20:04:04 +0000106 * The struct is used to trace EEH state for the associated
107 * PCI device node or PCI device. In future, it might
108 * represent PE as well so that the EEH device to form
109 * another tree except the currently existing tree of PCI
110 * buses and PCI devices
111 */
Gavin Shan4b83bd42013-07-24 10:24:59 +0800112#define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */
113#define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */
114#define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */
115#define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */
116#define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */
Gavin Shaneb740b52012-02-27 20:04:04 +0000117
Gavin Shanf26c7a02014-01-12 14:13:45 +0800118#define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */
119#define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */
Gavin Shand2b0f6f2014-04-24 18:00:19 +1000120#define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */
Gavin Shanab55d212013-07-24 10:25:01 +0800121
Gavin Shaneb740b52012-02-27 20:04:04 +0000122struct eeh_dev {
123 int mode; /* EEH mode */
124 int class_code; /* Class code of the device */
125 int config_addr; /* Config address */
126 int pe_config_addr; /* PE config address */
Gavin Shaneb740b52012-02-27 20:04:04 +0000127 u32 config_space[16]; /* Saved PCI config space */
Gavin Shan2a18dfc2014-04-24 18:00:16 +1000128 int pcix_cap; /* Saved PCIx capability */
129 int pcie_cap; /* Saved PCIe capability */
130 int aer_cap; /* Saved AER capability */
Gavin Shan968f9682012-09-07 22:44:05 +0000131 struct eeh_pe *pe; /* Associated PE */
132 struct list_head list; /* Form link list in the PE */
Gavin Shaneb740b52012-02-27 20:04:04 +0000133 struct pci_controller *phb; /* Associated PHB */
134 struct device_node *dn; /* Associated device node */
135 struct pci_dev *pdev; /* Associated PCI device */
Gavin Shanf5c57712013-07-24 10:24:58 +0800136 struct pci_bus *bus; /* PCI bus for partial hotplug */
Gavin Shaneb740b52012-02-27 20:04:04 +0000137};
138
139static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
140{
Gavin Shan2d5c1212013-06-05 15:34:03 +0800141 return edev ? edev->dn : NULL;
Gavin Shaneb740b52012-02-27 20:04:04 +0000142}
143
144static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
145{
Gavin Shan2d5c1212013-06-05 15:34:03 +0800146 return edev ? edev->pdev : NULL;
Gavin Shaneb740b52012-02-27 20:04:04 +0000147}
148
Wei Yang2a582222014-09-17 10:48:26 +0800149static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
150{
151 return edev ? edev->pe : NULL;
152}
153
Gavin Shan7e4e7862014-01-15 13:16:11 +0800154/* Return values from eeh_ops::next_error */
155enum {
156 EEH_NEXT_ERR_NONE = 0,
157 EEH_NEXT_ERR_INF,
158 EEH_NEXT_ERR_FROZEN_PE,
159 EEH_NEXT_ERR_FENCED_PHB,
160 EEH_NEXT_ERR_DEAD_PHB,
161 EEH_NEXT_ERR_DEAD_IOC
162};
163
Gavin Shaneb740b52012-02-27 20:04:04 +0000164/*
Gavin Shanaa1e6372012-02-27 20:03:53 +0000165 * The struct is used to trace the registered EEH operation
166 * callback functions. Actually, those operation callback
167 * functions are heavily platform dependent. That means the
168 * platform should register its own EEH operation callback
169 * functions before any EEH further operations.
170 */
Gavin Shan8fb8f702012-02-27 20:03:55 +0000171#define EEH_OPT_DISABLE 0 /* EEH disable */
172#define EEH_OPT_ENABLE 1 /* EEH enable */
173#define EEH_OPT_THAW_MMIO 2 /* MMIO enable */
174#define EEH_OPT_THAW_DMA 3 /* DMA enable */
Gavin Shaneb594a42012-02-27 20:03:57 +0000175#define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */
176#define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */
177#define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */
178#define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */
179#define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */
180#define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */
181#define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */
Gavin Shan212d16c2014-06-10 11:41:56 +1000182#define EEH_PE_STATE_NORMAL 0 /* Normal state */
183#define EEH_PE_STATE_RESET 1 /* PE reset asserted */
184#define EEH_PE_STATE_STOPPED_IO_DMA 2 /* Frozen PE */
185#define EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA, Enabled IO */
186#define EEH_PE_STATE_UNAVAIL 5 /* Unavailable */
Gavin Shan26524812012-02-27 20:03:59 +0000187#define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */
188#define EEH_RESET_HOT 1 /* Hot reset */
189#define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */
Gavin Shan8d633292012-02-27 20:04:00 +0000190#define EEH_LOG_TEMP 1 /* EEH temporary error log */
191#define EEH_LOG_PERM 2 /* EEH permanent error log */
Gavin Shaneb594a42012-02-27 20:03:57 +0000192
Gavin Shanaa1e6372012-02-27 20:03:53 +0000193struct eeh_ops {
194 char *name;
195 int (*init)(void);
Gavin Shan21fd21f2013-06-20 13:20:57 +0800196 int (*post_init)(void);
Gavin Shand7bb8862012-09-07 22:44:21 +0000197 void* (*of_probe)(struct device_node *dn, void *flag);
Gavin Shan51fb5f52013-06-20 13:20:56 +0800198 int (*dev_probe)(struct pci_dev *dev, void *flag);
Gavin Shan371a3952012-09-07 22:44:14 +0000199 int (*set_option)(struct eeh_pe *pe, int option);
200 int (*get_pe_addr)(struct eeh_pe *pe);
201 int (*get_state)(struct eeh_pe *pe, int *state);
202 int (*reset)(struct eeh_pe *pe, int option);
203 int (*wait_state)(struct eeh_pe *pe, int max_wait);
204 int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
205 int (*configure_bridge)(struct eeh_pe *pe);
Gavin Shan37804442012-02-27 20:04:11 +0000206 int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
207 int (*write_config)(struct device_node *dn, int where, int size, u32 val);
Gavin Shan8a6b1bc2013-06-20 13:21:04 +0800208 int (*next_error)(struct eeh_pe **pe);
Gavin Shan1d350542014-01-03 17:47:12 +0800209 int (*restore_config)(struct device_node *dn);
Gavin Shanaa1e6372012-02-27 20:03:53 +0000210};
211
Gavin Shan8a5ad352014-04-24 18:00:17 +1000212extern int eeh_subsystem_flags;
Gavin Shanaa1e6372012-02-27 20:03:53 +0000213extern struct eeh_ops *eeh_ops;
Gavin Shan49075812013-06-20 13:21:03 +0800214extern raw_spinlock_t confirm_error_lock;
Gavin Shand7bb8862012-09-07 22:44:21 +0000215
Gavin Shan05b17212014-07-17 14:41:38 +1000216static inline void eeh_add_flag(int flag)
Gavin Shand7bb8862012-09-07 22:44:21 +0000217{
Gavin Shan8a5ad352014-04-24 18:00:17 +1000218 eeh_subsystem_flags |= flag;
Gavin Shand7bb8862012-09-07 22:44:21 +0000219}
220
Gavin Shan05b17212014-07-17 14:41:38 +1000221static inline void eeh_clear_flag(int flag)
Gavin Shand7bb8862012-09-07 22:44:21 +0000222{
Gavin Shan05b17212014-07-17 14:41:38 +1000223 eeh_subsystem_flags &= ~flag;
Gavin Shand7bb8862012-09-07 22:44:21 +0000224}
225
Gavin Shan05b17212014-07-17 14:41:38 +1000226static inline bool eeh_has_flag(int flag)
Gavin Shand7bb8862012-09-07 22:44:21 +0000227{
Gavin Shan05b17212014-07-17 14:41:38 +1000228 return !!(eeh_subsystem_flags & flag);
229}
230
231static inline bool eeh_enabled(void)
232{
233 if (eeh_has_flag(EEH_FORCE_DISABLED) ||
234 !eeh_has_flag(EEH_ENABLED))
235 return false;
236
237 return true;
Gavin Shand7bb8862012-09-07 22:44:21 +0000238}
Gavin Shan646a8492012-09-07 22:44:06 +0000239
Gavin Shan49075812013-06-20 13:21:03 +0800240static inline void eeh_serialize_lock(unsigned long *flags)
241{
242 raw_spin_lock_irqsave(&confirm_error_lock, *flags);
243}
244
245static inline void eeh_serialize_unlock(unsigned long flags)
246{
247 raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
248}
249
Gavin Shancb3bc9d2012-02-27 20:03:51 +0000250/*
251 * Max number of EEH freezes allowed before we consider the device
252 * to be permanently disabled.
253 */
Linas Vepstas172ca922005-11-03 18:50:04 -0600254#define EEH_MAX_ALLOWED_FREEZES 5
255
Gavin Shan22f4ab12012-09-07 22:44:08 +0000256typedef void *(*eeh_traverse_func)(void *data, void *flag);
Gavin Shanbb593c02014-07-17 14:41:43 +1000257void eeh_set_pe_aux_size(int size);
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -0800258int eeh_phb_pe_create(struct pci_controller *phb);
Gavin Shan9ff67432013-06-20 13:20:53 +0800259struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
Gavin Shan01566802013-06-20 13:20:54 +0800260struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
Gavin Shan9b843482012-09-07 22:44:09 +0000261int eeh_add_to_parent_pe(struct eeh_dev *edev);
Gavin Shan807a8272013-07-24 10:24:55 +0800262int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
Gavin Shan5a719782013-06-20 13:21:01 +0800263void eeh_pe_update_time_stamp(struct eeh_pe *pe);
Gavin Shanf5c57712013-07-24 10:24:58 +0800264void *eeh_pe_traverse(struct eeh_pe *root,
265 eeh_traverse_func fn, void *flag);
Gavin Shan9e6d2cf2012-09-07 22:44:15 +0000266void *eeh_pe_dev_traverse(struct eeh_pe *root,
267 eeh_traverse_func fn, void *flag);
268void eeh_pe_restore_bars(struct eeh_pe *pe);
Gavin Shan357b2f32014-06-11 18:26:44 +1000269const char *eeh_pe_loc_get(struct eeh_pe *pe);
Gavin Shan9b3c76f2012-09-07 22:44:19 +0000270struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
Gavin Shan55037d12012-09-07 22:44:07 +0000271
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -0800272void *eeh_dev_init(struct device_node *dn, void *data);
273void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
Gavin Shaneeb63612013-06-27 13:46:47 +0800274int eeh_init(void);
Gavin Shanaa1e6372012-02-27 20:03:53 +0000275int __init eeh_ops_register(struct eeh_ops *ops);
276int __exit eeh_ops_unregister(const char *name);
Gavin Shan3e938052014-09-30 12:38:50 +1000277int eeh_check_failure(const volatile void __iomem *token);
Gavin Shanf8f7d632012-09-07 22:44:22 +0000278int eeh_dev_check_failure(struct eeh_dev *edev);
Gavin Shaneeb63612013-06-27 13:46:47 +0800279void eeh_addr_cache_build(void);
Gavin Shanf2856492013-07-24 10:24:52 +0800280void eeh_add_device_early(struct device_node *);
Linas Vepstase2a296e2005-11-03 18:51:31 -0600281void eeh_add_device_tree_early(struct device_node *);
Gavin Shanf2856492013-07-24 10:24:52 +0800282void eeh_add_device_late(struct pci_dev *);
John Rose827c1a62006-02-24 11:34:23 -0600283void eeh_add_device_tree_late(struct pci_bus *);
Thadeu Lima de Souza Cascardo6a040ce2012-12-28 09:13:19 +0000284void eeh_add_sysfs_files(struct pci_bus *);
Gavin Shan807a8272013-07-24 10:24:55 +0800285void eeh_remove_device(struct pci_dev *);
Gavin Shan212d16c2014-06-10 11:41:56 +1000286int eeh_dev_open(struct pci_dev *pdev);
287void eeh_dev_release(struct pci_dev *pdev);
288struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
289int eeh_pe_set_option(struct eeh_pe *pe, int option);
290int eeh_pe_get_state(struct eeh_pe *pe);
291int eeh_pe_reset(struct eeh_pe *pe, int option);
292int eeh_pe_configure(struct eeh_pe *pe);
Linas Vepstase2a296e2005-11-03 18:51:31 -0600293
294/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
296 *
297 * If this macro yields TRUE, the caller relays to eeh_check_failure()
298 * which does further tests out of line.
299 */
Gavin Shan2ec5a0a2014-02-12 15:24:55 +0800300#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled())
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301
302/*
303 * Reads from a device which has been isolated by EEH will return
304 * all 1s. This macro gives an all-1s value of the given size (in
305 * bytes: 1, 2, or 4) for comparing with the result of a read.
306 */
307#define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
308
309#else /* !CONFIG_EEH */
Gavin Shaneb740b52012-02-27 20:04:04 +0000310
Gavin Shan2ec5a0a2014-02-12 15:24:55 +0800311static inline bool eeh_enabled(void)
312{
313 return false;
314}
315
Gavin Shan51fb5f52013-06-20 13:20:56 +0800316static inline int eeh_init(void)
317{
318 return 0;
319}
320
Gavin Shaneb740b52012-02-27 20:04:04 +0000321static inline void *eeh_dev_init(struct device_node *dn, void *data)
322{
323 return NULL;
324}
325
326static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
327
Gavin Shan3e938052014-09-30 12:38:50 +1000328static inline int eeh_check_failure(const volatile void __iomem *token)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329{
Gavin Shan3e938052014-09-30 12:38:50 +1000330 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331}
332
Gavin Shanf8f7d632012-09-07 22:44:22 +0000333#define eeh_dev_check_failure(x) (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334
Gavin Shan3ab96a02012-09-07 22:44:23 +0000335static inline void eeh_addr_cache_build(void) { }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336
Gavin Shanf2856492013-07-24 10:24:52 +0800337static inline void eeh_add_device_early(struct device_node *dn) { }
338
Haren Myneni022930e2005-12-27 18:58:29 -0800339static inline void eeh_add_device_tree_early(struct device_node *dn) { }
340
Gavin Shanf2856492013-07-24 10:24:52 +0800341static inline void eeh_add_device_late(struct pci_dev *dev) { }
342
John Rose827c1a62006-02-24 11:34:23 -0600343static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
344
Thadeu Lima de Souza Cascardo6a040ce2012-12-28 09:13:19 +0000345static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
346
Gavin Shan807a8272013-07-24 10:24:55 +0800347static inline void eeh_remove_device(struct pci_dev *dev) { }
Gavin Shan646a8492012-09-07 22:44:06 +0000348
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349#define EEH_POSSIBLE_ERROR(val, type) (0)
350#define EEH_IO_ERROR_VALUE(size) (-1UL)
351#endif /* CONFIG_EEH */
352
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +0000353#ifdef CONFIG_PPC64
Linas Vepstas172ca922005-11-03 18:50:04 -0600354/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355 * MMIO read/write operations with EEH support.
356 */
357static inline u8 eeh_readb(const volatile void __iomem *addr)
358{
359 u8 val = in_8(addr);
360 if (EEH_POSSIBLE_ERROR(val, u8))
Gavin Shan3e938052014-09-30 12:38:50 +1000361 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 return val;
363}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364
365static inline u16 eeh_readw(const volatile void __iomem *addr)
366{
367 u16 val = in_le16(addr);
368 if (EEH_POSSIBLE_ERROR(val, u16))
Gavin Shan3e938052014-09-30 12:38:50 +1000369 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 return val;
371}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372
373static inline u32 eeh_readl(const volatile void __iomem *addr)
374{
375 u32 val = in_le32(addr);
376 if (EEH_POSSIBLE_ERROR(val, u32))
Gavin Shan3e938052014-09-30 12:38:50 +1000377 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 return val;
379}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380
381static inline u64 eeh_readq(const volatile void __iomem *addr)
382{
383 u64 val = in_le64(addr);
384 if (EEH_POSSIBLE_ERROR(val, u64))
Gavin Shan3e938052014-09-30 12:38:50 +1000385 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386 return val;
387}
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100388
389static inline u16 eeh_readw_be(const volatile void __iomem *addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390{
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100391 u16 val = in_be16(addr);
392 if (EEH_POSSIBLE_ERROR(val, u16))
Gavin Shan3e938052014-09-30 12:38:50 +1000393 eeh_check_failure(addr);
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100394 return val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395}
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100396
397static inline u32 eeh_readl_be(const volatile void __iomem *addr)
398{
399 u32 val = in_be32(addr);
400 if (EEH_POSSIBLE_ERROR(val, u32))
Gavin Shan3e938052014-09-30 12:38:50 +1000401 eeh_check_failure(addr);
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100402 return val;
403}
404
405static inline u64 eeh_readq_be(const volatile void __iomem *addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406{
407 u64 val = in_be64(addr);
408 if (EEH_POSSIBLE_ERROR(val, u64))
Gavin Shan3e938052014-09-30 12:38:50 +1000409 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410 return val;
411}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412
Benjamin Herrenschmidt68a64352006-11-13 09:27:39 +1100413static inline void eeh_memcpy_fromio(void *dest, const
414 volatile void __iomem *src,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415 unsigned long n)
416{
Benjamin Herrenschmidt68a64352006-11-13 09:27:39 +1100417 _memcpy_fromio(dest, src, n);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418
419 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes
420 * were copied. Check all four bytes.
421 */
Benjamin Herrenschmidt68a64352006-11-13 09:27:39 +1100422 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
Gavin Shan3e938052014-09-30 12:38:50 +1000423 eeh_check_failure(src);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424}
425
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426/* in-string eeh macros */
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100427static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
428 int ns)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429{
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100430 _insb(addr, buf, ns);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
Gavin Shan3e938052014-09-30 12:38:50 +1000432 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433}
434
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100435static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
436 int ns)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437{
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100438 _insw(addr, buf, ns);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
Gavin Shan3e938052014-09-30 12:38:50 +1000440 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441}
442
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100443static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
444 int nl)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445{
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100446 _insl(addr, buf, nl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
Gavin Shan3e938052014-09-30 12:38:50 +1000448 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449}
450
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +0000451#endif /* CONFIG_PPC64 */
Arnd Bergmann88ced032005-12-16 22:43:46 +0100452#endif /* __KERNEL__ */
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +0000453#endif /* _POWERPC_EEH_H */