Gregory Bean | 37a298f | 2010-04-30 22:22:07 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H |
| 31 | #define __ARCH_ARM_MACH_MSM_CLOCK_7X30_H |
| 32 | |
| 33 | enum { |
| 34 | L_7X30_NONE_CLK = -1, |
| 35 | L_7X30_ADM_CLK, |
| 36 | L_7X30_I2C_CLK, |
| 37 | L_7X30_I2C_2_CLK, |
| 38 | L_7X30_QUP_I2C_CLK, |
| 39 | L_7X30_UART1DM_CLK, |
| 40 | L_7X30_UART1DM_P_CLK, |
| 41 | L_7X30_UART2DM_CLK, |
| 42 | L_7X30_UART2DM_P_CLK, |
| 43 | L_7X30_EMDH_CLK, |
| 44 | L_7X30_EMDH_P_CLK, |
| 45 | L_7X30_PMDH_CLK, |
| 46 | L_7X30_PMDH_P_CLK, |
| 47 | L_7X30_GRP_2D_CLK, |
| 48 | L_7X30_GRP_2D_P_CLK, |
| 49 | L_7X30_GRP_3D_SRC_CLK, |
| 50 | L_7X30_GRP_3D_CLK, |
| 51 | L_7X30_GRP_3D_P_CLK, |
| 52 | L_7X30_IMEM_CLK, |
| 53 | L_7X30_SDC1_CLK, |
| 54 | L_7X30_SDC1_P_CLK, |
| 55 | L_7X30_SDC2_CLK, |
| 56 | L_7X30_SDC2_P_CLK, |
| 57 | L_7X30_SDC3_CLK, |
| 58 | L_7X30_SDC3_P_CLK, |
| 59 | L_7X30_SDC4_CLK, |
| 60 | L_7X30_SDC4_P_CLK, |
| 61 | L_7X30_MDP_CLK, |
| 62 | L_7X30_MDP_P_CLK, |
| 63 | L_7X30_MDP_LCDC_PCLK_CLK, |
| 64 | L_7X30_MDP_LCDC_PAD_PCLK_CLK, |
| 65 | L_7X30_MDP_VSYNC_CLK, |
| 66 | L_7X30_MI2S_CODEC_RX_M_CLK, |
| 67 | L_7X30_MI2S_CODEC_RX_S_CLK, |
| 68 | L_7X30_MI2S_CODEC_TX_M_CLK, |
| 69 | L_7X30_MI2S_CODEC_TX_S_CLK, |
| 70 | L_7X30_MI2S_M_CLK, |
| 71 | L_7X30_MI2S_S_CLK, |
| 72 | L_7X30_LPA_CODEC_CLK, |
| 73 | L_7X30_LPA_CORE_CLK, |
| 74 | L_7X30_LPA_P_CLK, |
| 75 | L_7X30_MIDI_CLK, |
| 76 | L_7X30_MDC_CLK, |
| 77 | L_7X30_ROTATOR_IMEM_CLK, |
| 78 | L_7X30_ROTATOR_P_CLK, |
| 79 | L_7X30_SDAC_M_CLK, |
| 80 | L_7X30_SDAC_CLK, |
| 81 | L_7X30_UART1_CLK, |
| 82 | L_7X30_UART2_CLK, |
| 83 | L_7X30_UART3_CLK, |
| 84 | L_7X30_TV_CLK, |
| 85 | L_7X30_TV_DAC_CLK, |
| 86 | L_7X30_TV_ENC_CLK, |
| 87 | L_7X30_HDMI_CLK, |
| 88 | L_7X30_TSIF_REF_CLK, |
| 89 | L_7X30_TSIF_P_CLK, |
| 90 | L_7X30_USB_HS_SRC_CLK, |
| 91 | L_7X30_USB_HS_CLK, |
| 92 | L_7X30_USB_HS_CORE_CLK, |
| 93 | L_7X30_USB_HS_P_CLK, |
| 94 | L_7X30_USB_HS2_CLK, |
| 95 | L_7X30_USB_HS2_CORE_CLK, |
| 96 | L_7X30_USB_HS2_P_CLK, |
| 97 | L_7X30_USB_HS3_CLK, |
| 98 | L_7X30_USB_HS3_CORE_CLK, |
| 99 | L_7X30_USB_HS3_P_CLK, |
| 100 | L_7X30_VFE_CLK, |
| 101 | L_7X30_VFE_P_CLK, |
| 102 | L_7X30_VFE_MDC_CLK, |
| 103 | L_7X30_VFE_CAMIF_CLK, |
| 104 | L_7X30_CAMIF_PAD_P_CLK, |
| 105 | L_7X30_CAM_M_CLK, |
| 106 | L_7X30_JPEG_CLK, |
| 107 | L_7X30_JPEG_P_CLK, |
| 108 | L_7X30_VPE_CLK, |
| 109 | L_7X30_MFC_CLK, |
| 110 | L_7X30_MFC_DIV2_CLK, |
| 111 | L_7X30_MFC_P_CLK, |
| 112 | L_7X30_SPI_CLK, |
| 113 | L_7X30_SPI_P_CLK, |
| 114 | L_7X30_CSI0_CLK, |
| 115 | L_7X30_CSI0_VFE_CLK, |
| 116 | L_7X30_CSI0_P_CLK, |
| 117 | L_7X30_CSI1_CLK, |
| 118 | L_7X30_CSI1_VFE_CLK, |
| 119 | L_7X30_CSI1_P_CLK, |
| 120 | L_7X30_GLBL_ROOT_CLK, |
| 121 | |
| 122 | L_7X30_AXI_LI_VG_CLK, |
| 123 | L_7X30_AXI_LI_GRP_CLK, |
| 124 | L_7X30_AXI_LI_JPEG_CLK, |
| 125 | L_7X30_AXI_GRP_2D_CLK, |
| 126 | L_7X30_AXI_MFC_CLK, |
| 127 | L_7X30_AXI_VPE_CLK, |
| 128 | L_7X30_AXI_LI_VFE_CLK, |
| 129 | L_7X30_AXI_LI_APPS_CLK, |
| 130 | L_7X30_AXI_MDP_CLK, |
| 131 | L_7X30_AXI_IMEM_CLK, |
| 132 | L_7X30_AXI_LI_ADSP_A_CLK, |
| 133 | L_7X30_AXI_ROTATOR_CLK, |
| 134 | |
| 135 | L_7X30_NR_CLKS |
| 136 | }; |
| 137 | |
| 138 | struct clk_ops; |
| 139 | extern struct clk_ops clk_ops_7x30; |
| 140 | |
| 141 | struct clk_ops *clk_7x30_is_local(uint32_t id); |
| 142 | int clk_7x30_init(void); |
| 143 | |
| 144 | void pll_enable(uint32_t pll); |
| 145 | void pll_disable(uint32_t pll); |
| 146 | |
| 147 | extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable); |
| 148 | |
| 149 | #define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) { \ |
| 150 | .name = clk_name, \ |
| 151 | .id = L_7X30_##clk_id, \ |
| 152 | .remote_id = P_##clk_id, \ |
| 153 | .flags = clk_flags, \ |
| 154 | .dev = clk_dev, \ |
| 155 | .dbg_name = #clk_id, \ |
| 156 | } |
| 157 | |
| 158 | #define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) { \ |
| 159 | .name = clk_name, \ |
| 160 | .id = L_7X30_##l_id, \ |
| 161 | .remote_id = P_##r_id, \ |
| 162 | .flags = clk_flags, \ |
| 163 | .dev = clk_dev, \ |
| 164 | .dbg_name = #l_id, \ |
| 165 | } |
| 166 | |
| 167 | #endif |
| 168 | |