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Tony Lindgren670c1042006-04-02 17:46:25 +01001/*
2 * linux/arch/arm/mach-omap2/sleep.S
3 *
4 * (C) Copyright 2004
5 * Texas Instruments, <www.ti.com>
6 * Richard Woodruff <r-woodruff2@ti.com>
7 *
Tony Lindgren1835f1d2008-10-06 15:49:15 +03008 * (C) Copyright 2006 Nokia Corporation
9 * Fixed idle loop sleep
10 * Igor Stoppa <igor.stoppa@nokia.com>
11 *
Tony Lindgren670c1042006-04-02 17:46:25 +010012 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Tony Lindgren670c1042006-04-02 17:46:25 +010028#include <linux/linkage.h>
29#include <asm/assembler.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010030#include <mach/io.h>
Tony Lindgren670c1042006-04-02 17:46:25 +010031
Tony Lindgrence491cf2009-10-20 09:40:47 -070032#include <plat/omap24xx.h>
Tony Lindgren1835f1d2008-10-06 15:49:15 +030033
Paul Walmsley44595982008-03-18 10:04:51 +020034#include "sdrc.h"
Tony Lindgren670c1042006-04-02 17:46:25 +010035
Paul Walmsley44595982008-03-18 10:04:51 +020036/* First address of reserved address space? apparently valid for OMAP2 & 3 */
Tony Lindgren670c1042006-04-02 17:46:25 +010037#define A_SDRC0_V (0xC0000000)
Tony Lindgren670c1042006-04-02 17:46:25 +010038
39 .text
40
41/*
42 * Forces OMAP into idle state
43 *
44 * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI
45 * for normal idles.
46 *
47 * Note: This code get's copied to internal SRAM at boot. When the OMAP
48 * wakes up it continues execution at the point it went to sleep.
49 */
50ENTRY(omap24xx_idle_loop_suspend)
51 stmfd sp!, {r0, lr} @ save registers on stack
52 mov r0, #0 @ clear for mcr setup
53 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
54 ldmfd sp!, {r0, pc} @ restore regs and return
55
56ENTRY(omap24xx_idle_loop_suspend_sz)
57 .word . - omap24xx_idle_loop_suspend
58
59/*
Tony Lindgren1835f1d2008-10-06 15:49:15 +030060 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
Tony Lindgren670c1042006-04-02 17:46:25 +010061 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
62 * SDRC.
63 *
64 * Input:
65 * R0 : DLL ctrl value pre-Sleep
Tony Lindgren1835f1d2008-10-06 15:49:15 +030066 * R1 : SDRC_DLLA_CTRL
67 * R2 : SDRC_POWER
Tony Lindgren670c1042006-04-02 17:46:25 +010068 *
69 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
70 * when we get called, but the DLL probably isn't. We will wait a bit more in
71 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
72 * if in unlocked mode.
73 *
74 * For less than 242x-ES2.2 upon wake from a sleep mode where the external
75 * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz
76 * clock can pass into the PRCM can cause problems at DSP and IVA.
77 * To work around this the code will switch to the 32kHz source prior to sleep.
78 * Post sleep we will shift back to using the DPLL. Apparently,
79 * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait
80 * 3x12MHz + 3x32kHz clocks for a full switch.
81 *
82 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored
83 * at wake
84 */
85ENTRY(omap24xx_cpu_suspend)
86 stmfd sp!, {r0 - r12, lr} @ save registers on stack
Tony Lindgren1835f1d2008-10-06 15:49:15 +030087 mov r3, #0x0 @ clear for mcr call
Tony Lindgren670c1042006-04-02 17:46:25 +010088 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
89 nop
90 nop
Tony Lindgren1835f1d2008-10-06 15:49:15 +030091 ldr r4, [r2] @ read SDRC_POWER
Tony Lindgren670c1042006-04-02 17:46:25 +010092 orr r4, r4, #0x40 @ enable self refresh on idle req
93 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
Tony Lindgren1835f1d2008-10-06 15:49:15 +030094 str r4, [r2] @ make it so
Tony Lindgren670c1042006-04-02 17:46:25 +010095 nop
Kevin Hilman0dc23d72009-01-29 08:57:18 -080096 mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
Tony Lindgren670c1042006-04-02 17:46:25 +010097 nop
98loop:
99 subs r5, r5, #0x1 @ awake, wait just a bit
100 bne loop
101
Tony Lindgren1835f1d2008-10-06 15:49:15 +0300102 /* The DPLL has to be on before we take the DDR out of self refresh */
Tony Lindgren670c1042006-04-02 17:46:25 +0100103 bic r4, r4, #0x40 @ now clear self refresh bit.
Tony Lindgren1835f1d2008-10-06 15:49:15 +0300104 str r4, [r2] @ write to SDRC_POWER
Tony Lindgren670c1042006-04-02 17:46:25 +0100105 ldr r4, A_SDRC0 @ make a clock happen
Tony Lindgren1835f1d2008-10-06 15:49:15 +0300106 ldr r4, [r4] @ read A_SDRC0
Tony Lindgren670c1042006-04-02 17:46:25 +0100107 nop @ start auto refresh only after clk ok
108 movs r0, r0 @ see if DDR or SDR
Tony Lindgren670c1042006-04-02 17:46:25 +0100109 strne r0, [r1] @ rewrite DLLA to force DLL reload
110 addne r1, r1, #0x8 @ move to DLLB
111 strne r0, [r1] @ rewrite DLLB to force DLL reload
112
113 mov r5, #0x1000
114loop2:
115 subs r5, r5, #0x1
116 bne loop2
117 /* resume*/
118 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
119
Tony Lindgren670c1042006-04-02 17:46:25 +0100120A_SDRC0:
121 .word A_SDRC0_V
Tony Lindgren670c1042006-04-02 17:46:25 +0100122
123ENTRY(omap24xx_cpu_suspend_sz)
124 .word . - omap24xx_cpu_suspend