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Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
Tony Lindgrenc2d43e32008-07-03 12:24:38 +03002 * linux/arch/arm/mach-omap2/sram242x.S
Tony Lindgren1dbae812005-11-10 14:26:51 +00003 *
4 * Omap2 specific functions that need to be run in internal SRAM
5 *
6 * (C) Copyright 2004
7 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
Paul Walmsley1124d2f2010-12-21 21:08:14 -070024 *
25 * Richard Woodruff notes that any changes to this code must be carefully
26 * audited and tested to ensure that they don't cause a TLB miss while
27 * the SDRAM is inaccessible. Such a situation will crash the system
28 * since it will cause the ARM MMU to attempt to walk the page tables.
29 * These crashes may be intermittent.
Tony Lindgren1dbae812005-11-10 14:26:51 +000030 */
Tony Lindgren1dbae812005-11-10 14:26:51 +000031#include <linux/linkage.h>
32#include <asm/assembler.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010033#include <mach/io.h>
34#include <mach/hardware.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000035
Paul Walmsley59fb6592010-12-21 15:30:55 -070036#include "prm2xxx_3xxx.h"
37#include "cm2xxx_3xxx.h"
Tony Lindgrenc2d43e32008-07-03 12:24:38 +030038#include "sdrc.h"
Tony Lindgren1dbae812005-11-10 14:26:51 +000039
40 .text
41
Tony Lindgrenc2d43e32008-07-03 12:24:38 +030042ENTRY(omap242x_sram_ddr_init)
Tony Lindgren1dbae812005-11-10 14:26:51 +000043 stmfd sp!, {r0 - r12, lr} @ save registers on stack
44
45 mov r12, r2 @ capture CS1 vs CS0
46 mov r8, r3 @ capture force parameter
47
48 /* frequency shift down */
Tony Lindgrenc2d43e32008-07-03 12:24:38 +030049 ldr r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
Tony Lindgren1dbae812005-11-10 14:26:51 +000050 mov r3, #0x1 @ value for 1x operation
51 str r3, [r2] @ go to L1-freq operation
52
53 /* voltage shift down */
54 mov r9, #0x1 @ set up for L1 voltage call
55 bl voltage_shift @ go drop voltage
56
57 /* dll lock mode */
Tony Lindgrenc2d43e32008-07-03 12:24:38 +030058 ldr r11, omap242x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
Tony Lindgren1dbae812005-11-10 14:26:51 +000059 ldr r10, [r11] @ get current val
60 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
61 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
62 mvn r9, #0x4 @ mask to get clear bit2
63 and r10, r10, r9 @ clear bit2 for lock mode.
64 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
65 orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz
66 str r10, [r11] @ commit to DLLA_CTRL
67 bl i_dll_wait @ wait for dll to lock
68
69 /* get dll value */
70 add r11, r11, #0x4 @ get addr of status reg
71 ldr r10, [r11] @ get locked value
72
73 /* voltage shift up */
74 mov r9, #0x0 @ shift back to L0-voltage
75 bl voltage_shift @ go raise voltage
76
77 /* frequency shift up */
78 mov r3, #0x2 @ value for 2x operation
79 str r3, [r2] @ go to L0-freq operation
80
81 /* reset entry mode for dllctrl */
82 sub r11, r11, #0x4 @ move from status to ctrl
83 cmp r12, #0x1 @ normalize if cs1 based
84 subeq r11, r11, #0x8 @ possibly back to DLLA
85 cmp r8, #0x1 @ if forced unlock exit
86 orreq r1, r1, #0x4 @ make sure exit with unlocked value
87 str r1, [r11] @ restore DLLA_CTRL high value
88 add r11, r11, #0x8 @ move to DLLB_CTRL addr
89 str r1, [r11] @ set value DLLB_CTRL
90 bl i_dll_wait @ wait for possible lock
91
92 /* set up for return, DDR should be good */
93 str r10, [r0] @ write dll_status and return counter
94 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
95
96 /* ensure the DLL has relocked */
97i_dll_wait:
98 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
99i_dll_delay:
100 subs r4, r4, #0x1
101 bne i_dll_delay
102 mov pc, lr
103
104 /*
105 * shift up or down voltage, use R9 as input to tell level.
106 * wait for it to finish, use 32k sync counter, 1tick=31uS.
107 */
108voltage_shift:
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300109 ldr r4, omap242x_sdi_prcm_voltctrl @ get addr of volt ctrl.
Tony Lindgren1dbae812005-11-10 14:26:51 +0000110 ldr r5, [r4] @ get value.
111 ldr r6, prcm_mask_val @ get value of mask
112 and r5, r5, r6 @ apply mask to clear bits
113 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
114 str r5, [r4] @ set up for change.
115 mov r3, #0x4000 @ get val for force
116 orr r5, r5, r3 @ build value for force
117 str r5, [r4] @ Force transition to L1
118
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300119 ldr r3, omap242x_sdi_timer_32ksynct_cr @ get addr of counter
Tony Lindgren1dbae812005-11-10 14:26:51 +0000120 ldr r5, [r3] @ get value
121 add r5, r5, #0x3 @ give it at most 93uS
122volt_delay:
123 ldr r7, [r3] @ get timer value
124 cmp r5, r7 @ time up?
125 bhi volt_delay @ not yet->branch
126 mov pc, lr @ back to caller.
127
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300128omap242x_sdi_cm_clksel2_pll:
Paul Walmsley44595982008-03-18 10:04:51 +0200129 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300130omap242x_sdi_sdrc_dlla_ctrl:
Paul Walmsley44595982008-03-18 10:04:51 +0200131 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300132omap242x_sdi_prcm_voltctrl:
Tony Lindgren8e3bd352009-05-25 11:26:42 -0700133 .word OMAP2420_PRCM_VOLTCTRL
Tony Lindgren1dbae812005-11-10 14:26:51 +0000134prcm_mask_val:
135 .word 0xFFFF3FFC
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300136omap242x_sdi_timer_32ksynct_cr:
Santosh Shilimkar233fd642009-10-19 15:25:31 -0700137 .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300138ENTRY(omap242x_sram_ddr_init_sz)
139 .word . - omap242x_sram_ddr_init
Tony Lindgren1dbae812005-11-10 14:26:51 +0000140
141/*
142 * Reprograms memory timings.
143 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
144 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
145 */
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300146ENTRY(omap242x_sram_reprogram_sdrc)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000147 stmfd sp!, {r0 - r10, lr} @ save registers on stack
148 mov r3, #0x0 @ clear for mrc call
149 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
150 nop
151 nop
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300152 ldr r6, omap242x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
Tony Lindgren1dbae812005-11-10 14:26:51 +0000153 ldr r5, [r6] @ get value
154 mov r5, r5, lsr #8 @ isolate rfr field and drop burst
155
156 cmp r0, #0x1 @ going to half speed?
157 movne r9, #0x0 @ if up set flag up for pre up, hi volt
158
159 blne voltage_shift_c @ adjust voltage
160
161 cmp r0, #0x1 @ going to half speed (post branch link)
162 moveq r5, r5, lsr #1 @ divide by 2 if to half
163 movne r5, r5, lsl #1 @ mult by 2 if to full
164 mov r5, r5, lsl #8 @ put rfr field back into place
165 add r5, r5, #0x1 @ turn on burst of 1
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300166 ldr r4, omap242x_srs_cm_clksel2_pll @ get address of out reg
Tony Lindgren1dbae812005-11-10 14:26:51 +0000167 ldr r3, [r4] @ get curr value
168 orr r3, r3, #0x3
169 bic r3, r3, #0x3 @ clear lower bits
170 orr r3, r3, r0 @ new state value
171 str r3, [r4] @ set new state (pll/x, x=1 or 2)
172 nop
173 nop
174
175 moveq r9, #0x1 @ if speed down, post down, drop volt
176 bleq voltage_shift_c
177
178 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
179 str r5, [r6] @ set new RFR_1 value
180 add r6, r6, #0x30 @ get RFR_2 addr
181 str r5, [r6] @ set RFR_2
182 nop
183 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
184 bne freq_out @ leave if SDR, no DLL function
185
186 /* With DDR, we need to take care of the DLL for the frequency change */
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300187 ldr r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
Tony Lindgren1dbae812005-11-10 14:26:51 +0000188 str r1, [r2] @ write out new SDRC_DLLA_CTRL
189 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
190 str r1, [r2] @ commit to SDRC_DLLB_CTRL
191 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
192dll_wait:
193 subs r1, r1, #0x1
194 bne dll_wait
195freq_out:
196 ldmfd sp!, {r0 - r10, pc} @ restore regs and return
197
198 /*
199 * shift up or down voltage, use R9 as input to tell level.
200 * wait for it to finish, use 32k sync counter, 1tick=31uS.
201 */
202voltage_shift_c:
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300203 ldr r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl
Tony Lindgren1dbae812005-11-10 14:26:51 +0000204 ldr r8, [r10] @ get value
205 ldr r7, ddr_prcm_mask_val @ get value of mask
206 and r8, r8, r7 @ apply mask to clear bits
207 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
208 str r8, [r10] @ set up for change.
209 mov r7, #0x4000 @ get val for force
210 orr r8, r8, r7 @ build value for force
211 str r8, [r10] @ Force transition to L1
212
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300213 ldr r10, omap242x_srs_timer_32ksynct @ get addr of counter
Tony Lindgren1dbae812005-11-10 14:26:51 +0000214 ldr r8, [r10] @ get value
215 add r8, r8, #0x2 @ give it at most 62uS (min 31+)
216volt_delay_c:
217 ldr r7, [r10] @ get timer value
218 cmp r8, r7 @ time up?
219 bhi volt_delay_c @ not yet->branch
220 mov pc, lr @ back to caller
221
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300222omap242x_srs_cm_clksel2_pll:
Paul Walmsley44595982008-03-18 10:04:51 +0200223 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300224omap242x_srs_sdrc_dlla_ctrl:
Paul Walmsley44595982008-03-18 10:04:51 +0200225 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300226omap242x_srs_sdrc_rfr_ctrl:
Paul Walmsley44595982008-03-18 10:04:51 +0200227 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300228omap242x_srs_prcm_voltctrl:
Tony Lindgren8e3bd352009-05-25 11:26:42 -0700229 .word OMAP2420_PRCM_VOLTCTRL
Tony Lindgren1dbae812005-11-10 14:26:51 +0000230ddr_prcm_mask_val:
231 .word 0xFFFF3FFC
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300232omap242x_srs_timer_32ksynct:
Santosh Shilimkar233fd642009-10-19 15:25:31 -0700233 .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000234
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300235ENTRY(omap242x_sram_reprogram_sdrc_sz)
236 .word . - omap242x_sram_reprogram_sdrc
Tony Lindgren1dbae812005-11-10 14:26:51 +0000237
238/*
239 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
240 */
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300241ENTRY(omap242x_sram_set_prcm)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000242 stmfd sp!, {r0-r12, lr} @ regs to stack
243 adr r4, pbegin @ addr of preload start
244 adr r8, pend @ addr of preload end
245 mcrr p15, 1, r8, r4, c12 @ preload into icache
246pbegin:
247 /* move into fast relock bypass */
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300248 ldr r8, omap242x_ssp_pll_ctl @ get addr
Tony Lindgren1dbae812005-11-10 14:26:51 +0000249 ldr r5, [r8] @ get val
250 mvn r6, #0x3 @ clear mask
251 and r5, r5, r6 @ clear field
252 orr r7, r5, #0x2 @ fast relock val
253 str r7, [r8] @ go to fast relock
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300254 ldr r4, omap242x_ssp_pll_stat @ addr of stat
Tony Lindgren1dbae812005-11-10 14:26:51 +0000255block:
256 /* wait for bypass */
257 ldr r8, [r4] @ stat value
258 and r8, r8, #0x3 @ mask for stat
259 cmp r8, #0x1 @ there yet
260 bne block @ loop if not
261
262 /* set new dpll dividers _after_ in bypass */
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300263 ldr r4, omap242x_ssp_pll_div @ get addr
Tony Lindgren1dbae812005-11-10 14:26:51 +0000264 str r0, [r4] @ set dpll ctrl val
265
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300266 ldr r4, omap242x_ssp_set_config @ get addr
Tony Lindgren1dbae812005-11-10 14:26:51 +0000267 mov r8, #1 @ valid cfg msk
268 str r8, [r4] @ make dividers take
269
270 mov r4, #100 @ dead spin a bit
271wait_a_bit:
272 subs r4, r4, #1 @ dec loop
273 bne wait_a_bit @ delay done?
274
275 /* check if staying in bypass */
276 cmp r2, #0x1 @ stay in bypass?
277 beq pend @ jump over dpll relock
278
279 /* relock DPLL with new vals */
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300280 ldr r5, omap242x_ssp_pll_stat @ get addr
281 ldr r4, omap242x_ssp_pll_ctl @ get addr
Tony Lindgren1dbae812005-11-10 14:26:51 +0000282 orr r8, r7, #0x3 @ val for lock dpll
283 str r8, [r4] @ set val
284 mov r0, #1000 @ dead spin a bit
285wait_more:
286 subs r0, r0, #1 @ dec loop
287 bne wait_more @ delay done?
288wait_lock:
289 ldr r8, [r5] @ get lock val
290 and r8, r8, #3 @ isolate field
291 cmp r8, #2 @ locked?
292 bne wait_lock @ wait if not
293pend:
294 /* update memory timings & briefly lock dll */
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300295 ldr r4, omap242x_ssp_sdrc_rfr @ get addr
Tony Lindgren1dbae812005-11-10 14:26:51 +0000296 str r1, [r4] @ update refresh timing
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300297 ldr r11, omap242x_ssp_dlla_ctrl @ get addr of DLLA ctrl
Tony Lindgren1dbae812005-11-10 14:26:51 +0000298 ldr r10, [r11] @ get current val
299 mvn r9, #0x4 @ mask to get clear bit2
300 and r10, r10, r9 @ clear bit2 for lock mode
301 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
302 str r10, [r11] @ commit to DLLA_CTRL
303 add r11, r11, #0x8 @ move to dllb
304 str r10, [r11] @ hit DLLB also
305
306 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
307wait_dll_lock:
308 subs r4, r4, #0x1
309 bne wait_dll_lock
310 nop
311 ldmfd sp!, {r0-r12, pc} @ restore regs and return
312
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300313omap242x_ssp_set_config:
Tony Lindgren8e3bd352009-05-25 11:26:42 -0700314 .word OMAP2420_PRCM_CLKCFG_CTRL
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300315omap242x_ssp_pll_ctl:
316 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
317omap242x_ssp_pll_stat:
318 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
319omap242x_ssp_pll_div:
320 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
321omap242x_ssp_sdrc_rfr:
Paul Walmsley44595982008-03-18 10:04:51 +0200322 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300323omap242x_ssp_dlla_ctrl:
Paul Walmsley44595982008-03-18 10:04:51 +0200324 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000325
Tony Lindgrenc2d43e32008-07-03 12:24:38 +0300326ENTRY(omap242x_sram_set_prcm_sz)
327 .word . - omap242x_sram_set_prcm