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Aneesh V7ec94452012-04-27 17:54:05 +05301#
2# Memory devices
3#
4
5menuconfig MEMORY
6 bool "Memory Controller drivers"
7
8if MEMORY
9
10config TI_EMIF
11 tristate "Texas Instruments EMIF driver"
Santosh Shilimkar18e9a972012-05-04 11:38:11 +053012 depends on ARCH_OMAP2PLUS
Aneesh V7ec94452012-04-27 17:54:05 +053013 select DDR
14 help
15 This driver is for the EMIF module available in Texas Instruments
16 SoCs. EMIF is an SDRAM controller that, based on its revision,
17 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
18 This driver takes care of only LPDDR2 memories presently. The
19 functions of the driver includes re-configuring AC timing
20 parameters and other settings during frequency, voltage and
21 temperature changes
22
Ezequiel Garcia3edad322013-04-23 16:21:26 -030023config MVEBU_DEVBUS
24 bool "Marvell EBU Device Bus Controller"
25 default y
26 depends on PLAT_ORION && OF
27 help
28 This driver is for the Device Bus controller available in some
29 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
30 Armada 370 and Armada XP. This controller allows to handle flash
31 devices such as NOR, NAND, SRAM, and FPGA.
32
Hiroshi DOYUc542fb72012-05-10 10:42:30 +030033config TEGRA20_MC
Hiroshi DOYUf0e33f92012-05-11 09:56:24 +030034 bool "Tegra20 Memory Controller(MC) driver"
35 default y
Hiroshi DOYUc542fb72012-05-10 10:42:30 +030036 depends on ARCH_TEGRA_2x_SOC
Hiroshi DOYUf0e33f92012-05-11 09:56:24 +030037 help
38 This driver is for the Memory Controller(MC) module available
39 in Tegra20 SoCs, mainly for a address translation fault
40 analysis, especially for IOMMU/GART(Graphics Address
41 Relocation Table) module.
Hiroshi DOYUc542fb72012-05-10 10:42:30 +030042
Hiroshi DOYUaf468102012-05-10 10:42:32 +030043config TEGRA30_MC
Hiroshi DOYU42d11492012-05-11 09:56:25 +030044 bool "Tegra30 Memory Controller(MC) driver"
45 default y
Hiroshi DOYUaf468102012-05-10 10:42:32 +030046 depends on ARCH_TEGRA_3x_SOC
Hiroshi DOYU42d11492012-05-11 09:56:25 +030047 help
48 This driver is for the Memory Controller(MC) module available
49 in Tegra30 SoCs, mainly for a address translation fault
50 analysis, especially for IOMMU/SMMU(System Memory Management
51 Unit) module.
Hiroshi DOYUaf468102012-05-10 10:42:32 +030052
Aneesh V7ec94452012-04-27 17:54:05 +053053endif